KR0182001B1 - Error position detecting circuit due to clock loss for a cd-rom decoder - Google Patents

Abstract

The present invention relates to a clock-free error position detection circuit in a CD-ROM decoder, which is characterized by the presence of the error and the position of the error as the remainder obtained by dividing the data input from the memory by the generated polynomial. And syndrome S0 and S1 generating means for generating syndromes S0 and S1 whose error values are also calculated through calculation, constant multiplication means for performing a multiplication of the constant α ^K to the syndrome S0, and an alpha constant α to the syndrome S1. Alpha input multiplication means for performing multiplication operation on each constant in parallel from ⁰ to α ^n-1 , and output values of the constant multiplication means are compared with the output values of the constant multiplication means. Parallel comparing means for determining whether the difference is different, and decoding means for finding an error position from the output of the parallel comparing means.

Description

Clock-free error position detection circuit in a CD-ROM decoder.

1 is a block diagram of a conventional error correction circuit.

FIG. 2 is an operation timing diagram illustrating a process of performing error correction on one code word in FIG.

3 is a block diagram showing an embodiment of an error position detection circuit according to the present invention;

4 is an embodiment of the alpha constant multiplier of FIG.

5 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

1: syndrome S0 generator 2: syndrome S1 generator

3: constant multiplier 40, 40A, 40B: alpha constant multiplier

50: parallel comparator 60: decoder

k: Number of codeword symbols n: Number of codeword information symbols

The present invention relates to a clock-free error position detection circuit in a CD-ROM decoder, and more particularly, by modifying an existing error correction scheme used at 1x and 2x speeds, or 8x or later. A clockless error position detection circuit is provided for minimizing the time required for decoding to be applicable to higher speeds.

The error correction circuit of CD-ROM data used in the conventional CD system is used at 1x or 2x speed, and the data inputted from the memory as shown in FIG. 1 is divided by a generator polynomial. Syndrome S0 generator (1) and syndrome S1 generator (2) for generating syndromes S0 and S1, which can know not only the existence of an error but also the position and error value of the error through calculation, and a constant (α ^K ) in the syndrome S0. A constant multiplier (3) for performing constant multiplication with one variable, and a serial multiplier for multiplying the syndrome S1 every clock (α ⁱ ; where α ⁱ is the i-th value below α) (4), a comparator (5) receiving and comparing the signals output from the constant multiplier and the serial multiplier and determining whether the two input values are different, the two syndromes S0 and the syndrome; An error position store 6 for detecting and storing a case where S1 is different, and an error-free detector 7 for detecting a case where both the syndromes S0 and S1 are zero.

Referring to the operation of the conventional error correction circuit of this configuration, the process of reading each symbol in the syndrome S0 generator 1 and the syndrome S1 generator 2 and calculating the syndromes S0 and S1 first reads each symbol of the code word. Requires time (t = a) and finally the syndromes S0 and S1 are determined at the moment the last symbol is read. For example, in the case of the (45,43) RS code, as shown in FIG. 2, 45 symbols are required for one code word, and 45 clock signals are required, and both syndromes (S0 and S1) are not 0. It can be seen that one error has occurred for each symbol. In order to know the error position generated from the syndrome determined in this way, the operation is performed every time by the serial multiplier 4 for each symbol in time, and the value of the operation result Is found through the comparator 5, which also requires at least 45 clock signals. At this time, the process of calculating the syndrome by reading each symbol in the two syndrome S0 generators (1) and the syndrome S1 generator (2) requires reading the symbols from memory one by one in succession. An important factor that determines the decoding speed for correction is the time to find the error position (t = b). In other words, at 1x and 2x speeds, 45 clock signals are needed to read data in the worst case to simplify the hardware, and 45 clock signals are used to find the error position again. This is possible because the decoding time is still sufficient.

However, the CD-ROMs used in CD systems have recently been increasing to 4x and 8x or 12x in the future based on the speed of the first audio CD player. Since time must be reduced inversely, the decoding speed for error correction has become a very important factor in determining the structure of the whole system. For reference, the encoding format of the CD-ROM data used in the current CD system is a cross interleaved encoding method using the (45,43) and (26,24) RS methods in the mode 1 and mode 2 form 1. Is taking. Therefore, error correction is possible not only for random random errors but also for continuous multiple errors. In addition, error correction is possible for a very large amount of errors by repeatedly correcting the cross interleaving method with one error correction method. In the double speed and 8 times speed, it is necessary to reduce this time because it is time-consuming to correct all the data in one sector within a given time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to add an operation function that simplifies the time to find an error location in the shortest time, and as soon as the syndrome is calculated in the state that does not require a clock signal. The present invention provides a clock-free error position detection circuit in a CD-ROM decoder which can reduce the error position detection time so that it can be applied at high speed.

A feature of a clock-free error position detection circuit in a CD-ROM decoder according to the present invention for achieving the above object is a residual value obtained by dividing the data input from the memory by the generated polynomial. Syndrome S0 and S1 generating means for generating syndromes S0 and S1 whose values are also calculated through operation, constant multiplication means for performing multiplication of the constant α ^K to the syndrome S0, and alpha constant α ⁰ to the syndrome S1. alpha constant multiplication means for performing multiplication operation on each constant in parallel up to α ^n-1 , and comparing the output values of the constant multiplication means with each output value of the alpha constant multiplication means And parallel means for determining and decoding means for finding an error position from the output of the parallel means.

Hereinafter, a preferred embodiment of a clock free error position detection circuit in a CD-ROM decoder according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a clock-free error position detection circuit in a CD-ROM decoder according to the present invention. As shown in the drawing, the syndromes S0 and S1 generating means are the remaining values obtained by dividing the data input from the memory by the generated polynomial. Synthesis S0 generator (1) and syndrome S1 generator (2) which generate syndrome S0 and syndrome S1 which can know the presence or absence of error and also the error position and error value are calculated, and a constant multiplication means is the syndrome S0 generator (B) a constant multiplier (3) which multiplies the syndrome S0 made by (1) with a constant (α ^K ; where k is the maximum value of i), and the alpha constant multiplication means is made by the syndrome S1 generator (2). alpha constant in S1 α ⁱ (stage i is a number from 0 to n-1) with respect to the respective constant (a constant of from α ⁰ to α ^n-1) of the alpha constant in parallel α ⁱ (stage i is 0 number of n-1) And a parallel comparator (50) configured to compare the output values of the constant multiplication means with the respective output values of the alpha constant multiplication means, and determine whether two input values are different. It is preferable that the decoding means comprises a decoder 60 for finding an error position from the output of the parallel comparing means.

4 is an example of the alpha constant multiplier of FIG. 3, (a) shows an alpha constant multiplier 40A whose output is S0 by multiplying the syndrome S0 by the alpha constant (α ⁰ = 1), b) implements an alpha constant multiplier 40B in which the output is equal to the input by multiplying the syndrome S0 with an alpha constant (α ¹ = x) using a plurality of exclusive or gates (EX-OR1 to EX-OR4). It is an example. In the case of (a), S0 * α ⁰ is α ⁰ = 1, so the input and output are the same, and in (b) SO * α ¹ is α ¹ = x

FIG. 5 is an operation timing diagram of FIG. 3 showing temporally an error correction process for one code word according to the present invention. FIG. 5 is a period t = a for reading data from memory and a period t for reading error data from memory. = c) and the memory write period (t = d) of the data for which error correction is completed, and as shown in this figure, a period (t = a) of reading data from the memory, a time (t = c) of reading error data, and The error recording time (t = d) is the same as the conventional case, but it can be seen that the time required for error detection is hardly taken.

Referring to the configuration as described above with reference to the operation of the clock-free error position detection circuit in the CD-ROM decoder according to the present invention.

First, the syndromes S0 and S1 are determined at the moment when the last symbol is finally read after the time (t = a) of reading each symbol of the code word from the memory in the syndrome S0 generator 1 and the syndrome S1 generator 2. In the constant multiplier (3), a constant multiplication of the constant (α ^K ) is performed on the syndrome S0 generated by the syndrome S0 generator (1) to produce an output (S0 * α ^K ), and in the alpha constant multiplier (40). Constant multiplication of each constant from α ⁰ to α ⁿ⁻¹ is performed in advance on the syndrome S 1 produced by the syndrome S 1 generator 2 so that an alpha constant α ⁱ is multiplied by each i value. A multiplication output (S1 * α ⁰ , S1 * α ¹ , S1 * α ² ,... S1 * α ⁴⁴ ) can be obtained, and in the parallel comparator 50, each multiplication output value of the alpha constant multiplier 40 is constant. It is determined whether the two input values are different by comparing with the output value of the multiplier (3), The decoder 60 may quickly find an error position by using the output of the parallel comparator 50.

That is, in the present invention, a simple operation function is added in the shortest time to find the error position, so that the position can be known as soon as syndromes S0 and S1 are calculated without requiring a clock. The simple expressions described below are mathematical expressions for deriving this approach.

An example of an error correction code (45,43) RS code is described below.

In case of an error, syndromes S0 and S1 are obtained as follows.

S0 = e (i), S1 = e (i) * α ⁱ = S0 * α ⁱ

As follows: When in the above formula, because S1 = S0 * α ⁱ α ⁱ is transferred to the left-hand side hayeoteul a constant multiplied by α ^K.

S1 * α ^k-1 = S0 * α ^K , where the variable i is a position where an error occurs and has a size from 0 to 44 since the (45,43) RS code, and k is 44, the maximum value of i.

In the above formula, if the first data input from the memory is the most significant symbol, the position of the actual error that satisfies the formula is (k-i + 1). Therefore, by substituting all i's from 0 to 44 by finding an error location, if i finds a satisfying i value, the actual error location becomes (k-i + 1). Therefore, in the present invention, the alpha constant multiplier 40 does not use a clock in parallel to calculate the magnitude (S1 * α ⁴⁴ , S1 * α ⁴³ , S1 * α ⁴² ,... S1 * α ⁰ ) corresponding to each i value in parallel. By calculating in advance, the parallel comparator 50 also compares the output of the constant multiplier 3 and the output of the alpha constant multiplier 40 without using a clock, so that an error position can be immediately found and quick error correction can be performed. do.

In order to calculate the syndrome in memory from the above equation, the magnitude of k-i + 1 represents the current error position in order of reading. 45 clocks are required because the comparison is performed for each clock. However, in the present invention, when one error occurs, each of the pre-calculated result values S1 * α ⁰ , S1 * α ¹ , S1 * α ² ,... … Since any one of the values of S1 * α ⁴⁴ will be necessarily equal to the syndrome S0 * α ^k , the error position can be finally obtained using the value corresponding to the position according to the comparison result in the parallel comparator 50. Will be.

As described above, according to the clock-free error position detection circuit according to the present invention, not only the error position can be found in a state where the structure is simple but does not require a clock, and each alpha constant multiplier is also shown in FIG. Since only 8 or 12 exclusive orgates are needed, there is no burden in terms of hardware, so there is a usefulness that can be easily applied.

Claims (1)

And the generating means S0 and S1 for generating syndromes S0 and S1, which are known through the operation, as the remaining values obtained by dividing the data input from the memory by the polynomial, and the position and error value of the error, and the syndrome S0. Constant multiplication means for performing multiplication on a constant α ^k , alpha constant multiplication means for performing multiplication operation on each constant in parallel from the alpha constant α ⁰ to α ^n-1 on the syndrome S1, and the alpha Each output value of the constant multiplication means is compared with the output value of the constant multiplication means by means of parallel comparison means for determining whether two input values are different, and decoding means for finding the error position from the output of the parallel comparison means No-clock error position detection circuit.