KR0180134B1 - Twin wall forming method - Google Patents
Twin wall forming method Download PDFInfo
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- KR0180134B1 KR0180134B1 KR1019950005643A KR19950005643A KR0180134B1 KR 0180134 B1 KR0180134 B1 KR 0180134B1 KR 1019950005643 A KR1019950005643 A KR 1019950005643A KR 19950005643 A KR19950005643 A KR 19950005643A KR 0180134 B1 KR0180134 B1 KR 0180134B1
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- conductive
- selective epitaxial
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Abstract
본 발명은 CMOS의 N-웰 및 P-웰, 즉 트윈 웰을 형성하는 방법에 관한 것으로, N-웰 및 P-웰 이온주입 마스크의 정렬을 별도의 얼라인 마크를 사용하지 않고 자기정렬 방식으로 정렬하여 공정의 단순화, 소자의 특성 및 공정 수율을 향상시키는 효과가 있다.The present invention relates to a method for forming N-well and P-well, i.e., twin wells of CMOS, wherein the alignment of the N-well and P-well implantation masks is performed in a self-aligning manner without using separate alignment marks. Alignment has the effect of simplifying the process, improving the device properties and process yield.
Description
제1a도 내지 제1d도는 종래기술에 따른 트윈웰 형성 공정도.1a to 1d is a twin well forming process according to the prior art.
제2a도 내지 제2d도는 본 발명의 일실시예에 따른 트윈 헬 형성 공정도.2a to 2d is a twin hell forming process according to an embodiment of the present invention.
제3a도 내지 제3d도는 본 발명의 다른 실시예에 따른 트윈 헬 형성 공정도.3a to 3d is a twin hel formation process according to another embodiment of the present invention.
제4a도 내지 제4d도는 본 발명의 또 다른 실시예에 따른 트윈 헬 형성 공정도.4a to 4d is a twin hell forming process according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21, 31, 41 : 실리콘 기판 22, 25, 32, 35, 42 : 산화막21, 31, 41: silicon substrate 22, 25, 32, 35, 42: oxide film
23 : 질화막 24, 44 : P-웰 마스크 패턴23 nitride film 24, 44 P-well mask pattern
26, 36 : 선택적 에피택셜 실리콘층 27, 37 : P-웰26, 36: selective epitaxial silicon layer 27, 37: P-well
33, 43 : N-웰 마스크 패턴 34 : 트렌치33, 43: N-well mask pattern 34: trench
43' : 잔류 감광막 45 : N-웰43 ': residual photoresist 45: N-well
46 : P-웰46: P-well
본 발명은 반도체소자 제조 공정중 N-웰(Well) 및 P-웰로 이루어지는 트윈(Twin)웰을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a twin well consisting of N-well and P-well during a semiconductor device manufacturing process.
반도체 제조 공정에서 웰 형성방법은 씨모스(CMOS)가 주종을 이룸으로써, N-MOS를 위한 P-웰,P-MOS를 위한 N-웰을 반도체 기판에 형성하는 트윈 웰 형성 방법은 보편화되었다.In the semiconductor manufacturing process, CMOS is mainly used as a method of forming a well, and thus, a twin well forming method for forming a P-well for N-MOS and an N-well for P-MOS on a semiconductor substrate has become popular.
제1a도 내지 제1d도를 통해 종래의 트윈 웰 형성방법을 살펴본다.A first twin well forming method will be described with reference to FIGS. 1A to 1D.
먼저, 제1a도는 반도체 기판(11)상에 얇은 산화막(12) 성장 및 감광막(13)을 도포한 상태로서, 감광막은 차후에 형성되는 N-웰 및 P-웰 마스크 패턴의 얼라인 마크 형성을 위한 얼라인 마크 마스크 패턴 형성용이며, 이때, 얼라인 키는 통상적으로, 웨이퍼의 스크라이브 라인 또는 빈 공간 등에 형성됨으로 도면에는 도시되지 않았다.First, FIG. 1A is a state in which a thin oxide film 12 is grown on the semiconductor substrate 11 and a photoresist film 13 is applied, and the photoresist film is used for forming alignment marks of the N-well and P-well mask patterns formed later. It is for forming an alignment mark mask pattern, in which an alignment key is typically formed on a scribe line or an empty space of a wafer, which is not shown in the drawing.
이어서, 제1b도와 같이 감광막(13)을 제거한 후, 다시 사진식각공정을 통해 N-웰 마스크 패턴(14)을 형성하고 N-타입 불순물인 인(P)을 이온주입한다.Subsequently, after removing the photosensitive film 13 as shown in FIG. 1B, an N-well mask pattern 14 is formed through photolithography again, and phosphorus (P), an N-type impurity, is implanted.
이어서, 제1c와 같이 N-웰 마스크 패턴(14)을 제거하고, 다시 사진식각공정을 통해 P-웰 마스크 패턴(15)을 형성하고 P-형 불순물인 붕소(B)를 이온주입한다.Subsequently, the N-well mask pattern 14 is removed as in FIG. 1C, and the P-well mask pattern 15 is formed again through a photolithography process, and boron (B), a P-type impurity, is implanted.
계속해서, 제1d도는 P-웰 마스크 패턴(15)을 제거하고 이온주입 불순물 확산인 드라이버 인(drive in)을 위한 열공정 후, 산화막(12)을 제거한 상태로서, N-웰(17) 및 P-웰(16), 즉 트윈 웰이 형성되어 있다.Subsequently, FIG. 1D is a state in which the oxide film 12 is removed after the thermal process for removing the P-well mask pattern 15 and driving the ion implanted impurity diffusion into the N-well 17 and P-wells 16, ie twin wells, are formed.
상기와 같은 종래의 트윈 웰 형성 방법은 사진식각공정을 세번씩이나 실시해야 하며,N-웰 마스크 패턴 및 P-웰 마스크 패턴은 자기정렬방식이 아니고 얼라인 키에 정렬해야 하는 문제점이 있어, 제1d도와 같이 미스 얼라인시 N-웰 및 P-웰의 경계부위가 겹치게 된다.The conventional twin well forming method as described above has to perform the photolithography process three times, and the N-well mask pattern and the P-well mask pattern are not self-aligned but have to be aligned to the alignment key. As shown in FIG. 1d, the boundary portions of the N-well and the P-well overlap when the misalignment occurs.
또한, 이후의 공정에서 N-웰 또는 P-웰 어느 한쪽에 집중적으로 공정이 이루어져 어느 한쪽에 높은 토폴로지(topology)가 형성되게 된다.In addition, in a subsequent process, the process is concentrated on either the N-well or the P-well to form a high topology on either side.
따라서, 본 발명은 N-웰 및 P-웰을 자기정렬방식으로 형성하고 기판의 토폴로지를 완화하는 트윈 웰 방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a twin well method for forming N-wells and P-wells in a self-aligning manner and relaxing the topology of a substrate.
상기 목적을 달성하기 위하여 본 발명은, 반도체소자 제조방법에 있어서, 반도체기판 상에 제1산화막과 기판산화방지막을 차례로 형성하는 제1단계; 상기 기판산화방지막 상에 제1도전형-웰 마스크 패턴을 형성하는 제2단계; 노출된 상기 기판산화방지막을 식각하고, 제1도전형 불순물을 이온주입하는 제3단계; 상기 제1도전형-웰 마스크 패턴을 제거하고 상기 제1도전형 불순물을 열공정으로 드라이브 인(drive in)하여 제1도전형-웰을 형성하는 제4단계; 열공정으로 상기 기판산화방지막이 오픈된 영역의 상기 반도체기판을 산화시켜 제2산화막을 형성하는 제5단계; 상기 기판산화막과 그 하부의 상기 제1산화막을 제거하는 제6단계; 및 상기 제2산화막에 의해 오픈된 영역의 상기 반도체기판에 제2도전형의 불순물이 도핑된 선택적 에피택셜막을 형성하여 제2도전형-웰을 형성하는 제7단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor device manufacturing method comprising: a first step of sequentially forming a first oxide film and a substrate antioxidant film on a semiconductor substrate; A second step of forming a first conductive well mask pattern on the substrate antioxidant layer; A third step of etching the exposed substrate anti-oxidation film and ion implanting a first conductivity type impurity; A fourth step of removing the first conductive well mask pattern and driving the first conductive impurities into a thermal process to form a first conductive well; A fifth step of forming a second oxide film by oxidizing the semiconductor substrate in a region in which the substrate anti-oxidation film is opened by a thermal process; A sixth step of removing the substrate oxide film and the first oxide film under the substrate oxide film; And a seventh step of forming a second conductive type well by forming a selective epitaxial layer doped with a second type of impurity on the semiconductor substrate in the region opened by the second oxide layer. .
또한 본 발명은, 반도체소자 제조방법에 있어서, 반도체기판 상에 제1산화막을 형성하는 제1단계; 상기 반도체기판에 제1도전형 불순물을 이온주입하는 제2단계; 상기 제1산화막 상에 제2도전형-웰 마스크 패턴을 형성하는 제3단계; 노출된 상기 제1산화막을 식각하고, 상기 제1산화막 식각에 의해 노출된 상기 반도체기판을 식각하여 트렌치를 형성하는 제4단계; 상기 제2도전형-웰 마스크 패턴을 제거하고 열공정으로 상기 제2단계에서 이온주입된 제1도전형 불순물을 드라이브-인하여 제1도전형-웰을 형성하는 제5단계; 상기 트렌치 부위의 반도체 기판 측벽에 스페이서 제2산화막을 형성하는 제6단계; 및 상기 제1 및 제2산화막으로 덮히지 않는 트렌치 부위의 상기 반도체기판 상에 상기 제2도전형 불순물이 도핑된 선택적 에피택셜막을 형성하여 제2도전형-웰을 형성하는 제7단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention also provides a semiconductor device manufacturing method comprising: a first step of forming a first oxide film on a semiconductor substrate; A second step of ion implanting a first conductivity type impurity into the semiconductor substrate; Forming a second conductive well mask pattern on the first oxide layer; Etching the exposed first oxide film and etching the semiconductor substrate exposed by the first oxide film etching to form a trench; A fifth step of removing the second conductive-well mask pattern and forming a first conductive well by driving-in the first conductive impurity implanted in the second step by a thermal process; A sixth step of forming a spacer second oxide film on sidewalls of the semiconductor substrate in the trench region; And a seventh step of forming a second conductive type well by forming a selective epitaxial layer doped with the second conductive type impurity on the semiconductor substrate in the trench portion not covered with the first and second oxide layers. Characterized in that made.
여기서, 바람직하게 상기 선택적 액피택셜막은 상기 트렌치 깊이보다 낮은 두께로 형성되는 것을 특징으로 한다.Here, preferably, the selective epitaxial layer is formed to a thickness lower than the depth of the trench.
또한, 본 발명은, 반도체소자 제조방법에 있어서, 반도체기판 상에 제1산화막을 형성하는 제1단계; 상기 제1산화막 상에 제1도전형-웰 마스크 패턴으로서 제1감광막 패턴을 형성하는 제2단계; 제1도전형 불순물을 이온주입하는 제3단계; 상기 제1감광막 패턴의 전체두께중 일부를 제거하여 잔류 제1감광막을 남기는 제4단계; 상기 잔류 제1감광막을 하드 베이킹하는 제5단계; 사진식각공정으로 제2도전형-웰 마스크 패턴으로서 제2감광막 패턴을 형성하는 제6단계; 상기 제2도전형 불순물을 이온주입하는 제7단계; 상기 잔류 제1감광막 및 제2감광막 패턴을 제거하는 제8단계; 및 열공정으로 상기 이온주입된 불순물을 드라이브 인하는 제9단계를 포함하여 이루어지는 것은 특징으로 한다.The present invention also provides a semiconductor device manufacturing method comprising: a first step of forming a first oxide film on a semiconductor substrate; Forming a first photoresist layer pattern on the first oxide layer as a first conductive well mask pattern; A third step of ion implanting first conductive impurities; A fourth step of leaving a remaining first photoresist film by removing a part of the overall thickness of the first photoresist pattern; A fifth step of hard baking the residual first photoresist film; A sixth step of forming a second photoresist pattern as a second conductive-well mask pattern by a photolithography process; A seventh step of ion implanting the second conductive impurity; An eighth step of removing the residual first photoresist film and the second photoresist film pattern; And a ninth step of driving-in the ion-implanted impurities by a thermal process.
여기서, 바람직하게 상기 잔류 제2감광막은 제7단계에서 이온주입되는 불순물이 상기 반도체기판에 이온주입된 정도의 두께를 갖는 것을 특징으로 한다.Here, preferably, the remaining second photoresist layer has a thickness such that an impurity implanted in the seventh step is implanted into the semiconductor substrate.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예들을 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
제2a도 내지 제2d도는 본 발명의 일실시예에 따른 트윈 웰 형성 공정도로서, 제2a도는 실리콘 기판(21)상에 산화막(22) 및 질화막(23)을 차례로 형성한 다음, 사진식각공정으로 P-웰 마스크 패턴(24)을 형성하고, 노출된 질화막(23)을 제거하고 P-형 불순물을 이온주입하는 상태이다.2A to 2D are diagrams illustrating a twin well forming process according to an embodiment of the present invention, and FIG. 2A illustrates an oxide film 22 and a nitride film 23 sequentially formed on a silicon substrate 21 and then a photolithography process. The P-well mask pattern 24 is formed, the exposed nitride film 23 is removed, and P-type impurities are ion implanted.
이어서, 제2b도와 같이 P-웰 마스크 패턴(24)을 제거한 후, 열공정으로 P-형 불순물을 드라이브 인 (drive in)하여 P-웰(27)을 형성하고, 열공정으로 산화막(25)을 형성하는데, 이때, 산화막(25)은 P-웰 (27)지역에만 형성되고 질화막(23)으로 덮힌 N-웰 지역은 산화막(25)이 형성되지 않는다.Subsequently, after removing the P-well mask pattern 24 as shown in FIG. 2B, the P-well 27 is formed by driving P-type impurities in a thermal process to form the P-well 27, and the oxide film 25 is thermally processed. In this case, the oxide film 25 is formed only in the P-well 27 region, and the oxide film 25 is not formed in the N-well region covered by the nitride film 23.
이어서, 제2c도와 같이 질화막(23) 및 산화막(22)을 제거한 후, 가스로 PH3도핑 조절된 선택적 에피택셜 실리콘층(26)을 3-4㎛ 두께로 성장시키는데, 이때 선택적 에피택셜 실리콘층(26)은 N-형 불순물인 인이 도핑됨으로 N-웰을 이루게 된다.Subsequently, after removing the nitride film 23 and the oxide film 22 as shown in FIG. 2C, the selective epitaxial silicon layer 26 which is doped with gas and controlled to pH 3 is grown to a thickness of 3-4 μm, wherein the selective epitaxial silicon layer is Reference numeral 26 denotes an N-well by being doped with phosphorus, an N-type impurity.
끝으로, 제 2d도는 P-웰(27)상의 산화막(25)을 제거한 상태이다.Lastly, in FIG. 2D, the oxide film 25 on the P-well 27 is removed.
본 발명은 일실시예에서 N-웰을 이온주입에 의해 형성하고 P-웰을 선택적 에피택셜 실리콘층으로 형성하여, 보다 P-MOS 보다 상대적으로 래치업에 취약한 N-MOS의 래치업 문제를 효과적으로 방지할 수 있다. 이때, P-웰은 B2H6가스로 도핑 조절된 선택적 에피택셜 실리콘층으로 형성한다.In one embodiment, the N-well is formed by ion implantation and the P-well is formed of a selective epitaxial silicon layer to effectively solve the latch-up problem of N-MOS, which is more susceptible to latchup than P-MOS. It can prevent. At this time, the P-well is formed of a selective epitaxial silicon layer doped with B 2 H 6 gas.
그리고, 얼라인 키와 형성 공정이 필요 없는 자기정렬 방식으로 트윈 웰이 형성되며, N-웰 또는 P-웰 어느 한쪽의 단차가 낮으므로, 단차가 낮은 쪽에 집중적으로 공정이 이루어짐으로써 발생하는 토폴로지의 심화를 방지한다.In addition, since the twin well is formed by a self-aligning method that does not require the alignment key and the forming process, and the step difference of either the N-well or the P-well is low, the topology generated by intensively processing the step is lowered. Prevent deepening
제3a도 내지 제3d도는 본 발명의 다른 실시예에 따른 트윈 웰 형성 공정도로서,제3a도는 실리콘 기판(31)상에 산화막(32)을 형성하고 P-웰을 형성하기 위한 P-형 불순물인 붕소(B)를 이온주입하는 상태이다. 이때,P-웰 마스크 패턴을 형성하지 않는 이유는 후속공정에서 N-웰 지역의 실리콘 기판이 식각되기 때문이다.3A to 3D are diagrams illustrating a twin well forming process according to another embodiment of the present invention, and FIG. 3A is a P-type impurity for forming an oxide film 32 and forming a P-well on a silicon substrate 31. In this state, ion implantation of boron (B) is carried out. At this time, the reason why the P-well mask pattern is not formed is because the silicon substrate in the N-well region is etched in a subsequent process.
이어서, 제 3b도와 같이 사진식각공정으로 N-웰 마스크 패턴(33)을 형성하고 노출된 N-웰 지역의 산화막(32)을 제거한 후 실리콘 기판(31)을 3㎛정도 식각하여 트렌치(34)를 형성한다.Subsequently, as illustrated in FIG. 3B, the N-well mask pattern 33 is formed by a photolithography process, the oxide layer 32 in the exposed N-well region is removed, and the silicon substrate 31 is etched by about 3 μm to form the trench 34. To form.
이어서, 제3c도와 같이 N-웰 마스크 패턴(33)을 제거하고, 열공정으로 P-형 불순물 드라이브-인 공정을 실시하여 P-웰(37)을 형성한후,산화막 증착후 다시 산화막을 비등방성 전면식각하여 실리콘 기판의 트렌치 식각 측벽 부위에 산화막(35)을 형성한 다음,PH3가스로 도핑 조절된 선택적 에피택셜 실리콘층(36)을 3㎛정도 성장시킨다. 이때, 선택적 에피택셜 실리콘층(36)은 N-형 불순물이 도핑됨으로 N-웰을 이루게 된다.Subsequently, as shown in FIG. 3C, the N-well mask pattern 33 is removed, a P-type impurity drive-in process is performed in a thermal process to form the P-well 37, and after the deposition of the oxide film, the oxide film is rained again. After the isotropic surface etching, the oxide layer 35 is formed on the trench etch sidewall of the silicon substrate, and then the selective epitaxial silicon layer 36 doped with PH 3 gas is grown to about 3 μm. In this case, the selective epitaxial silicon layer 36 forms an N-well by being doped with N-type impurities.
끝으로, 제3d도는 P-웰(37) 상의 산화막(32)을 제거한 상태이다.Finally, FIG. 3D is a state in which the oxide film 32 on the P-well 37 is removed.
본 발명의 다른 실시예에서 N-웰을 이온주입에 의해 형성하고 P-웰을 선택적 에피택셜 실리콘층으로 형성하여, P-MOS 보다 상대적으로 래치업에 취약한 N-MOS의 래치업 문제를 효과적으로 방지할 수 있으며, 또한, 트렌치 식각 깊이 보다 낮게 선택적 에피택셜 층을 형성하여 N-웰과 P-웰의 단차를 다르게 형성하여, 이후의 공정에서 어느 한쪽으로 공정이 집중되어 토폴로지가 심화되는 것을 방지할 수 있다. 그리고, 얼라인 키 형성을 위한 사진식각공정 및 N-웰 마스크 형성을 위한 사진식각공정이 필요없어 공정산소화 및 비용절감을 가져온다.In another embodiment of the present invention, the N-well is formed by ion implantation and the P-well is formed of a selective epitaxial silicon layer, effectively preventing the latch-up problem of N-MOS, which is relatively more susceptible to latchup than P-MOS. In addition, by forming a selective epitaxial layer lower than the depth of the trench etching to form a step difference between the N-well and the P-well, it is possible to prevent the process from concentrating on either side and deepening the topology. Can be. In addition, there is no need for a photolithography process for forming an alignment key and a photolithography process for forming an N-well mask, resulting in process oxygenation and cost reduction.
제4a도 내지 제4d도는 본 발명의 또 다른 실시예에 따른 트윈 웰 형성 공정도로서, 제4a도는 실리콘 기판(41)상에 얇은 산화막(42)을 형성하고, 사진식각공정으로 감광막인 N-웰 이온주입 마스크 패턴(43)을 형성한 후,N-형 불순물 이온을 이온주입하는 상태를 나타낸다.4A to 4D are diagrams illustrating a twin well forming process according to still another embodiment of the present invention. FIG. 4A is a thin oxide film 42 formed on a silicon substrate 41, and an N-well as a photoresist film by a photolithography process. After the ion implantation mask pattern 43 is formed, the state of ion implantation of N-type impurity ions is shown.
이어서, 제4b도와 같이 상기 N-웰 이온주입 마스크 패턴(43)을 제거하되, 전체두께중 1/3내지 1/4의 감광막(43')을 잔류시킨 후, 하드 베이크 공정으로 잔류 감광막(43')을 탄소화 한 다음, 사진식각공정으로 P-웰 이온주입 마스크(44)를 형성하고 P-형 불순물인 붕소(B)이온주입한다.Subsequently, the N-well ion implantation mask pattern 43 is removed as shown in FIG. 4B, but 1/3 to 1/4 of the overall thickness of the photoresist film 43 'is left, and the remaining photoresist film 43 is then subjected to a hard bake process. After carbonization of '), a P-well ion implantation mask 44 is formed by a photolithography process, and boron (B) ion, which is a P-type impurity, is implanted.
이때, 붕소가 P-웰의 얇은 잔류 감광막(43') 및 산화막(42)을 뚫고 이온주입되며 N-웰 쪽은 두꺼운 감광막(P-웰 이온주입 마스크,44)을 뚫지 못하고 이온주입되지 못한다.At this time, boron is implanted through the thin residual photoresist film 43 'and the oxide film 42 of the P-well, and the N-well side is not penetrated through the thick photoresist film (P-well ion implantation mask 44) and cannot be ion implanted.
이어서, 제4c도와 같이 P-웰 이온주입 마스크(44) 및 잔류 감광막(43')을 제거하고, 제4d도와 같이 산화막(42)을 제거한 후, 열공정을 통한 불순물 드라이브 인 공정을 실시하여 N-웰(45) 및 P-웰(46)을 형성한다.Subsequently, the P-well ion implantation mask 44 and the residual photoresist film 43 'are removed as shown in FIG. 4C, the oxide film 42 is removed as shown in FIG. 4D, and then an impurity drive-in process is performed through a thermal process to form N. -Well 45 and P-well 46 are formed.
본 발명의 또다른 실시예에서, 잔류 감광막(43')은 P-웰 이온주입 마스크 패턴(44)형성시의 얼라인 마크 역할을 하게 되어, 별도의 얼라인 키의 형성 공정이 필요없는 자기정렬 방식으로 트윈 웰이 형성된다.In another embodiment of the present invention, the residual photoresist film 43 'serves as an alignment mark when forming the P-well ion implantation mask pattern 44, thereby eliminating the need for a separate alignment key forming process. Twin wells are formed in this manner.
이상, 상기 설명과 같이 이루어지는 본 발명은 자기정렬 방식으로 트윈 웰이 형성되어 소자의 특성 및 공정 수율을 향상시키는 효과를 가져온다.As described above, the present invention made as described above has the effect of improving the characteristics and process yield of the device by forming a twin well in a self-aligned manner.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
Claims (11)
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| KR1019950005643A KR0180134B1 (en) | 1995-03-17 | 1995-03-17 | Twin wall forming method |
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| KR100817417B1 (en) * | 2006-12-26 | 2008-03-27 | 동부일렉트로닉스 주식회사 | High voltage cmos device and the fabricating method thereof |
| DE102016119962A1 (en) | 2015-12-16 | 2017-06-22 | Hyundai Motor Company | Motor synchronization device and control method thereof |
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1995
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100817417B1 (en) * | 2006-12-26 | 2008-03-27 | 동부일렉트로닉스 주식회사 | High voltage cmos device and the fabricating method thereof |
| DE102016119962A1 (en) | 2015-12-16 | 2017-06-22 | Hyundai Motor Company | Motor synchronization device and control method thereof |
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