KR0179916B1 - Input buffer - Google Patents

Abstract

The present invention relates to an input buffer circuit, which aims to improve noise margin and improve electrostatic discharge (ESD) and latch up by not forming parasitic bipolar transistors. The object of the present invention is that the PMOS transistor (MP1), the gate is applied to the input signal (IN), the source is applied to the power supply voltage (VDD), the gate is applied to the input signal (IN), the source is the PMOS A PMOS transistor MP2 connected to the drain of the transistor MP1, an NMOS transistor MN2 having a gate applied with an input signal IN, and a drain connected to a drain of the PMOS transistor MP2; An NMOS transistor MN1 having a gate applied with an input signal IN, a drain connected to a source of the NMOS transistor MN2, and a source connected to ground GND, and a gate connected to an input signal IN. Dre An NMOS transistor MN3 connected to the drain of the PMOS transistor MP1 and the source of the PMOS transistor MP2, the source of which is connected to the ground GND, and the gate applies an input signal IN. And a drain is connected to the source of the NMOS transistor MN2 and the drain of the NMOS transistor MN1, and the source is formed of a PMOS transistor MP3 to which a power supply voltage VDD is applied. Is achieved by implementing an input buffer circuit comprising a first inverting unit for inverting and outputting the second inverting unit and an inverter (X1) for inverting and outputting the first inverting unit again.

Description

Input buffer circuit

1 is a conventional input buffer circuit diagram.

2 shows parasitic bipolar transistors in FIG.

(a) is a layout diagram of a PMOS transistor,

(b) is a layout diagram of an NMOS transistor.

3 shows a spice simulation characteristic of a conventional input buffer circuit.

4 is an input buffer circuit diagram of the present invention.

Figure 5 shows the spice simulation characteristics of the input buffer circuit of the present invention.

* Explanation of symbols for main parts of the drawings

110: first inverted portion 120: second inverted portion

MN1-MN3: NMOS transistor MPI-MP3: PMOS transistor

X1: Inverter

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an input buffer circuit, in particular an input that is suitable for improving electrostatic discharge (ESD) and latch up by improving noise margin and not forming parasitic bipolar transistors. Buffer circuit

In the conventional input buffer circuit, as shown in FIG. 1, the PMOS transistor MP1 receives the input signal IN and the source receives the power supply voltage VDD, and the gate receives the input signal IN. PMOS transistor MP2 whose source is connected to the drain of the PMOS transistor MP1 and a gate whose input is applied to the input signal IN and whose drain is connected to the drain of the PMOS transistor MP2 An MOS transistor MN2, an NMOS transistor MN1 having a gate connected to a source of the NMOS transistor MN2 having a gate applied with an input signal IN, and a source thereof connected to a ground GND; Is connected to the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2, and the source is connected to the drain of the PMOS transistor MP1 and the source of the PMOS transistor MP2. grounding( A PMOS transistor MP3 connected to a GND, a gate connected to a drain of the PMOS transistor MP2 and a drain of the NMOS transistor MN2, and a source of the PMOS transistor MP3 connected to a GND. A first inverting unit 10 which is connected to the drain of the NMOS transistor MN1 and whose drain is connected to the power supply voltage VDD to invert and output the input signal IN, and an inverter And a second inverting unit 20 configured to generate an output signal OUT by inverting the output of the first inverting unit 10 again.

Referring to the operation of the conventional input buffer circuit as follows.

First, when the input signal IN is high, the NMOS transistors MN1 and MN2 of the first inverting unit 10 are turned on and the PMOS transistors MP1 and MP2 are turned off.

Thus, node A goes low, which is applied to the gates of PMOS transistor MP3 and NMOS transistor MN3.

That is, the conventional input buffer circuit forms a feedback loop.

The low signal output from the first inverting unit 10 is inverted again by the inverter X1 of the second inverting unit 20 to output high as the output signal OUT.

On the other hand, when the input signal IN is low, the PMOS transistors MP1 and MP2 are turned on and the NMOS transistors MN1 and MN2 are turned off.

Therefore, the node A becomes high, which is applied to the gates of the PMOS transistor MP3 and the NMOS transistor MN3 to form a feedback loop, and then the first inverting portion (2) in the second inverting portion 20 is formed. The high signal of 10) is inverted again to output low as the output signal OUT.

However, the conventional input buffer circuit generates a parasitic bipolar transistor, which will be described with reference to the layout of FIG.

As shown in FIG. 2, parasitic bipolar transistors are formed between two MOS transistors.

(A) of FIG. 2 shows parasitic bipolar transistors between PMOS transistors, and (b) shows parasitic bipolar transistors between NMOS transistors.

Therefore, when the PMOS transistor MP3 and the NMOS transistor MN3 are implemented in the CMOS layout, parasitic bipolar transistors are formed, which adversely affects the electrostatic discharge (ESD) and the latch up. The problem arises.

3 shows the input / output characteristics of the conventional input buffer circuit as a result of Spice simulation, and the difference of the trigger point when the input transitions from low to high and from high to low Will be much better.

Therefore, there is a problem that noise margin is limited when used as a digital input buffer.

As described above, the conventional input buffer circuit has a limitation in noise margin and adversely affects the sides of the electrostatic discharge (ESD) and the latch up.

The present invention was devised to solve the conventional problems as described above. The present invention improves noise margin and improves electrostatic discharge (ESD) and latch up by not forming parasitic bipolar transistors. The purpose is to provide an input buffer circuit capable of doing so.

As shown in FIG. 4, the input buffer circuit according to the present invention includes the first inverting unit 110 for inverting and outputting the input signal IN, and the inverter X1. The second inverting unit 120 is configured to invert and output the output of the first inverting unit 110 again.

The first inverting unit 110 includes a PMOS transistor MP1 having a gate applied with an input signal IN and a source having a power supply voltage VDD, a gate having an input signal IN, and a source having the source. A PMOS transistor MP2 connected to the drain of the PMOS transistor MP1, an NMOS transistor MN2 connected to a drain of the PMOS transistor MP2 with a gate applied with an input signal IN, and a drain connected to the drain of the PMOS transistor MP2. The NMOS transistor MN1 is connected to the source of the NMOS transistor MN2 and the drain thereof is connected to the ground GND. The gate is the input signal IN. The NMOS transistor MN3 is connected to the drain of the PMOS transistor MP1 and the source of the PMOS transistor MP2, the source of which is connected to the ground GND, and the gate is input signal. (IN) and the drain is the enmo The PMOS transistor MP3 is connected to the source of the switch transistor MN2 and the drain of the NMOS transistor MN1, and the source of which is applied to the power supply voltage VDD.

As described above, the operation and effects of the input buffer circuit of the present invention are configured such that a feedback loop is not formed between the input and the output, and the gates of the NMOS transistor MN3 and the PMOS transistor MP3 are directly connected to the input signal IN. It will be described in detail as follows.

First, when the input signal IN is high, the NMOS transistors MN1, MN2, and MN3 of the first inverting unit 110 are turned on and the PMOS transistors MP1, MP2, and MP3 are turned off.

Therefore, the node A becomes low, which is inverted again by the inverter X1 of the second inverting unit 120 to output high as the output signal OUT.

On the other hand, when the input signal IN is low, the PMOS transistors MP1, MP2, and MP3 of the first inverting unit 110 are turned on and the NMOS transistors MN1, MN2, and MN3 are turned off so that the node A is turned off. High, which is inverted again by the inverter X1 of the second inverting unit 120 to output a low as the output signal OUT.

FIG. 5 shows the input / output characteristics of the input buffer circuit of the present invention operating as described above by SPICE Simu1ation, when the input transitions from low to high and transitions from high to low as compared to the conventional input buffer circuit. When the difference between the trigger point (Trigger point) is significantly reduced, the noise margin is remarkably improved.

In addition, in the present invention, since the PMOS transistor is not directly connected to the ground GND or the NMOS transistor is directly connected to the power supply voltage VDD, the parasitic bipolar transistor as shown in FIG. 2 is not formed.

Therefore, in consideration of the CMOS layout, there is an effect that the electrostatic discharge (ESD) and latch up are improved.

As described above, the present invention has an effect of improving noise margin and improving electrostatic discharge (ESD) and latch up.

Claims (1)

PMOS transistor MP1 has a gate applied with an input signal IN and a source applied with a power supply voltage VDD, and gate has an input signal IN, and a source has been applied to a drain of the PMOS transistor MP1. PMOS transistor MP2 connected to the gate, NMOS transistor MN2 connected to the drain of the PMOS transistor MP2 having a gate applied with the input signal IN, and a gate connected to the input signal IN. An NMOS transistor MN1 having an applied and drain connected to the source of the NMOS transistor MN2, the source of which is connected to ground GND, a gate applied to an input signal IN, and a drain thereof being the PMOS transistor An NMOS transistor MN3 connected to the drain of MP1 and the source of the PMOS transistor MP2, the source of which is connected to ground GND, a gate of which receives an input signal IN, and a drain of the NMOS transistor MN3. Of the MOS transistor MN2 Switch and the NMOS transistor is connected to the drain of the (MN1) the source of the first reversing portion configured to receive a supply power voltage (VDD) PMOS transistor (MP3) (110) and; A second inverting unit 120 including an inverter X1 that receives a signal output from a common connection point of the drain of the PMOS transistor MP2 and the NMOS transistor MN2 of the first inverting unit 110 and inverts it. Input buffer circuit, characterized in that consisting of).