KR0150227B1 - Input circuit - Google Patents

Abstract

The input circuit according to the invention comprises a pseudo latch circuit for latching the level of the output signal to an appropriate level. The pseudo latch circuit is selected from first and second circuit configurations that depend on the timing at which noise occurs. The first configuration consists of two p-MOS transistors connected between the Vcc power supply and the selected node, and the second configuration consists of two n-MOS transistors connected between the node and ground.

Description

Input circuit

1 is a circuit diagram showing a conventional input circuit.

2A and 2B are timing diagrams showing the operation of a conventional input circuit.

3 is a circuit diagram showing an input circuit of a first embodiment according to the present invention.

4 is a timing diagram showing the operation of the first embodiment.

5 is a circuit diagram showing an input circuit of a second embodiment according to the present invention.

6 is a timing diagram showing the operation of the second preferred embodiment.

* Explanation of symbols for main parts of the drawings

10, 30, and 50: input circuit 12: input inverter

14: output inverters 16, 32, and 52: pseudo latch circuit

18, 22, 24, 34 and 36: p-MOS transistors

20, 28, 29, 54 and 56: n-MOS transistors

26: inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to input circuits for semiconductor ICs (integrated circuits), and more particularly, to input circuits having an artificial latch circuit for preventing malfunction.

In general, an input circuit for a semiconductor IC includes an input inverter for inverting an input signal, an output inverter for inverting an output signal of the input inverter to provide an output signal, and a pseudo latch circuit for maintaining an appropriate level of the output signal. This prevents malfunction of the semiconductor IC due to noise.

The pseudo latch circuit includes two p-MOS transistors and two n-MOS transistors connected between the Vcc power supply and the ground by the source-drain path, so that the output signal is independent of the operation of the input inverter which is changed by noise. Can be latched to an appropriate level.

However, since the pseudo latch circuit includes four p and n-MOS transistors as described above, the structure of the input circuit is complicated. As a result, the scale of the conventional input circuit becomes large.

Accordingly, it is an object of the present invention to provide an input circuit having a simple structure so that the scale becomes small.

According to the present invention, an input circuit includes an input inverter for inverting an input signal to provide an inverted signal at an output nodal point, and an output for inverting the inverted signal to provide an output signal at the same level as the input signal. An inverter, and a latch circuit for latching a potential at the output node to be at a level opposite to that of the input signal, the latch circuit having the same conductivity connected in series by a source-drain path between the fixed potential and the output node. It includes two MOS transistors of the type, and the conductivity type depends on the level of the input signal at the timing when noise is input to the input circuit.

In order to better understand the background of the present invention, first, the basic principle of the prior art will be described below with reference to FIGS. 1 and 2a and 2b.

1 shows an input inverter 12 comprising a p-MOS transistor 18 and an n-MOS transistor 20; An output inverter 14 connected between the input inverter 12 and an output terminal OUT for providing an output signal OUT; And a conventional input circuit 10 including a pseudo latch circuit 16.

In the input inverter 12, the common gate of the p-MOS transistor 18 and the n-MOS transistor 20 is connected to the input terminal IN to which the input signal IN is supplied, and the p-MOS transistor 18 The source of is connected to the power supply (Vcc), the source of the n-MOS transistor 20 is connected to ground, the common drain of the p-MOS transistor 18 and n-MOS transistor 20 is the output inverter 14 It is connected to the node A connected to the input of.

Pseudo latch circuit 16 includes p-MOS transistors 22, 24, n-MOS transistors 28, 29, and inverter 26. The p-MOS transistor 22 is connected to the power supply Vcc at the source. The common gate of the p-MOS transistor 22 and the n-MOS transistor 29 is connected to a node B connected to the output of the output inverter 14. The p-MOS transistor 24 is connected to the output of the inverter 26 at the gate, to the drain of the p-MOS transistor 22 at the source, and to the node C connected at the node A at the drain. The n-MOS transistor 29 is connected to ground at the source and to the source of the n-MOS transistor 28 at the drain. The n-MOS transistor 28 is connected to the node D connected to the control terminal So to which the control signal So is supplied at the gate, and to the node C at the drain. The inverter 26 is connected to the node D at the input. The control signal So is generated by a known address detection circuit or the like.

FIG. 2A is a timing diagram showing the operation of the input circuit 10 when the low level input signal IN is supplied to the input inverter 12. FIG. When the low level input signal IN is supplied to the gates of the p-MOS transistor 18 and the n-MOS transistor 20, the p-MOS transistor 18 is turned on and the n-MOS transistor 20 is turned on. Turned off, the high level signal is supplied to the output inverter 14. The high level signal is inverted by the output inverter 14 into a low level signal, and a low level output signal OUT is supplied from the output terminal OUT of the input circuit 10. At this time, a low level signal is supplied to the gates of the p-MOS transistor 22 and the n-MOS transistor 29 so that the p-MOS transistor 22 is turned on and the n-MOS transistor 29 is turned off.

In normal operation, a low level control signal So is provided to the pseudo latch circuit 16 so that each p-MOS transistor 24 and n-MOS transistor 28 are turned off. Therefore, the input circuit 10 is not affected by the pseudo latch circuit 16. That is, node A is separated from power source Vcc and ground.

Then, when noise occurs in the semiconductor IC and affects the power supply Vcc and ground as shown in FIG. 2A, the level of the control signal So is from low state to high state at timing synchronized with noise generation. Is changed to In response to the high level control signal So, each p-MOS transistor 24 and n-MOS transistor 28 are turned on, and a high level signal is supplied to the node A. FIG. Therefore, since the gate-to-source voltage of the n-MOS transistor 20 is assumed to be higher than the threshold voltage, even when the n-MOS transistor 20 is turned on due to noise, the level of the node A remains high. maintain. As a result, the level of the output signal OUT is latched to the low state.

On the other hand, when the input circuit 10 does not include the pseudo latch circuit 16, a malfunction occurs. In more detail, the n-MOS transistor 20 is turned on. Therefore, the potential drops from the node A to the ground potential, so that the level of the output signal OUT changes from the low state to the high state.

FIG. 2B is a timing diagram showing the operation of the input circuit 10 when the high level input signal IN is supplied to the input inverter 12. FIG. Even in this case, when the high level control signal So is supplied to the pseudo latch circuit 16 at a timing synchronized with noise generation as shown in FIG. 2B, the low level signal is supplied from the pseudo latch circuit 16. FIG. It is provided at the node A. Therefore, the level of the node A remains low even when the p-MOS transistor 18 is turned on by the noise. As a result, the level of the output signal OUT is latched high.

On the other hand, when the input circuit 10 does not include the pseudo latch circuit 16, a malfunction occurs. In more detail, the voltage across the gate and the source of the n-MOS transistor 18 is raised above the threshold level by noise, and the n-MOS transistor 18 is turned on. Therefore, a high level signal is provided to the output inverter 14, so that the level of the output signal OUT changes from the high state to the low state.

According to the conventional input circuit 10, the output signal OUT can be latched to an appropriate level regardless of malfunction of the input inverter 12 due to noise. However, since the pseudo latch circuit 16 includes four transistors 22, 24, 28 and 29, the structure thereof becomes complicated.

3 shows the input circuit 30 of the first preferred embodiment according to the present invention, wherein the level of the input signal IN goes low at a timing when internal noise is input to the input circuit 30. The input circuit 30 includes an input inverter 12 including a p-MOS transistor 18 and an n-MOS transistor 20, an output inverter 14, and a pseudo latch circuit 32. The input inverter 12 has the same structure as the conventional input circuit 10 shown in FIG.

Pseudo latch circuit 32 includes two p-MOS transistors 34, 36 connected in series by source-drain paths. The p-MOS transistor 34 is connected to the power source Vcc at the source, to the source of the p-MOS transistor 36 at the drain, and to the node E at the gate. The p-MOS transistor 36 is connected to the control terminal So to which the control signal So is supplied at the gate, and to the node F at the drain.

4 is a timing diagram showing the operation of the input circuit 30. As shown in FIG. When the low level input signal IN is supplied to the gates of the p-MOS transistor 18 and the n-MOS transistor 20, the p-MOS transistor 18 is turned on and the n-MOS transistor 20 is Turned off, the high level signal is supplied to the output inverter 14. The high level signal is inverted by the output inverter 14 into a low level signal, so that the low level output signal OUT is supplied from the input circuit 30. At this time, a low level signal is provided to the gate of the p-MOS transistor 34 so that the p-MOS transistor 34 is turned on.

In normal operation, a high level control signal So is provided to the gate of the p-MOS transistor 36 so that the p-MOS transistor 36 is turned off. As a result, the input circuit 30 is not affected by the pseudo latch circuit 32. That is, the potential is separated from the power supply Vcc at the node F.

Then, when noise occurs in the semiconductor IC and affects the power supply Vcc and ground, the level of the control signal So is changed from the high state to the low state at the timing synchronized with the noise generation, so that the p-MOS Transistor 36 is turned on. Therefore, the level of the node F is kept high even when the n-MOS transistor 20 is turned on by noise. As a result, the level of the output signal OUT is latched low.

On the other hand, when the input circuit 30 does not include the pseudo latch circuit 32, a malfunction occurs. In more detail, the voltage across the gate and the source of the n-MOS transistor 20 rises above the threshold level by noise, so that the n-MOS transistor 20 is turned on. Therefore, the low level signal is supplied to the output inverter 14 so that the level of the output signal OUT is changed from the low state to the high state.

5 shows the input circuit 50 of the second preferred embodiment according to the present invention, wherein the level of the input signal IN becomes high at the timing when internal noise is input to the input circuit 50. In this embodiment, the same parts are denoted by the same reference numerals as used in FIG. 3, and the description of the same structure as in the first embodiment will be omitted.

The input circuit 50 includes a MOS transistor of the pseudo latch circuit 52 having a polarity opposite to that of the pseudo latch circuit 32 of the first preferred embodiment. That is, the pseudo latch circuit 52 includes two n-MOS transistors 54 and 56 connected in series with the source drain path. The n-MOS transistor 54 is connected to the control terminal So to which the control signal So is supplied at the gate and to the node G at the drain. The n-MOS transistor 56 is connected to the node H at the gate, to the ground at the source, and to the source of the n-MOS transistor 54 at the drain.

6 is a timing diagram showing the operation of the input circuit 50. As shown in FIG. In the input circuit 50, when the high level input signal IN is supplied to the gates of the p-MOS transistor 18 and the n-MOS transistor 20, the p-MOS transistor 18 is turned off, The n-MOS transistor 20 is turned on so that a low level signal is supplied from the input inverter to the output inverter 14. The low level signal is inverted to a high level signal by the output inverter 14, so that an output signal OUT having a high level is supplied from the output terminal OUT of the input circuit 50. In normal operation, the low level control signal So is provided to the gate of the n-MOS transistor 54 so that the n-MOS transistor 54 is turned off. As a result, the input circuit 50 is not affected by the pseudo latch circuit 52. In other words, the potential of the node G is not affected by grounding.

Then, when noise occurs in the semiconductor IC and affects the power supply Vcc and ground, a high level control signal So is supplied to the gate of the n-MOS transistor 54 at a timing synchronized with the noise generation. , n-MOS transistor 54 is turned on. Therefore, the level of the node G is kept low, and the p-MOS transistor 18 is turned on by the noise. As a result, the level of the output signal OUT is latched high.

On the other hand, if the input circuit 50 does not include the pseudo latch circuit 52, a malfunction occurs. In more detail, when the voltage across the gate and the source of the p-MOS transistor 18 rises above the threshold level by noise, the p-MOS transistor 18 is turned on. Therefore, the high level signal is supplied to the output inverter 14, so that the level of the output signal OUT is changed from the high state to the low state.

The present invention is made on the assumption that the timing at which internal noise is input to the input circuit is fixed to the timing at which one of the high state and low state input signals is provided to the input circuit. Therefore, one of the first and second preferred embodiments is selected depending on the timing.

While specific embodiments have been described in order to more clearly illustrate the present invention, the appended claims are not limited thereto and may be readily made by those skilled in the art according to the description herein. It is to be understood that all changes and optional configurations that fall within the scope of the invention are included.

Claims (5)

An input inverter for inverting the input signal to provide an inverted signal at an output node, an output inverter for inverting the inverted signal to provide an output signal at the same level as the input signal, and a potential of the output node. A latch circuit for latching at a level opposite to the level of the input signal, the latch circuit comprising two MOS transistors of the same conductivity type connected in series by a source-drain path between a fixed potential and the output node. And wherein the conductive type of the two MOS transistors of the same conductivity type depends on the level of the input signal at a timing at which noise is input into the input circuit. 2. The device of claim 1, wherein the two MOS transistors are p-type when the input signal is low at the timing, the fixed potential is a Vcc power source, and one of the two MOS transistors is connected to a control signal terminal at a gate. And the other one of said two MOS transistors is connected to said output terminal at a gate. 2. The device of claim 1, wherein the two MOS transistors are n-type when the input signal is high at the timing, the fixed potential is a ground potential, and one of the two MOS transistors is a control signal terminal at a gate. And the other one of said two MOS transistors is connected to said output terminal at a gate. Means for generating an output signal in accordance with a low level input signal, and a latch circuit for latching the level of the output signal to an appropriate level in accordance with a control signal supplied at a timing at which noise occurs, wherein the output signal is generated Means for including a first inverter circuit for inverting the level of the input signal and a second inverter circuit for inverting the level of the signal supplied from the first inverter circuit such that the output signal is generated in a low state, The latch circuit is connected to a power supply at a source and a first p-MOS transistor connected at a gate to an output of the second inverter circuit, and at a gate to a terminal to which the low level control signal is supplied and at the source to the first a second p-MO connected to the drain of the p-MOS transistor and connected to the output of the first inverter circuit at the drain An input circuit comprising an S transistor. Means for generating an output signal in accordance with a high level input signal, and a latch circuit for latching the level of the output signal to an appropriate level in accordance with a control signal supplied at a timing at which noise occurs, wherein the output signal is generated Means includes a second inverter circuit for inverting the level of the input signal such that the output signal is generated in a high state, the latch circuit being connected to ground at the source and connected to the output of the second inverter circuit at the gate. A first n-MOS transistor to be connected to a terminal to which the control signal at a high level is supplied at a gate and to a drain of the first n-MOS transistor at a source and to an output of the first inverter circuit at a drain. And a second n-MOS transistor.