KR0179091B1 - Method of fabricating mosfet - Google Patents
Method of fabricating mosfet Download PDFInfo
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- KR0179091B1 KR0179091B1 KR1019950069508A KR19950069508A KR0179091B1 KR 0179091 B1 KR0179091 B1 KR 0179091B1 KR 1019950069508 A KR1019950069508 A KR 1019950069508A KR 19950069508 A KR19950069508 A KR 19950069508A KR 0179091 B1 KR0179091 B1 KR 0179091B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 14
- 238000002513 implantation Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 5
- 125000004437 phosphorous atom Chemical group 0.000 claims abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000011065 in-situ storage Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 19
- 125000004429 atom Chemical group 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명서는 통전시의 동작속도 저하를 방지할 수 있는 비대칭 LDD구조의 MOSFET의 제조방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a method of manufacturing a MOSFET having an asymmetric LDD structure that can prevent a decrease in operating speed during energization.
상기한 목적을 달성하기 위한 본 발명의 MOSFET 제조방법은, 반도체 기판의 소정부분을 식각하여 소정 부분을 함몰시키는 함몰부를 형성하는 단계; 전면에 소정 두께의 게이트 산화막, 도핑된 폴리실리콘막 및 산화질화막을 적층한 다음, 함몰부의 소정 부분에 감광막 마스크를 형성하여 노출된 산화질화막과 폴리실리콘막을 동일한 식각 챔버에서 인-시튜로 식각하는 단계; 드레인 전극이 형성될 영역을 제외한 영역에 소정의 제2감광막 패턴을 형성한 다음에 인 원자를 소정 농도와 소정 주입 에너지로서 이온주입하여 N-영역을 형성하는 단계; 전면에 텅스텐 실리사이드를 소정 두께로 증착하고, 게이트 산화막이 노출될 때까지 비등방성 식각하여 폴리실리콘 막의 측에 텅스텐 실리사이드 스페이서를 형성하는 단계; 전면에 비소 원자를 소정 농도와 소정의 주입에너지로서 이온 주입하여 N+영역을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of fabricating a MOSFET, including: forming a recess to etch a predetermined portion of a semiconductor substrate to dent a predetermined portion; Stacking a gate oxide film, a doped polysilicon film, and an oxynitride film having a predetermined thickness on the entire surface, and then forming a photoresist mask on a predetermined portion of the depression to etch the exposed oxynitride film and the polysilicon film in-situ in the same etching chamber. ; Forming a second photoresist pattern in a region other than a region in which the drain electrode is to be formed, and then ion implanting phosphorus atoms at a predetermined concentration and a predetermined implantation energy to form an N − region; Depositing tungsten silicide on the entire surface to a predetermined thickness and anisotropically etching until the gate oxide film is exposed to form a tungsten silicide spacer on the side of the polysilicon film; And ion implanting an arsenic atom on the front surface at a predetermined concentration and a predetermined implantation energy to form an N + region.
Description
제1도는 종래의 실시예에 따른 함몰형 폴리사이드 구조를 갖는 MOSFET의 단면도.1 is a cross-sectional view of a MOSFET having a recessed polyside structure according to a conventional embodiment.
제2도는 본 발명의 일실시예에 따른 비대칭 함몰형 MOSFET을 형성하기 위한 과정을 설명하는 부분 공정 흐름도.2 is a partial process flow diagram illustrating a process for forming an asymmetric recessed MOSFET in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 함몰부11 semiconductor substrate 12 depression
13 : 게이트 산화막 14 : 도핑된 폴리실리콘막13 gate oxide film 14 doped polysilicon film
15 : 산화질화막 16 : 제1감광막 패턴15 oxynitride film 16 first photosensitive film pattern
17 : 제2감광막 패턴 18 : N-영역17 second photosensitive film pattern 18 N - region
19 : 텅스텐 실리사이드 스페이서 20 : N+영역19: tungsten silicide spacer 20: N + region
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 드레인 전극은 N-영역 및 N+영역의 저도핑 영역(LDD:Lightly Doped Drain)이 형성된 구조를 가지나, 소오스 전극은 N+영역만을 갖게 되는 함몰 형태의 게이트 전극을 형성하는 반도체 소자의 금속산화물 반도체 전계효과 트랜지스터(이하, MOSFET으로 약칭)의 제조방법-에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, the drain electrode has a structure in which a lightly doped drain (LDD) of N − and N + regions is formed, but the source electrode has a depression having only N + region. The present invention relates to a method for manufacturing a metal oxide semiconductor field effect transistor (hereinafter, abbreviated as MOSFET) of a semiconductor device for forming a gate electrode of the type.
반도체 소자가 고집적화됨에 따라, 폴리사이드 구조를 갖는 게이트 전극이 개발되어 사용되고 있다. 특히, 채널로부터 소오스 전극과 드레인 전극에 이르는 저항 성분이 줄어들도록 즉, 채널에서 트랜지스터의 연결단자에 이르기까지 확산 영역의 통로에서 발생하는 트랜지스터의 내부 저항 성분을 줄이기 위한 방법으로, 또 드레인 전극 쪽에 높은 전계가 형성되는 것을 방지하여 열전자(hot electron)에 의한 여러 가지 현상을 최소화시키기 위해 LDD공정을 채용한다.As semiconductor devices are highly integrated, gate electrodes having polyside structures have been developed and used. In particular, a method for reducing the resistance component from the channel to the source electrode and the drain electrode, that is, to reduce the internal resistance component of the transistor occurring in the passage of the diffusion region from the channel to the connection terminal of the transistor, The LDD process is employed to prevent the formation of an electric field and to minimize various phenomena caused by hot electrons.
첨부한 도면 제1도는 종래의 실시예에 따른 함몰형 폴리사이드 구조를 갖는 MOSEET의 단면도이다.1 is a cross-sectional view of a MOSEET having a recessed polycide structure according to a conventional embodiment.
상기 MOSFET은 먼저, 반도체 기판(1) 상에 사진 식각법으로 함몰 부위(2)를 형성하고, 소정 두께의 게이트 산화막(3), 도핑된 폴리실리콘막(4), 텅스텐 실리사이드(5)를 순차적으로 적충한 다음, 사진식각법으로 상기 게이트 산화막(3)을 노출시켜 게이트 전극 패턴을 형성하고, 이온주입법으로 N-영역(6)을 형성하고, 산화막의 전면 증착후, 게이트 전극 표면이 노출될 때까지 전면식각하여 게이트 전극의 측벽에 산화막 스페이서(7)를 형성하고, 이온주입법으로 N+영역(8)을 형성한다.The MOSFET first forms a recessed portion 2 on the semiconductor substrate 1 by photolithography, and then sequentially forms a gate oxide film 3, a doped polysilicon film 4, and a tungsten silicide 5 having a predetermined thickness. The gate oxide pattern 3 is exposed by photolithography to form a gate electrode pattern, and the N − region 6 is formed by ion implantation. After the entire surface of the oxide film is deposited, the gate electrode surface is exposed. The oxide layer spacer 7 is formed on the sidewall of the gate electrode until the surface is etched, and the N + region 8 is formed by ion implantation.
상기와 같이 형성되는 LDD구조를 갖는 MOSFET은 상기에서 언급한 LDD공정의 목적과 소자의 빠른 동작속도를 위하여 LDD영역이 드레인측에만 형성되는 것이 바람직하지만, 소오스 전극에도 동일하게 형성되어 소자의 턴-온(turn-on)시 동작 속도를 저하시키는 문제점이 존재한다.The MOSFET having the LDD structure formed as described above is preferably formed only on the drain side of the LDD region for the purpose of the above-mentioned LDD process and fast operation speed of the device. There is a problem of lowering the operation speed at turn-on.
따라서, 본 발명의 목적은 소오스 영역의 저도핑 영역을 제거하여 함몰형의 게이트 전극을 형성하므로써 상기한 소자의 통전시, 동작속도 저하를 방지할 수 있는 MOSFET의 제조방법 제공하기 위한 것이다.Accordingly, it is an object of the present invention to provide a method for manufacturing a MOSFET which can prevent a decrease in operating speed when the device is energized by removing a low doping region of a source region to form a recessed gate electrode.
상기한 목적을 달성하기 위한 본 발명의 MOSFET제조방법은, 반도체 기판의 상부에 소정의 감광막 마스크를 형성하여 노출된 부분을 식각하므로써, 반도체 기판의 소정 부분을 함몰시키는 함몰부를 형성하는 단계; 전면에 소정 두께의 게이트 산화막, 도핑된 폴리실리콘막 및 산화질화막을 적충한 다음, 함몰부의 소정 부분에 제1감광막 마스크를 형성하는 단계; 상기 제1감광막 마스크를 식각장벽으로 하여, 상기 도핑된 폴리실리콘막이 소정두께만큼 남을 때까지 노출된 산화질화막과 폴리실리콘막을 식각하는 단계; 상기 제1감광막 마스크의 제거후, 드레인 전극이 형성될 영역을 제외한 영역의 소정의 제2감광막 마스크 패턴을 형성한 다음에 인 원자를 소정 농도와 소정 주입 에너지로서 이온주입하여 N_영역을 형성하는 단계; 상기 제2감광막 패턴을 제거한 다음, 전면에 텅스텐 실리사이드를 소정두께로 증착하고, 게이트 산화막이 노출될 때까지 비등방성 식각하여 상기 폴리실리콘 막의 측벽에 텅스텐 실리사이드 스페이서를 형성하는 단계; 전면에 비소 원자를 소정 농도와 소정의 주입에너지로서 이온 주입하여 N+영역을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a MOSFET, which includes forming a recess on an upper portion of a semiconductor substrate by etching a portion of the semiconductor substrate by forming a predetermined photoresist mask on the upper portion of the semiconductor substrate; Filling a gate oxide film, a doped polysilicon film, and an oxynitride film of a predetermined thickness on the entire surface, and then forming a first photoresist mask on a predetermined portion of the depression; Etching the exposed oxynitride layer and the polysilicon layer until the doped polysilicon layer remains a predetermined thickness using the first photoresist mask as an etch barrier; After removing the first photoresist mask, a predetermined second photoresist mask pattern of a region excluding the region where the drain electrode is to be formed is formed, and then phosphorus atoms are ion implanted at a predetermined concentration and a predetermined implantation energy to form an N_ region. step; Removing the second photoresist layer pattern, depositing tungsten silicide to a predetermined thickness on the entire surface, and anisotropically etching the gate oxide layer to form a tungsten silicide spacer on the sidewall of the polysilicon layer; And ion implanting an arsenic atom on the front surface at a predetermined concentration and a predetermined implantation energy to form an N + region.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
제2도는 본 발명의 일 실시예에 따른 함몰 MOSFET의 제조방법을 설명하기 위한 부분 공정 흐름도이다.2 is a partial process flowchart illustrating a method of manufacturing a recessed MOSFET according to an embodiment of the present invention.
먼저, 제2a도에 도시한 바와 같이, 반도체 기판(11)의 상부에 소정의 감광막 마스크를 형성하여 노출된 부분을 1,000내지 3,000Å정도 식각하므로써, 반도체 기판의 소정 부분을 함몰시키는 함몰부(12)를 형성한다. 이후, 전면에 100 내지 200Å의 게이트 산화막(13), 약 1,000 내지 3,000Å두께의 도핑된 폴리실리콘막(14) 및 약 500 내지 1,000Å두께의 산화질화막(Oxynitride)을 적증한 다음, 함몰부의 소정 부분에 게이트 제1감광막 마스크 패턴(16)을 형성한다.First, as shown in FIG. 2A, a recess 12 that recesses a predetermined portion of the semiconductor substrate by forming a predetermined photoresist mask on the semiconductor substrate 11 and etching the exposed portion by about 1,000 to 3,000 kPa. ). Thereafter, the gate oxide film 13 having a thickness of 100 to 200 microseconds, the doped polysilicon film 14 having a thickness of about 1,000 to 3,000 microseconds, and the oxynitride film having a thickness of about 500 to 1,000 microseconds are deposited on the entire surface, The gate first photoresist mask pattern 16 is formed in the portion.
다음으로, 제2b도와 같이, 비둥방성 과소식각법으로 식각된 폴리실리콘막(14)이 약 100 내지 500Å 정도 남을 때까지 식각한 다음, 제1감광막 마스크 패턴(16)을 제거한다.Next, as shown in FIG. 2B, the polysilicon film 14 etched by the anisotropic underetching method is etched until about 100 to 500 kV remains, and then the first photoresist mask pattern 16 is removed.
상기 식각단계에서 산화질화막(15) 및 폴리실리콘막(14)은 동일한 식각 챔버에서 인-시튜(in-situ)로 식각한다.In the etching step, the oxynitride film 15 and the polysilicon film 14 are etched in-situ in the same etching chamber.
이 후, 제2c도와 같이, 드레인 전극이 형성될 영역을 제외한 영역에 소정의 제2감광막 패턴(17)을 형성한 다음에, 인(P) 원자를 1×1011내지 1×1015원자/㎤ 의 농도와 30 내지 100 KeV의 주입 에너지로서 이온주입하여 N-영역(18)을 형성한다.Thereafter, as shown in FIG. 2C, a predetermined second photoresist pattern 17 is formed in a region other than the region in which the drain electrode is to be formed, and then phosphorus (P) atoms are 1 × 10 11 to 1 × 10 15 atoms / Ion implantation is performed at a concentration of cm 3 and implantation energy of 30 to 100 KeV to form the N − region 18.
다음으로, 제2d도와 같이, 상기 제2감광막 마스크 패턴(17)을 제거한 다음, WF6및 SiH4가스를 사용하여 전체 구조의 상부에 약 1,500 내지 3,500Å의 텅스텐 실리사이드(WSi2)(미도시)를 소정 두께로 전면 증착하고, SF6및 Cl2가스를 공급하여 게이트 산화막이 노출될 때까지 비등방성 식각하여 상기 폴리실리콘 막의 측벽에 텅스텐 실리사이드 스페이서를 형성한다. 이때, 산화질화막(15)은 폴리실리콘막(14)의 식각보호층 역할을 한다.Next, as shown in FIG. 2D, the second photoresist mask pattern 17 is removed, and then tungsten silicide (WSi 2 ) of about 1,500 to 3,500 kPa on top of the entire structure using WF 6 and SiH 4 gas (not shown). ) Is entirely deposited to a predetermined thickness, and anisotropic etching is performed until the gate oxide film is exposed by supplying SF 6 and Cl 2 gas to form a tungsten silicide spacer on the sidewall of the polysilicon film. In this case, the oxynitride film 15 serves as an etch protection layer of the polysilicon film 14.
다음으로, 상기 게이트 전극 부위(19, 15, 14)를 이온주입 저지층으로 하여, 전면에 비소 원자를 1×1013내지 1×1017원자/㎤ 의 농도의 50 내지 120 KeV의 주입 에너지로서 이온 주입하여 N+영역(20)을 형성하므로써, 제2e도와 같은 함몰형 게이트 전극을 갖는 MOSFET을 형성한다.Next, using the gate electrode portions 19, 15, and 14 as ion implantation blocking layers, arsenic atoms on the entire surface as implantation energy of 50 to 120 KeV at a concentration of 1 × 10 13 to 1 × 10 17 atoms / cm 3. By ion implantation to form the N + region 20, a MOSFET having a recessed gate electrode as shown in FIG. 2e is formed.
이상에서 설명한 바와 같이, 본 발명의 MOSFET구조 및 제조방법은 소오스 영역에 불필요한 LDD영역이 형성되므로써, 통전시 소자의 동작속도를 저하시키는 문제점을 텅스텐 실리사이드 스페이서를 이용하여 드레인 영역에만 LDD영역을 형성하는 비대칭 함몰형 MOSFET을 제조하므로써, 초고집적 반도체 소자의 동작 속도를 향상시키는 효과를 제공한다.As described above, in the MOSFET structure and manufacturing method of the present invention, since the unnecessary LDD region is formed in the source region, the LDD region is formed only in the drain region using tungsten silicide spacers. By fabricating an asymmetric recessed MOSFET, it provides the effect of improving the operation speed of ultra-high density semiconductor devices.
여기에서는 본 발명의 특정실시예에 대하여 설명하고 도시하였지만 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, those skilled in the art can make modifications and variations.
따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (12)
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