KR0175043B1 - Planarization Method of Semiconductor Memory Device - Google Patents

Abstract

A planarization method of a semiconductor memory device is disclosed. The present invention provides a planarization method of a semiconductor memory device, comprising: a cell array region in which memory cells including cell capacitors are arranged two-dimensionally; and a peripheral circuit region formed of integrated circuits for driving the memory cells. Forming a cell capacitor and a first wiring having the same height in the region and the peripheral circuit region at the same time, and forming a second interlayer insulating film covering the entire substrate on which the cell capacitor and the first wiring are formed. The second interlayer dielectric film is formed so as not to have an inclined surface at the boundary portion between the peripheral circuit regions. According to the present invention, it is possible to form a flat second interlayer insulating film, thereby preventing the occurrence of pattern defects when forming the second wiring thereon.

Description

Planarization Method of Semiconductor Memory Device

1 is a cross-sectional view for explaining a conventional planarization method.

2 to 4 are cross-sectional views for explaining the planarization method of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor memory device, and more particularly, to a planarization method capable of eliminating a surface step occurring between a cell array region and a peripheral circuit region.

In recent years, the area occupied by unit cells has greatly decreased as the degree of integration of semiconductor memory devices, such as DRAMs, increases. The DRAM cell is composed of one cell capacitor and one transistor, and the area occupied by the cell capacitor decreases as the density of DRAM increases. Thus, the capacitance of the cell capacitor is reduced, so that the electrical characteristics of the cell, for example, the ability to read information at low voltages, is greatly reduced. In addition, when the capacitance of the cell capacitor is reduced, the information stored in the cell is easily destroyed by the α-particles injected from the outside. Therefore, in order to form a cell suitable for highly integrated DRAM, it is necessary to form a cell capacitor having a constant value or more in a limited area. In order to increase the capacitance of the cell capacitor, it is necessary to use a high dielectric constant of high dielectric constant or increase the surface area of the electrode of the capacitor, that is, the storage electrode.

Recently, in order to increase the surface area of the storage electrode, various methods of forming the storage electrode having a three-dimensional structure have been proposed. However, when the three-dimensional storage electrode is adopted in the DRAM cell, the surface level difference between the cell array region and the peripheral circuit region increases, resulting in pattern defects during the photolithography process for forming wiring in the stepped portions therebetween. .

1 is a cross-sectional view for explaining a method of planarizing an interlayer insulating film using a conventional DRAM manufacturing method as an example. Here, the portions indicated by a and b denote cell array regions and peripheral circuit regions, respectively.

Referring to FIG. 1, a planarized first interlayer insulating film is formed on a semiconductor substrate 1, and then the first interlayer insulating film is patterned to include a storage electrode contact hole of a cell capacitor in the cell array region a. An interlayer insulating film pattern is formed. Here, the first interlayer insulating film is a widely used BPSG film flowed at a high temperature. Subsequently, a first conductive film filling the storage electrode contact hole is formed on the entire surface of the resultant, and then patterned to form a plurality of storage electrodes 5 covering each storage electrode contact hole in the cell array region a. In this case, the storage electrode 5 may be formed to have a three-dimensional structure, for example, a cylindrical or fin type structure in order to increase its surface area.

Subsequently, a dielectric film and a second conductive film are sequentially formed on the entire surface of the resultant, and then patterned to form a dielectric film pattern 7 and a second conductive film pattern covering the cell array region a, that is, a plate electrode 9. . The surface of the substrate on which the cell capacitor composed of the storage electrode 5, the dielectric film pattern 7, and the plate electrode 9 is formed is the surface of the cell array region a and the surface of the peripheral circuit region b by the cell capacitor. It has different heights. Subsequently, a second interlayer insulating film, for example, a BPSG film flowed at a high temperature, is formed on the entire substrate on which the cell capacitor is formed. At this time, the surface of the second interlayer insulating film also has an inclined surface indicated by reference numeral A between the cell array region a and the peripheral circuit region b due to the surface step formed by the cell capacitor as shown. Next, the second interlayer insulating film pattern and the first interlayer insulating film pattern are successively patterned to form a first interlayer insulating film pattern 3 and a second interlayer insulating film pattern 11 having wiring contact holes in the peripheral circuit region b. Form. Subsequently, a conductive layer, such as an aluminum layer, is formed on the entire surface of the resultant contact hole, and then patterned by a conventional photo / etching process, thereby wiring each of the cell array region (a) and the peripheral circuit region (b). 13a) and wiring 13b are formed. In this case, it is difficult to form the wiring 13a formed on the inclined surface A of the second interlayer insulating film pattern 11 to a desired shape. This is because diffuse reflection by the inclined surface A occurs severely during the photolithography process for patterning the conductive layer, so that a photoresist pattern of a desired shape is not formed.

As described above, in the conventional method of planarizing the interlayer insulating film, the surface of the second interlayer insulating film is formed to be inclined by the step generated between the cell array region and the peripheral circuit region. This inclined surface causes poor patterning of the wiring when the wiring is formed thereon, thereby lowering the electrical characteristics of the DRAM.

Accordingly, an object of the present invention is to provide a planarization method of a semiconductor memory device capable of eliminating pattern defects in wiring.

The present invention to achieve the above object,

A flattening method of a semiconductor memory device comprising a cell array region in which memory cells consisting of one cell capacitor and one transistor are two-dimensionally arranged and a peripheral circuit region formed of an integrated circuit for driving the memory cells,

Forming a first interlayer insulating film on the semiconductor substrate;

Patterning the first interlayer dielectric layer to form a first interlayer dielectric layer pattern having a storage electrode contact hole and a first wiring contact hole of the cell capacitor in the cell array region and the peripheral circuit region, respectively;

Forming a first conductive layer filling the storage electrode contact hole and the first wiring contact hole on the entire surface of the resultant material;

Patterning the first conductive film to form a storage electrode covering the storage electrode contact hole and a first conductive film pattern covering the entirety of the peripheral circuit region;

Sequentially forming a dielectric film and a second conductive film on the entire surface of the resultant product;

The second conductive film, the dielectric film, and the first conductive film pattern are successively patterned to form a local wiring in the peripheral circuit area while isolating the cell array area and the peripheral circuit area. Forming a first pattern in the peripheral circuit region while forming a dummy pattern including a plate electrode, a dielectric layer pattern, and a first conductive layer pattern formed of the second conductive layer; And

And forming a second interlayer insulating film on the entire surface of the resultant.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 4 are cross-sectional views for explaining a planarization method of a semiconductor memory device according to the present invention using a DRAM as an example. Here, the portions indicated by a and b denote cell array regions and peripheral circuit regions, respectively.

2 is a cross-sectional view for explaining a step of forming the storage electrode 25a and the first conductive film pattern 25b. First, after depositing a first interlayer insulating film, for example, a BPSG film on the semiconductor substrate 21, it is flowed at a temperature of 800 ℃ to 900 ℃ to form a first planarized interlayer insulating film. Subsequently, the first interlayer insulating layer pattern is patterned to include a storage electrode contact hole of a plurality of DRAM cell capacitors in a cell array region a and a first wiring contact hole in a peripheral circuit region b. ).

Next, a first conductive film is formed on the entire surface of the resultant, and then patterned to cover the storage electrode 25a covering the respective storage electrode contact holes and the entire first circuit contact hole while covering the entire storage circuit area b. The first conductive film pattern 25b is formed on the substrate. Here, the first conductive film may be formed of a doped polysilicon film or an oxidized metal film, and in particular, when a high dielectric film such as a tantalum oxide film or a BST film is used to increase the capacitance of the cell capacitor in a subsequent process. It is preferable to form the first conductive film with an oxidation resistant metal film such as platinum, tungsten nitride, or titanium nitride. This is because when the high dielectric film is formed on the doped polysilicon film, an oxide film is formed at an interface between them during a subsequent thermal process to reduce the capacitance of the cell capacitor.

Therefore, when a high dielectric film such as a tantalum oxide film or a BST film is used for the cell capacitor, it is preferable to form the first conductive film as the oxidation resistant metal film.

3 is a cross-sectional view for describing a step of forming a cell capacitor and a first wiring. Specifically, a dielectric film and a second conductive film are sequentially formed on the entire surface of the substrate on which the storage electrode 25a and the first conductive film pattern 25b are formed. Here, the dielectric film is formed of an oxide film, N / O (nitride / oxide), O / N / O (oxide / nitride / oxide), tantalum oxide film, or BST film, wherein the second conductive film is a doped polysilicon film To form. Subsequently, the second conductive film, the dielectric film, and the first conductive film pattern 23 are successively patterned by a normal photo / etch process to cover the cell array region a, and the plate electrode made of the second conductive film ( 29a) and a dummy pattern 25c and a peripheral circuit region formed of a portion of the first conductive layer pattern 23 at the edge of the cell array region a while forming a dielectric layer pattern 27a under the plate electrode 29a. A first wiring is formed in (b) to cover the first wiring contact hole and to connect the elements (not shown) of the peripheral circuit to each other. The plate electrode 29a, the dielectric layer pattern 27a, and the storage electrode 25a constitute a cell capacitor, and the first wiring line includes the first conductive layer pattern 25d, the dielectric layer pattern 27b, and the first electrode. The two conductive film patterns 29b are sequentially stacked.

In this case, the gap between the dummy pattern 25c formed at the edge of the seal array region a and the first wiring adjacent thereto may be formed to have a minimum design rule size. This allows the second interlayer insulating film to be formed in a subsequent process to sufficiently fill the gap between the dummy pattern 2Sc and the first wiring adjacent thereto so as to be inclined between the cell array region a and the peripheral circuit region b. This is to prevent the formation.

As such, the surface of the substrate on which the cell capacitor and the first wiring are formed has an overall flat surface as shown.

4 is a cross-sectional view for explaining a step of forming the second interlayer insulating film pattern 31 and the second wirings 33a and 33b. In more detail, a second interlayer insulating film, for example, a BPSG film flowed at a temperature of 800 ° C. to 900 ° C., is formed on the entire surface of the substrate on which the cell capacitor and the first wiring are formed. When the second interlayer insulating film is flattened as described above, the surface of the second interlayer insulating film is formed to be flat as shown in FIG. In particular, a flat second interlayer insulating film is formed between the cell array region a and the peripheral circuit region b to prevent the formation of the inclined surface. Next, the second interlayer insulating film, the plate electrode 29a, the second conductive film pattern 29b, and the dielectric film patterns 27a and 27b are successively patterned to form the dummy pattern 25c and the first conductive film pattern 25d. A second wiring contact hole for exposing a predetermined region of the < RTI ID = 0.0 >), < / RTI > second interlayer insulating film pattern 31, plate electrode pattern 29c, second conductive film pattern 29d, and dielectric film pattern 27c, 27d To form. In this case, the plate electrode pattern 29c is exposed together on the sidewall of the second wiring contact hole exposing the dummy pattern 25c.

Next, the second wiring 33a and the first conductive film pattern 25d constituting the first wiring are connected to the surface of the dummy pattern 25c and the sidewall of the plate electrode pattern 29c through the second wiring contact hole. The second wiring 33b to be formed is formed by a conventional method. Here, the second wiring 33a is connected to the plate electrode pattern 29c of the cell capacitor as shown, and is a means for applying a voltage to the cell capacitor from the outside.

As described above, according to the embodiment of the present invention, by simultaneously forming the cell capacitor and the first wiring in the cell array region and the peripheral circuit region, respectively, using the same material layer, the cell array region surface and the peripheral circuit region surface have the same height as a whole. It can be formed to have. Therefore, since the second interlayer insulating film covering the cell capacitor and the first wiring can maintain a flat surface, it is possible to prevent the formation of the inclined second interlayer insulating film at the boundary between the cell array region and the peripheral circuit region. As a result, the pattern defect of the second wiring can be prevented when the second wiring is formed on the second interlayer insulating film.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (7)

1. A method of planarizing a semiconductor memory device, comprising: a semiconductor array region in which a memory cell composed of one cell capacitor and one transistor is two-dimensionally arranged; and a peripheral circuit region formed of an integrated circuit for driving the memory cell. Forming a first interlayer insulating film on the substrate; Patterning the first interlayer dielectric layer to form a first interlayer dielectric layer pattern having a storage electrode contact hole and a first wiring contact hole of the cell capacitor in the cell array region and the peripheral circuit region, respectively; Forming a first conductive layer filling the storage electrode contact hole and the first wiring contact hole on the entire surface of the resultant material; Patterning the first conductive film to form a storage electrode covering the storage electrode contact hole and a first conductive film pattern covering the entirety of the peripheral circuit region; Sequentially forming a dielectric film and a second conductive film on the entire surface of the resultant product; The second conductive film, the dielectric film, and the first conductive film pattern are successively patterned to form a local wiring in the peripheral circuit area while isolating the cell array area and the peripheral circuit area. Forming a first pattern in the peripheral circuit region while forming a dummy pattern including a plate electrode, a dielectric layer pattern, and a first conductive layer pattern formed of the second conductive layer; And forming a second interlayer insulating film over the entire surface of the resultant material. 2. The method of claim 1, wherein the first interlayer insulating film pattern is formed of a BPSG film. The method of claim 1, wherein the first conductive layer is formed of any one of a doped polysilicon layer and an oxidized metal layer. 4. The method of claim 3, wherein the metal oxide film is formed of one selected from a group consisting of platinum, tungsten nitride, and titanium nitride. 2. The method of claim 1, wherein the dielectric film is formed of any one selected from a tantalum oxide film and a BST film. The method of claim 1, wherein the second interlayer insulating film is formed of a BPSG film. The method of claim 1, wherein a gap between the dummy pattern and the first wiring adjacent thereto is formed to have a minimum design rule size.