KR0169766B1 - Frame number identification device for personal communication equipment - Google Patents

Abstract

The present invention relates to a frame number confirmation device of a personal communication terminal which can identify a current frame number based on a frame start signal transmitted from a base station and a 13 MHz reference clock in a personal communication device such as a portable telephone. In a personal communication system configured to form a time slot of 156.25 bits, each data bit having a length of 48 clocks based on a 13 MHz clock, and a clock generating means for generating a 13 MHz reference clock. Bit synchronization signal generating means for generating a bit synchronization signal based on the reference clock and the frame start signal, time slot synchronization signal generating means for generating a time slot synchronization signal based on the bit synchronization signal and the reference clock, and the time slot A time slot number counting means for counting a synchronous signal and outputting a current time slot number; Frame synchronous signal generating means for generating a frame synchronous signal based on the time slot number output from the hand means, frame number counting means for counting the frame synchronous signal output from the frame synchronous signal generating means and outputting the frame number; And latching means for latching the frame number output from the frame number counting means in accordance with the signal and outputting the latched number data.

Description

Frame number confirmation device of personal communication terminal

1 is a system configuration diagram showing the overall configuration of a personal communication system.

2 is a configuration diagram showing a frame structure of transmission / reception data in the personal communication system shown in FIG.

3 is a circuit diagram showing the configuration of a frame number confirmation apparatus for a personal communication terminal according to an embodiment of the present invention.

4 is a timing chart for explaining the operation of the apparatus shown in FIG.

5 is a timing chart for explaining the operation of the apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

1: terminal 2 (2 _{1 to} 3n): base station

3 (3 _{1 to} 3n): base station controller 4: switchboard

5: authentication center 30: bit synchronization signal generator

40: time slot synchronization signal generator 41: 156 bit signal generator

42: 12 clock counting section 50: reset section

60: time slot number counting unit 70: frame synchronization signal generating unit

80: frame number counting unit

AND1 to AND3: AND gates C1 to C8: counter

IV1 to IV17: Inverter LA1: Latch Circuit

NAND1-NAND4: NAND gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal communication device such as a portable telephone. Particularly, the frame number of a personal communication terminal is checked so that the current frame number can be checked based on a frame start signal transmitted from a base station and a reference clock of 13 MHz. Relates to a device.

Recently, with the rapid development of communication technology, a personal communication system has been developed and generalized so that an individual can communicate with another person while moving from an arbitrary place or from one place to another.

The personal communication system is largely divided into a time division multiple access (TDMA) system and a code division multiple access (CDMA) system. The TDMA system is widely used worldwide because of the high stability of the system and completeness of technology.

1 is a configuration diagram schematically showing the configuration of a personal communication system, in particular a TDMA system according to the TDMA scheme, in which reference numeral 1 denotes a terminal to be carried by an individual, and 2 (2 _{1 to} 2n) denotes a plurality of terminals ( 1) A base station which transmits / receives various data to and from the wireless signal to the terminal 1 and performs communication protocol conversion, encryption / decryption, etc., and 3 (3 _{1 to} 3n) are multiple base stations (2: 2 ₁ to 2n), the base station controller which performs functions such as allocation control and handover decision of the communication channel for each terminal 1, and the base station controller 3 and the trunk line or the local exchange are subsequently connected. An exchange that connects the authentication center 5 to be described, 5 is an authentication center that executes a license and charge processing for any terminal 1 by providing a unique number for each terminal 1 and the like.

In the personal communication system having the above configuration, when any terminal 1 is located in a specific area, the base station 2 having jurisdiction over the area confirms the existence of the terminal 1 and reports it to the base station controller 3. The base station controller 3 checks the registration status of the terminal 1 from the authentication center 5 and assigns an encryption code or the like necessary for the call through the base station 2 to make the terminal 1 usable. In addition, the call, etc. from the other terminal (1) is connected to the terminal (1).

In the above-described personal communication system, however, the base station 2 and the terminal 1 transmit and receive data through wireless communication, so that the base station 2 and the terminal 1 are provided. In order to transmit / receive data between them, it is necessary to match the transmission / reception method or the specification of the transmission / reception data. In consideration of this point, in general, in a TDMA type personal communication system, the system is configured according to the GSM (Global System for Mobile communication) standard.

According to the GSM standard, the base station controller 3 and the base station 2 transmit and receive data according to the LAPD protocol, and the base station 2 and the terminal 1 perform the LAPDm protocol.

In addition, according to the GSM standard, each base station (or terminal) has four radio carriers for data transmission and reception, and eight time slots (TS) for each radio carrier, and each time slot is 156.25. In this case, each time slot is allocated by the base station controller 3 for transmission of control data and traffic data of the terminal.

In addition, the base station 2 and the terminal 1 operate on the basis of a 13 MHz clock so that each bit constituting the timeslot TS has a length of 48 clocks, and as shown in FIG. With eight timeslots TS as one frame, 51-multiframe includes 51 frames for control data and 26-multiframe includes 26 frames for traffic data (voice and data). It is supposed to constitute.

In the above configuration, the base station 2 transmits to each terminal 1 a frame start signal for indicating the start time of the data frame and a time slot number to be used, and each terminal 1 transmits the frame start signal. After the synchronization with the base station 2 is synchronized with the base station 2 for data transmission and reception, various types of data transmission and reception are performed with the base station 2 through the assigned time slot period of each data frame to provide a call function to the user.

Therefore, in the above-described personal communication system, the bit synchronization signal, the time slot synchronization signal, and the time slot number data frame are based on the frame start signal transmitted from the base station 2 by the terminal 1 and the 13 MHz clock signal generated by itself. It is necessary to generate a synchronization signal, frame number data, and the like, and to perform data reception from the base station and data transmission to the base station.

Accordingly, the present invention has been made in view of the above circumstances, and uses the frame start signal transmitted from the base station and a 13 MHz reference clock generated by itself to identify the current frame number. The purpose is to provide an identification device.

The frame synchronization signal generator of a personal communication terminal according to the present invention for realizing the above object is configured to configure one time slot with 156.25 bits, while each data bit has a length of 48 clocks based on a 13 MHz clock. Clock generation means for generating a reference clock of 13 MHz in the personal communication system, bit synchronization signal generation means for generating a bit synchronization signal based on the reference clock and the frame start signal, and time based on the bit synchronization signal and the reference clock A time slot synchronous signal generating means for generating a slot synchronous signal, a time slot number counting means for counting the time slot synchronous signal, and outputting a current time slot number, based on the time slot number output from the time slot number counting means Frame synchronous signal generating means for generating a frame synchronous signal, which is output from the frame synchronous signal generating means Frame number counting means for counting a frame synchronous signal to output the frame number, and latching means for latching the frame number outputted from the frame number counting means in accordance with a latch signal and outputting the latched number data. It is characterized by.

Further, the present invention is characterized in that it further comprises a first reset means for counting the frame synchronous signal output from the frame synchronous signal generating means and reset the frame number counting means when the count value reaches 26. .

Further, the present invention is characterized in that it further comprises a second reset means for counting the frame synchronous signal output from the frame synchronous signal generating means and resetting the frame number counting means when the count value reaches 51. .

According to the present invention having the above-described configuration, a bit synchronization signal corresponding to each data bit is generated on the basis of a 13 MHz clock signal, and a time slot synchronization having a period of 156.25 bits using the bit synchronization signal and the clock signal is performed. Will generate a signal.

After calculating the current time slot number based on the count value of the time slot synchronization signal, the frame synchronization signal is generated using the calculated time slot number, and then the frame synchronization signal is counted to generate the frame number. After that, by latching it through the latch means, it is possible to check the current frame number whenever necessary.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

3 is a block diagram showing a frame number confirmation device of a personal communication terminal according to an embodiment of the present invention.

In Fig. 3, reference numeral 30 denotes a bit synchronous signal generator that counts a reference clock of 13 MHz output from a clock generating means (not shown) and outputs a clock signal when the count is 48. The first counter C1 of the 4-bit output that counts the reference clock, the second counter C2 of the 4-bit output that receives and counts the most significant bit output of the first counter C1, and the first counter C1. The NML gate NAND1 and the NAND gate NAND1 outputting a low level signal when the input signal becomes high level by receiving the DML inverted output and the first and second outputs of the second counter C2. The inverter IV5 which inverts an output and outputs it is comprised.

In this case, the output of the NAND gate NAND1 is used as a reset signal of the bit synchronous signal generator 30.

That is, as described above, according to the GSM standard, the terminal is synchronized with a clock signal of 13 MHz so that one bit has a size of 48 clocks. The bit synchronization signal generator 30 may generate a reference clock of 13 MHz in the first and second clocks. When the counter counts to the second counters C1 and C2 and the count value reaches 48, that is, the output of the first counter C1 is 0 and the output of the second counter C2 is 11, so that the first and second counters ( When the outputs of C1 and C2 are 0011 0000 as a whole, a clock signal indicating a bit synchronization signal is output.

The output of the NAND gate NAND1 is applied to the clear input terminal CLR of the first and second counters C1 and C2 through the AND gates AND1 and AND2 of the reset unit 50. The first and second counters C1 and C2 are reset.

Next, reference numeral 40 denotes a time slot synchronization signal generator for generating a time slot synchronization signal based on the bit synchronization signal output from the bit synchronization signal generator 30 and a reference clock of 13 MHz, which generates the bit synchronization signal. When the bit synchronization signal output from the unit 30 is counted and the count value is 156, the 156 bit counter 41 outputs a clock signal, and when the output of the 156 bit counter 41 becomes high, And a 12 clock counting section 42 for counting a reference clock of 13 MHz and outputting a clock signal as a time slot synchronizing signal when the count value reaches 12.

Here, the 156 bit counter 41 is similar to the bit sync signal generator 30 described above, and the first and second four bit output counters C3 and C4 of the serial connection for counting the bit sync signal, and When the outputs of the first and second counters C3 and C4 become 1001 1100, that is, 156 as a whole, the inverter that inverts the outputs of the NAND gate NAND2 and the NAND gate NAND2 whose output level is low It consists of (IV10).

The 12 clock counting unit 42 counts an AND gate AND1 that logically multiplies the output of the 156 bit counting unit 41 with the reference clock of 13 MHz, and counts a clock signal outputted from the AND gate AND1. When the output of the 4-bit output counter C5, the counter C5 becomes 1100, that is, 12, the NAND gate NAND3 for outputting the low level signal and the inverter for inverting the output of the NAND gate NAND3 ( IV13). The output of the NAND gate NAND3 is used as a clear signal of the first and second counters C3 and C4 constituting the counter C5 and the 156 bit count unit 41.

Reference numeral 50 denotes a reset unit, which is a first logical AND product of the NAND gate output of the bit synchronization signal generator 30 and the NAND gate output of the 12 clock counter 42. And an AND gate AND2, and a second AND gate AND3 for ANDing the output of the first AND gate AND2 and the frame start signal, and the output of the second AND gate AND3 is the bit. It is input as a clear signal of the first and second counters C1 and C2 constituting the synchronization signal generator 30.

In FIG. 3, reference numeral 60 denotes a time slot number generator for generating a time slot number by counting the time slot synchronous signal output from the time slot synchronous signal generator 40, which generates the time slot synchronous signal. The counter 40 is provided with a counter C6 for counting the clock signal output from the unit 40.

The counter C6 counts the timeslot numbers from 0 to 7 (0 to 111) by applying the most significant bit output stage QA4 DML output value to the clear input stage CLR through the inverter IV14. When the count value reaches 8, that is, when the output terminals QA4 to QA1 reach 1000, the counting operation is cleared again.

Further, reference numeral 70 denotes a frame synchronous signal generator for outputting a clock signal whenever the output value from the timeslot number generator 60 becomes 8, which is a counter provided in the timeslot number generator 60. Inverters IV15 to IV17 connected to the lower 3 bit outputs QA1 to QA3 of (C6), output values of the inverters IV15 to IV17, and output values output from the output terminal QA4 of the counter C6, respectively. A NAND gate NAND4 serving as an input and an inverter IV18 for inverting and outputting the output value of the NAND gate NAND4 are configured.

That is, the frame synchronous signal generator 70 outputs a clock signal having a predetermined pulse width whenever 1000, that is, 8 is input from the time slot number generator 60. In addition, at this time, the pulse width is set by the signal delay time by the inverter IV14 of the time slot number generator 60.

In FIG. 3, reference numeral 80 denotes a frame number generation unit for generating a frame number by counting the frame synchronization signal output from the frame synchronization signal generation unit 40, which is the frame synchronization signal generation unit 70 DPTJ. It is comprised by the counter (C7, C8) of the serial connection which counts the clock signal output.

The counters C7 and C8 are configured to be cleared in different ways depending on the type of data frame to which the apparatus is applied. That is, as described above, according to the GSM standard, the traffic data is composed of 26 frames of multiframes and the control data of 51 frames. The counters C7 and C8 are applicable data. Depending on the type of frame, they are cleared at different timings. In addition, the clear signal CLR for clearing the counters C7 and C8 counts the frame synchronous signal output from the frame synchronous signal generation unit 70, and the low level when the count value becomes 26 or 51. By constructing a counter that outputs a signal, it can be easily generated.

In addition, in FIG. 3, reference numeral LA1 latches frame number data output from the frame number counting unit 80 in accordance with a read control signal (I / O RD) from a microprocessor (not shown). The latch circuit outputs the data via the data bus 35.

Next, the operation of the apparatus having the above-described configuration will be described in more detail using the timing charts shown in FIG. 4 and FIG.

As shown in FIG. 4, in a personal communication system, one time slot is composed of 156.25 bits, and each bit has 48 clock periods based on a 13 MHz clock.

Therefore, in the apparatus shown in FIG. 3, 48 clocks of 13 MHz are first generated to generate a synchronization signal according to each bit, 156 of these synchronization signals are counted, and then an additional 12 reference clocks are counted to generate a time slot synchronization signal. Will generate

After generating the current timeslot number by counting the timeslot synchronization signal, whenever the timeslot number is 8, a synchronization signal for a data frame consisting of eight timeslots is outputted. The frame number is generated by counting the synchronization signal, and then latched through the latch circuit LA1 to output the frame number.

That is, as shown in FIG. 4 (b), after the frame start signal drops to a low level and the first and second counters C1 and C2 of the bit synchronization signal generator 30 are cleared, the frame start signal Is raised to the high level again, the first and second counters C1 and C2 of the bit synchronization signal generator 30 perform the counting operation, and the counter values corresponding thereto are output stages QA1 to QA4 and QB1 to QB4. Will output via

At this time, the output terminals QA to QA4 of the first counter C1 are connected to the NAND gate NAND1 directly through the inverters IV1 to IV4, and the output terminals QB1 and QB2 of the second counter C2 are directly connected. Accordingly, the NAND gate NAND1 is configured when the outputs QA1 to QA4 of the first counter C1 are all 0 and the outputs QB1 and QB2 of the second counter C2 are 11. When the output values QB4, QB3, QB2, QB1, QA4, QA3, QA2 and QA1 by the first and second counters C1 and C2 become 0011 0000, that is, 48, the low level signal is output.

In addition, the output of the NAND gate NAND1 is clear input terminal CLR of the first and second counters C1 and C2 through the first and second AND gates AND2 and AND3 of the reset unit 50. It is applied to reset the first and second counters (C1, C2) and is output through the inverter IV5, accordingly, the bit synchronization signal generator 30 in FIG. The bit synchronization signal corresponding to each bit signal as shown in FIG.

On the other hand, the clock signal output from the bit sync signal generator 30 is counted by the 156 bit counter 41 of the time slot sync signal generator 40, and the 156 bit counter 41 Similar to the bit sync signal generator 30 described above, the input clock signal is counted using the first and second counters C3 and C4 connected in series.

The output terminals QA1, QA2, QB2 and QB3 of the first and second counters C3 and C4 are coupled to the NAND gate NAND2 through the inverters IV6 to IV9. The gate NAND2 is at a low level when the outputs QB4 to QB1 and QA4 to QA1 of the first and second counters C3 and C4 become 1001 1100, that is, 156.

That is, the 156 bit counter 41 outputs a high level signal when the bit synchronization signal is input 156 times as shown in FIG.

Subsequently, when the output from the 156 bit counter 41 becomes high level, the 12 clock counter 42 causes a 13 MHz clock signal input through the AND gate AND1 to be applied to the counter C5 to count. Similarly to the above-described operation, when the count value of this counter C5 becomes 12, that is, the outputs QA4 to QA1 become 1100, the output of the NAND gate NAND3 becomes low level. As shown in Fig. (E), the synchronization signal corresponding to the time slot section is output.

In addition, the low level output of the NAND gate NAND3 is applied to the bit synchronization signal generator 30 through the first and second AND gates AND2 and AND3 of the reset 50, and thus the first and second outputs. In addition to clearing the two counters C1 and C2, the entire device is cleared by clearing the first and second counters C3 and C4 of the 156 bit counter 41 and the counter C5 of the 12 clock counter 42. Will be initialized.

That is, the bit sync signal generator 30 and the time slot sync signal generator 40 repeatedly execute the above-described operation to continuously generate and output a sync signal corresponding to the time slot. Accordingly, the time slot synchronization signal generator 40 outputs a synchronization signal corresponding to each time slot as shown in FIG.

Meanwhile, the timeslot number generator 60 counts the timeslot synchronization signal output from the timeslot synchronous signal generator 40 to output the timeslot number data, and at this time, the counter C6. ) Outputs the time slot number of 1 to 7 (TS1 to TS7), that is, the time slot number of 001 to 111, so that the output signal of the highest output terminal QA4 is used as a clear signal. , QA2, QA1) is cleared to 1000, and outputs a time slot number of 0, that is, TS0.

When the output of the counter C6 of the timeslot number generation unit 60 becomes 1000, that is, the frame synchronous signal generator 70 becomes low level, the output of the NAND gate NAND4 becomes low level. ), The output of the inverter IV18 goes back to the low level when the counter C6 is cleared by the inverter IV14 and the output of the counter C6 becomes zero. As shown in FIG. 5C, the signal generator 70 outputs a synchronization signal corresponding to the data frame.

Subsequently, the frame synchronizing signal output from the frame synchronizing signal generating unit 70 is counted by the frame number counting unit 80, and the count value thereof outputs the output terminals QB4 to QB1 and QA4 to QA1 of the counters C7 and C8. It is output through and coupled to the data input terminals 2A4 to 2A1 and 1A4 to 1A1 of the latch circuit LA1.

Therefore, an external device such as a microprocessor outputs the read control signal I / O RD to the latch circuit LA1 and checks the frame number through the data bus 35.

That is, according to the above embodiment, first, a bit synchronization signal corresponding to a data bit is generated on the basis of a 13 MHz reference clock, and a time slot synchronization signal having a period of 156.25 bits is generated using the bit synchronization signal and the reference clock. Will be done.

The frame synchronization signal is generated using the calculated time slot number based on the current time slot number based on the count value of the time slot synchronization signal, and then the frame synchronization signal is counted to generate a frame number. By latching through the latch means, the current frame number can be checked whenever necessary.

In addition, this invention is not limited to the said Example, It can implement in a various deformation | transformation in the range which does not deviate from the technical summary of this invention.

As described above, according to the present invention, a frame number confirmation apparatus of a personal communication terminal capable of identifying a current frame number for a data frame based on a frame start signal transmitted from a base station and a 13 MHz clock signal generated by itself is provided. It can be realized.

Claims (3)

In a personal communication system configured to form a time slot of 156.25 bits with each data bit having a length of 48 clocks based on a 13 MHz clock, clock generation means for generating a reference clock of 13 MHz, and the reference. A bit synchronous signal generating means for generating a bit synchronous signal based on a clock and a frame start signal, a time slot synchronous signal generating means for generating a time slot synchronous signal based on the bit synchronous signal and a reference clock, and the time slot synchronous signal A time slot number counting means for counting and outputting a current time slot number, a frame sync signal generating means for outputting a frame sync signal when the time slot number outputted from the time slot number counting means reaches a predetermined value, and the frame sync signal Frame number counting means for counting the frame synchronization signal outputted from the generating means and outputting the frame number And latch means for latching the frame number output from the frame number counting means and outputting the latched number data according to the latch signal. 2. The apparatus according to claim 1, further comprising a first reset means for counting a frame synchronous signal output from said frame synchronous signal generating means and resetting said frame number counting means when its count value reaches 26. Frame number confirmation device of the personal communication terminal. 2. The apparatus according to claim 1, further comprising a second reset means for counting a frame synchronous signal output from said frame synchronous signal generating means and resetting said frame number counting means when the count value reaches 51. Frame number confirmation device of the personal communication terminal.