KR100197492B1 - Traffic channel strove signal generating device for pcs - Google Patents

Abstract

The present invention relates to a strobe signal of an uplink traffic channel for a corresponding time slot based on a frame start signal transmitted from a base station and a time slot number allowed to be used in a personal communication device such as a portable telephone. An apparatus for generating an uplink traffic channel strobe signal for an assigned timeslot of a personal communication terminal, the bit synchronization signal corresponding to each data bit is generated based on a 13 MHz clock signal. A time slot synchronizing signal having a 156.25 bit interval is generated using a clock signal, and data transmission / reception is performed by comparing the count value of the time slot synchronizing signal with a time slot number delayed by 3 timeslots from the time slot number assigned thereto. Generate an uplink timeslot strobe signal for After calculating the current time slot number based on the numerical value, the frame synchronization signal is generated by using the calculated time slot number. Then, the frame synchronization signal is counted to generate the frame number. After generating the traffic channel strobe signal for data transmission and reception, the uplink traffic channel strobe signal for the allocated timeslot is generated through the logical product of the uplink timeslot strobe signal.

Description

Uplink traffic channel strobe signal generator for assigned timeslot of personal communication terminal

1 is a system configuration diagram showing the overall configuration of a personal communication system.

2 is a configuration diagram showing a frame structure of transmission / reception data in the personal communication system shown in FIG.

3 is a data configuration diagram of a traffic channel for transmitting and receiving voice data in the personal communication system shown in FIG.

4 is a configuration diagram of data of a control channel for transmitting and receiving control data in the personal communication system shown in FIG.

5 is a circuit diagram showing the configuration of an uplink traffic channel strobe signal generator for an assigned timeslot of a personal communication terminal according to an embodiment of the present invention.

6 is a timing chart for explaining the operation of the apparatus shown in FIG.

FIG. 7 is a timing chart for explaining the operation of the apparatus shown in FIG.

8 is a timing chart for explaining the operation of the apparatus shown in FIG.

9 is a timing chart for explaining the operation of the apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

1: terminal 2 (2 _{1-2 n} ): base station

3 (3 ₁ to 3 _n ): base station controller 4: switchboard

5: authentication center 10: bit synchronization signal generator

15: data bus 20: time slot synchronization signal generator

21: 156 bit signal generator 22: 12 clock counter

30: reset unit, 40: time slot number generation unit

50: uplink timeslot strobe signal generator 60: frame sync signal generator

70: frame number generator 80: clock signal output unit

90: traffic channel strobe signal generator

100: uplink traffic channel strobe signal generator

AND1 to AND5: AND gates C1 to C8: counter

IV1 to IV21: Inverter LA1: Latch Circuit

NAND1 to NAND4: NAND gate CP1 to CP4: comparator

ADD1 to ADD2: Adder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal communication device such as a portable telephone, and more particularly, to an uplink traffic channel stream for a corresponding time slot based on a frame start signal transmitted from a base station and a time slot number allowed to be used. An apparatus for generating an uplink traffic channel strobe signal for an allocated timeslot of a personal communication terminal configured to generate a sub-signal.

Recently, with the rapid development of communication technology, a personal communication system has been developed and generalized so that an individual can communicate with another person while moving from an arbitrary place or from one place to another.

The personal communication system is largely divided into a time division multiple access (TDMA) system and a code division multiple access (CDMA) system. The TDMA system is widely used worldwide because of the high stability of the system and completeness of technology.

1 is a configuration diagram schematically showing the configuration of a personal communication system, in particular, a TDMA system according to the TDMA method, in which reference numeral 1 denotes a terminal to be carried by an individual, and 2 (2 ₁ to 2 _n ) represents a plurality of terminals. 1 and transmits and receives various data to execute the conversion and encryption / decryption, etc. of transmission and reception with the communication protocol of the radio signal for the terminal (1) the base station, 3 (3 ₁ ~3 _n) includes a plurality of base stations (2: 2 A base station controller that performs functions such as allocation control and handover decision of a communication channel for each terminal 1 while managing ₁ to 2 _n ), and 4 is a base line or a local exchange with this base station controller 3. Switching process for connecting and processing the authentication center (5) to be described later, 5 is provided with a unique number for each terminal 1, etc. Authentication center for performing the use and billing processing for any terminal 1, etc. to be.

In the personal communication system having the above configuration, when any terminal 1 is located in a specific area, the base station 2 having jurisdiction over the area confirms the existence of the corresponding terminal 1 and reports it to the base station controller 3. The base station controller 3 checks the registration status of the terminal 1 from the authentication center 5 and then assigns an encryption code or the like necessary for a call through the base station 2 to enable the corresponding terminal 1 to be used. In addition, the call, etc. from the other terminal (1) is connected to the terminal (1).

In the above-described personal communication system, however, the base station 2 and the terminal 1 transmit and receive data through wireless communication, so that the base station 2 and the terminal 1 are provided. In order to transmit / receive data between them, it is necessary to match the transmission / reception method or the specification of the transmission / reception data. In consideration of this point, in general, in a TDMA type personal communication system, the system is configured according to the GSM (Global System for Mobile communication) standard.

According to the GSM standard, the base station controller 3 and the base station 2 are configured to transmit and receive data according to the LAPD protocol, and the base station 2 and the terminal 1 according to the LAPDm protocol.

In addition, according to the GSM standard, each base station (or terminal) has four radio carriers for data transmission and reception, and eight time slots (TS) for each radio carrier, and each time slot is 156.25. In this case, each time slot is allocated by the base station controller 3 for transmission of control data and traffic data of the terminal.

In addition, the base station 2 and the terminal 1 operate on the basis of a 13 MHz clock so that each bit constituting the timeslot TS has a length of 48 clocks, and as shown in FIG. Eight timeslots (TS) are used as one frame, and 51-multiframe or 102-multiframe including 51 or 102 frames for control data and 26 frames for traffic data (voice and data) It consists of a 26-multiframe including, and collects the 26-multiframe 51 or the 51-multiframe 26 or 102-multiframe 13 to form a superframe (Supter Frame) .

In the above configuration, the base station 2 transmits to each terminal 1 a frame start signal for indicating the start time of the data frame and a time slot number to be used, and each terminal 1 transmits the frame start signal. By synchronizing data transmission / reception with the base station 2 on the basis of the following, and transmitting and receiving various data, for example, voice data or control data, with the base station 2 through the allocated time slot period of each data frame. It is intended to provide a call function to the user.

FIG. 3 is a data configuration diagram showing a 26-multiframe configuration of a traffic channel for transmitting and receiving voice data between the base station 2 and the terminal 1. In FIG. Shows the relationship between the data frame transmitted to 1) and the data frame transmitted from the terminal 1 to the base station 2, and (b) and (c) represent data received through the timeslot assigned to the specific terminal. (B) shows a case in which one terminal uses one timeslot, and (c) shows a time slot shared by two terminals. The case of use is shown.

As shown in FIG. 3 (a), the downlink and uplink have a frequency difference of 90 MHz, and the uplink is a time slot in which three timeslots are shifted with respect to the downlink. It is set automatically.

That is, according to the GSM standard, when the terminal 1 is assigned a frequency for the downlink and its timeslot number by the base station controller 3, the terminal 1 is up to 90 MHz lower frequency and 3 timeslot delayed timeslot for the downlink frequency. It is intended to set the frequency and timeslot for the link.

As shown in FIG. 3 (b), after transmitting the voice channel T through 12 time slots, that is, 12 frames, the terminal 1 and the base station 2 adjust timing according to the transmission / reception distance. After transmitting the Slow Associateed Control Channel (A), and then transmitting 12 voice channels, a time slot for the idle is allocated.

In addition, in the case where one time slot is shared by two terminals as shown in FIG. 3 (c), after transmitting 12 voice channels T and t, the low speed combined control channel A for the first terminal is transmitted. And then transmit the 12 voice channels (T, t) again and then transmit the low speed combined control channel (a) for the second terminal.

On the other hand, Figure 4 shows the configuration of 51-multi-frame of the control channel for transmitting and receiving control data between the base station 2 and the terminal 1, which is shown in Figure 3 (b) and (c) in a specific terminal It shows the result of collecting the data received through the timeslot assigned to it.

In FIG. 4, reference numeral F denotes a frequency correction channel (FCCH) for frequency correction of the terminal, S denotes a synchronization channel (SCH) for the terminal to synchronize frame synchronization with the base station, and B denotes various types of base stations for the terminal. A broadcast control channel (BCCH) for transmitting various data for the terminal to access the base station, such as the status or information of neighboring base stations, and C is an access allowable channel (AGCH) or terminal for a response to an outgoing request from the terminal. A common control channel (CCCH) for transmitting / receiving various control data such as a call channel (PCH) for transmitting a call signal for a call or a fast combined control channel (FACCH) for a handover function, and R is a terminal. The random access channel (RACH), D0 to D7, for requesting a time or responding to a call signal from a base station, performs authentication processing or registers a call to register a terminal. An independent control channel (SDCCH) for transmitting and receiving various control data, A0 to A7, transmits and receives a signal strength or a timing advance value of a signal transmitted or received while a terminal performs a connection process with a base station or a call with another terminal. As a low speed coupled control channel (SACCH), in a personal communication system, various control data necessary for transmission and reception are transmitted and received by combining the various control channels as shown in FIG.

Therefore, in the above-described personal communication terminal, it is necessary to generate a timing signal for transmitting and receiving data through the various traffic channels or control channels.

Accordingly, the present invention was created in view of the above circumstances, and uses an uplink traffic channel strobe for a time slot allocated by a base station controller using a frame start signal transmitted from a base station and a 13 MHz reference clock generated by itself. An object of the present invention is to provide an uplink traffic channel strobe signal generator for an allocated timeslot of a personal communication terminal capable of generating a signal.

The uplink traffic channel strobe signal generator for the assigned timeslot of the personal communication terminal according to the present invention for realizing the above object has each clock bit length of 48 clocks based on a 13 MHz clock, and 156.25. A personal communication system configured to configure one time slot with bits, comprising: clock generating means for generating a reference clock of 13 MHz, bit synchronizing signal generating means for generating a bit synchronization signal based on the reference clock and a frame start signal; A time slot synchronous signal generating means for generating a time slot synchronous signal based on a bit synchronous signal and a reference clock; a time slot number counting means for counting the time slot synchronous signal and outputting a current time slot number; Latch means for storing a number, the timeslot number counted by said timeslot number counting means and said latch An uplink time slot strobe signal generating means for generating an uplink time slot strobe signal based on a time slot number delayed by three timeslots from the time slot number registered by the means, and a time slot outputted from the time slot number counting means A frame synchronous signal generating means for outputting a frame synchronous signal when the number becomes a predetermined value, frame number counting means for counting a frame synchronous signal outputted from the frame synchronous signal generating means and outputting a frame number from the frame number counting means; Traffic channel strobe signal generating means for generating a strobe signal for the traffic channel, and an uplink time slot strobe signal output from the uplink time slot strobe signal generating means and a traffic channel output from the traffic channel strobe signal generating means Straw signal logic And characterized by consisting of, including uplink traffic chaeteol strobe signal generating means for generating a strobe signal for the uplink traffic channel assigned timeslot.

According to the present invention having the above-described configuration, a bit synchronization signal corresponding to each data bit is generated on the basis of a 13 MHz clock signal, and a time slot synchronization having a period of 156.25 bits using the bit synchronization signal and the clock signal is performed. Will generate a signal.

The uplink time slot straw signal for data transmission and reception is generated by comparing the time slot number delayed by three times slots from the count value of the timeslot synchronization signal and the timeslot number assigned thereto.

In addition, after calculating the current time slot number based on the count value of the time slot synchronization signal, the frame synchronization signal is generated using the calculated time slot number, and the frame synchronization signal is counted to generate the frame number. .

After generating the traffic channel strobe signal for data transmission / reception by comparing the frame number with the assigned frame number, the uplink traffic channel strobe for the allocated time slot is logically multiplied with the uplink time slot strobe signal. Will generate a signal.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

5 is a circuit diagram illustrating an uplink traffic channel strobe signal generator for an allocated timeslot of a personal communication terminal according to an embodiment of the present invention.

In FIG. 5A, reference numeral 10 denotes a bit synchronous signal generator that counts a reference clock of 13 MHz output from a clock generator (not shown) and outputs a clock signal when its count reaches 48. The first counter C1 of the 4-bit output that counts the reference clock, the second counter C2 of the 4-bit output that receives the highest bit output of the first counter C1, and counts the first counter C1, and the first counter C1. Of the NAND gate NAND1 and the NAND gate NAND1 that output a low level signal when the input signal becomes high level by receiving the inverted output of < RTI ID = 0.0 >) < / RTI > The inverter IV5 which inverts an output and outputs it is comprised. Here, the output of the NAND gate NAND1 is to be used as a reset signal of the bit synchronous signal generator 10.

That is, as described above, according to the GSM standard, the terminal is synchronized with a 13 MHz clock signal so that 1 bit has a size of 48 clocks. The bit synchronous signal generator 10 may generate a 13 MHz reference clock. When the counter counts to the second counters C1 and C2 and the counter value reaches 48, that is, the output of the first counter C1 is 0 and the output of the second counter C2 becomes 11, so that the first and second counters ( When the output of C1, C2 is 0011 0000 as a whole, the clock signal indicating the bit synchronization signal is outputted.

The output of the NAND gate NAND1 is applied to the clear input terminal CLR of the first and second counters C1 and C2 through the AND gates AND2 and AND3 of the reset unit 30. The first and second counters C1 and C2 are reset.

Next, reference numeral 20 denotes a time slot synchronization signal generator for generating a time slot synchronization signal based on the bit synchronization signal output from the bit synchronization signal generator 10 and a reference clock of 13 MHz, which generates the bit synchronization signal. When the bit synchronization signal output from the unit 10 is counted and the count value is 156, the 156 bit counter 21 outputs a clock signal, and when the output of the 156 bit counter 21 becomes high, And a 12 clock counting unit 22 for counting a reference clock of 13 MHz and outputting a clock signal as a time slot synchronizing signal when the count is 12.

Here, the 156 bit counter 21 is similar to the bit synchronous signal generator 10 described above, and the third and fourth bit output counters C3 and C4 of the serial connection for counting the bit synchronous signal, and the third. And when the outputs of the fourth counters C3 and C4 become 1001 1100, that is, 156, the NAND gate NAND2 whose output level is low, and the inverter inverting the outputs of the NAND gate NAND2 and outputting the same. It consists of (IV10).

In addition, the 12 clock counting unit 22 performs an AND gate AND1 for ANDing the output signal of the 156 bit counting unit 21 and the output signal from the NAND gate NAND3, which will be described later, and the AND gate AND1. 4-bit output counter C5 counting the 13 MHz reference clock when the output signal from the high level is high, and NAND3 outputting a low level signal when the output of the counter C5 is 1100, i.e., 12. ) And an inverter IV13 for inverting and outputting the output of the NAND gate NAND3. In addition, the output of the NAND gate NAND3 is used as a clear signal of the third and fourth counters C3 and C4 constituting the counter C5 and the 156 bit counter 21.

Reference numeral 30 denotes a reset unit, which is a first end for performing an AND operation on the NAND1 output of the bit synchronization signal generator 10 and the NAND3 output of the 12 clock counter 22. A gate AND2, and a second AND gate AND3 for ANDing the output of the first AND gate AND2 and the frame start signal, and the output of the second AND gate AND3 is the bit synchronization. It is input as a clear signal of the first and second counters C1 and C2 constituting the signal generator 10.

In FIG. 5A, reference numeral 40 denotes a time slot number generation unit for generating a time slot number by counting a time slot synchronization signal output from the time slot synchronization signal generator 20, which is the time slot. The counter C6 which counts the clock signal output from the synchronous signal generation part 20 is comprised. The counter C6 counts the timeslot numbers 0 to 7 (0 to 111) by outputting the output value of the most significant bit output terminal QA4 to the clear input terminal CLR through the inverter IV14. When the count value reaches 8, that is, when the output terminals QA4 to QA1 reach 1000, the counting operation is cleared again.

Reference numeral LA1 denotes a latch circuit LA1 for latching the timeslot number data input via the data bus 15 when the write control signal I / O WR is input (rising edge). ) Registers the timeslot number transmitted from the base station.

Reference numeral 50 denotes an uplink timeslot strobe signal generator, which adds 3 to the set timeslot number output from the latch circuit LA1, that is, 3 timeslots with respect to the timeslot number transmitted from the base station. The first adder ADD1 for delaying and the time slot number delayed by the three time slots outputted from the first adder ADD1 are compared with the time slot number outputted from the time slot number generation unit 40. Is matched, the first comparator CP1 for outputting the high level comparison signal and the set time slot number outputted from the latch circuit LA1 are added to 4 to the time slot number outputted from the first adder ADD1. A second adder ADD2 for outputting a time slot number delayed by one time slot with respect to the first slot, a time slot number output from the second adder ADD2, and a time output from the time slot number generation unit 40 If the numbers are identical by comparing the lot numbers, the active comparator performs preset and clear operations by the second comparator CP2 and the low level signal, which outputs a high level comparison signal. D flip-flop (F1) of the D flip-flop (F1) of the preset input terminal PR of the first comparator (CP1) when the signal output from the first comparator (CP1) is inverted when the low level signal is applied By being set, the high level signal is output as an uplink timeslot strobe signal and the low level signal in which the signal output from the second comparator CP2 is inverted is applied to the clear input terminal CLR of the D flip-flop F1. When it is cleared.

On the other hand, reference numeral 60 in FIG. 5 (b) denotes a frame synchronous signal generator for outputting a clock signal whenever an output value from the time slot number generator 40 in FIG. 5 (a) becomes 8, The inverters IV17 to IV19 connected to the lower 3 bit outputs QA1 to QA3 of the counter C6 provided in the time slot number generation unit 50, and the output values of the inverters IV17 to IV19 and the And a NAND gate NAND4 for inputting an output value output from the output terminal QA4 of the counter C6, and an inverter IV20 for inverting and outputting the output value of the NAND gate NAND4.

That is, the frame synchronization signal generation unit 60 outputs a clock signal having a predetermined pulse width whenever 1000, that is, 8 is input from the time slot number generation unit 40. At this time, the pulse width is set by the signal delay time by the inverter IV14 of the time slot number generator 40.

Meanwhile, reference numeral 70 in FIG. 5 (b) denotes a frame number generator for generating a frame number by counting the frame sync signal output from the frame sync signal generator 60, which is the frame sync signal generator ( 60 is provided with counters C7 and C8 of serial connection for counting clock signals outputted from the terminal 60. The binary data corresponding to 5 bits of this counter is output as a frame number.

Reference numeral CP3 denotes data values input through the data input terminals P0 to P7, that is, frame number data and data input terminals Q0 to Q7 input from the counters C7 and C8 of the frame number generation unit 70. Is a comparator that outputs a high level signal when both data values coincide with each other, and the reference data values of the comparator CP3 set Q7 to Q0 to 0001 1010, that is, 26. have.

In addition, the output of the comparator CP3 is applied to the synchronization signal output unit 80 to be described later, and the counters C7 and C8 constituting the frame number generation unit 70 through the inverter IV21. Since the counters C7 and C8 are applied to the clear input terminal CLR, when the high level comparison signal is output from the comparator CP3, the counters C7 and C8 are cleared at the same time.

Also, in FIG. 5B, reference numeral 80 denotes a clock signal output unit which outputs a clock signal at a rising edge of the signal when a high level signal is output from the comparator CP3. The output signal of CP3) is coupled to the clock input terminal CLK and the D input terminal has a D flip-flop F2 coupled to the power supply voltage Vcc, and the D flip-flop F2 has its inverted output. Reset signal from and external Is applied through the AND gate AND4 to be cleared.

On the other hand, reference numeral 90 in FIG. 5 (b) is a traffic channel strobe signal generator for generating a strobe signal for the traffic channel from the frame number input from the frame number generator 70, which is the frame number generator. High level when the frame number data of 5 bits inputted from 70 to the lower data input terminals P0 to P4 and the 5-bit reference data value 1100, i.e., 12, input to the lower data input terminals Q0 to Q4 are matched. When the fourth comparator CP4 outputs a signal of 11, i.e., equals to 11001, 25, the fifth comparator CP5 outputs a high level signal, and the fourth comparator CP4 and the fifth comparator CP5. An OR gate OR1 for ORing the output and an inverter IV22 for inverting and outputting the output value of the OR gate OR1 are configured.

Further, reference numeral 100 in FIG. 5 (b) denotes an uplink traffic channel strobe signal generator, which is a traffic channel strobe signal input from the traffic channel strobe signal generator 90 and the uplink time slot straw unit. It consists of an AND gate AND5 for logically multiplying the uplink timeslot straw signal inputted from the signal generator 50. The uplink traffic channel for the timeslot assigned to the user through this ANDgate AND5. The straw signal is selected and output.

Next, the operation of the apparatus having the above-described configuration will be described in more detail using the timing charts shown in FIGS. 6 and 7.

As shown in FIG. 6, in a personal communication system, one time slot is composed of 156.25 bits, and each bit has 48 clock periods based on a 13 MHz clock.

Therefore, in the apparatus shown in Fig. 5A, first, 48 clocks of 13 MHz are counted to generate a sync signal according to each bit, 156 counts the sync signals, and then 12 additional reference clocks are counted. A slot sync signal is generated.

After generating the current timeslot number by counting the timeslot synchronization signal, whenever the timeslot number is 8, a synchronization signal for a data frame consisting of eight timeslots is outputted. The frame number is generated by counting the synchronization signal, and then latched through the latch circuit LA1 to output the frame number.

That is, as shown in FIG. 6 (b), after the frame start signal drops to low level and the first and second counters C1 and C2 of the bit synchronization signal generator 10 are cleared, the frame start signal Is raised to the high level again, the first and second counters C1 and C2 of the bit synchronization signal generator 10 perform the counting operation, and the count values corresponding thereto are output stages QA1 to QA4 and QB1 to QB4. Will output via

At this time, the output terminals QA1 to QA4 of the first counter C1 are coupled to the NAND gate NAND1 by the output terminals QB1 and QB2 of the second counter C2 directly through the inverters IV1 to IV4. Accordingly, when the NAND gate NAND1 has all the outputs QA1 to QA4 of the first counter C1 being 0 and the outputs QB1 and QB2 of the second counter C2 are 11, That is, when the output values QB4, QB3, QB2, QB1, QA4, QA3, QA2 and QA1 by the first and second counters C1 and C2 become 0011 0000, that is, 48, the low level signal is output.

In addition, the output of the NAND gate NAND1 is the clear input terminal CLR of the first and second counters C1 and C2 through the first and second and gates AND2 and AND3 of the reset unit 30. It is applied to reset the first and second counters (C1, C2) and is output through the inverter IV5, so that the bit synchronization signal generator 10 in FIG. The bit synchronization signal corresponding to each bit signal as shown in FIG.

On the other hand, the clock signal output from the bit sync signal generator 10 is counted by the 156 bit counter 21 of the time slot sync signal generator 20, and the 156 bit counter 21 Like the bit sync signal generator 10 described above, the input clock signal is counted using the third and fourth counters C3 and C4 connected in series.

The output terminals QA1, QA2, QB2, and QB3 of the third and fourth counters C3 and C4 are coupled to the NAND gate NAND2 through the inverters IV6 to IV9. NAND2 becomes low when the outputs QB4 to QB1 and QA4 to QA1 of the third and fourth counters C3 and C4 become 1001 1100, that is, 156.

That is, the 156 bit counting unit 21 outputs a high level signal when the bit synchronization signal is input 156 times as shown in FIG.

Subsequently, when the output from the 156 bit counter 21 becomes high level and the clear signal applied to the clear terminal CLR becomes high level, the 12 clock counter 22 receives the counter C5. The clock signal of 13 MHz inputted to (CLK) is counted. When the counter C5 has a count value of 12, i.e., its outputs QA4 to QA1 are 1100, the output of the NAND gate NAND3 is low. The level becomes a level so that the synchronization signal corresponding to the time slot section is output from the inverter IV13 as shown in FIG.

In addition, the low level output of the NAND gate NAND3 is applied to the bit synchronization signal generator 10 through the first and second AND gates AND2 and AND3 of the reset unit 30, and the first and second outputs. In addition to clearing the second counters C1 and C2, the third and fourth counters C3 and C4 of the 156 bit counter 21 and the counter C5 of the 12 clock counter 22 are cleared. Will be initialized.

That is, the bit sync signal generator 10 and the time slot sync signal generator 20 repeatedly execute the above-described operation to continuously generate and output a sync signal corresponding to the time slot. Accordingly, the time slot synchronization signal generator 20 outputs a synchronization signal corresponding to each time slot as shown in FIG.

Meanwhile, the timeslot number generator 40 counts the timeslot synchronization signal output from the timeslot synchronous signal generator 20 to output timeslot number data, and at this time, the counter C6. ) Outputs the time slot number of 1 to 7 (TS1 to TS7), that is, the time slot number of 001 to 111, so that the output signal of the highest output terminal QA4 is used as a clear signal, and then outputs (QA4, QA3). When QA2 and QA1) become 1000, they are cleared to output a time slot number of 0, that is, TS0.

The timeslot number data output from the timeslot number generator 40 is input to each of the input terminals A0 to A2 of the first and second comparators CP1 and CP2 of the uplink timeslot strobe signal generator 50. In the first comparator CP1, the time slot number applied from the time slot number generation unit 40 is added to the time slot number registered in the latch circuit LA1, thereby adding 3 times. When the delayed timeslot numbers are compared and matched, a high level signal is output, and the second comparator CP2 outputs a time slot number applied from the timeslot number generator 40 and the latch circuit LA1. The time slot number applied from the adder ADD which adds 4 to the registered time slot number is compared and the high level signal is output.

In addition, the high level signal output from the first comparator CP1 is input to the preset input terminal PR of the active low D flip-flop F1 by the inverted signal through the inverter IV15. A high level signal preset through (Q) is output, and a high level signal output from the second comparator CP2 after one time delay is outputted to the clear input terminal CLR of the D flip-flop F1. The inverted signal is inputted through the inverter IV16 to clear the signal of the D flip-flop.

That is, for example, when the time slot number registered in the latch circuit LA1 is 4, that is, the outputs Q2, Q1, Q0 of the latch circuit LA1 are 100, as shown in FIG. From the D flip-flop F1 by the output signal of the first comparator CP1 at the time when the fourth clock signal is output from the signal generator 20 at the time when the fourth clock signal is delayed by three timeslots. The signal of the preset high level is output, and the signal of the D flip-flop F1 is cleared by the output signal of the second comparator CP2 after one time slot is delayed. As a result, an uplink strobe signal corresponding to the corresponding timeslot is output.

Meanwhile, when the output of the counter C6 of the timeslot number generator 40 becomes 1000, that is, the frame synchronization signal generator 60 of FIG. When the output becomes low level, the output of the inverter IV20 becomes high level, and then the counter C6 is cleared by the inverter IV14 so that the output of the counter C6 becomes zero. By being low again, the frame synchronizing signal generating unit 60 outputs a synchronizing signal corresponding to the data frame as shown in FIG.

Subsequently, the frame synchronizing signal output from the frame synchronizing signal generating unit 60 is counted by the frame number counting unit 70, and the count value of the frame synchronizing signal generating unit 60 outputs the output terminals QB4 to QB1 and QA4 to QA1 of the counters C7 and C8. It is output through and coupled to the data input terminals P0 to P7 of the comparator CP3.

On the other hand, the comparator CP3 compares the count value data by the counters C7 and C8 input to the data input terminals P0 to P7 and the reference data input to the data input terminals Q0 to Q7 to compare the input terminals Q7 to Q0. When the data to be input is 0001 1010 and becomes the same as the reference data value, that is, when the count value by the counters C7 and C8 is 26, a high level signal is output.

The high level signal is applied to the clear input terminal CLR of the counters C7 and C8 through the inverter IV21 to clear the counters C7 and C8 and to the clock signal output unit 80. Will be.

Subsequently, the clock signal output unit 80 generates the D flip-flop F2? At a rising edge at which the output of the comparator CP3 becomes a high level. The output Q becomes high level, after which the inverted output The D flip-flop F3 is cleared so that the output Q is brought back to a low level, thereby outputting a synchronization signal for 26-multiframe.

FIG. 8 is a timing chart showing a synchronization signal for a 26-multiframe output from the clock signal output unit 80. In FIG. 8, (a) shows a configuration of a 26-multiframe, and (b) As shown in FIG. 6 (d), it is a synchronization signal for each frame output from the frame synchronization signal generator 60, and (c) is a synchronization signal of 26-multi frame output from the clock signal output unit 80. It is shown.

Meanwhile, output QA4 of the seventh counter C7 of the frame number generation unit 70 in FIG. 5 (b). The 5-bit frame number data output from the lower output QB1 of the QA1 and the eighth counter C8 is input to the fourth and fifth comparators CP4 and CP5 of the traffic channel strobe signal generator 90. When the fourth comparator CP4 coincides with the 5-bit frame number data input from the frame number generation unit 70 and the reference data value 1100, i.e., 12, of 5 bits input to the data input terminals Q0 to Q4, The level signal is output, and the fifth comparator CP5 outputs a high level signal when it matches 11001 (25). In addition, the output signals of the first comparator CP1 and the second comparator CP2 are logically multiplied through the OR gate OR1 and then inverted and output through the inverter IV22, as shown in FIG. Likewise, the strobe signal for the traffic channel is generated.

In addition, the traffic channel strobe signal outputted from the traffic channel strobe signal generator 90 and the uplink time slot strobe signal outputted from the uplink time slot strobe signal generator 50 are the uplink traffic channel strobe. By being logically multiplied through the AND gate AND5 of the signal generator 100, the uplink traffic channel strobe signal for the timeslot assigned to the user is selected and output.

That is, FIG. 9 is a timing chart showing the uplink traffic channel strobe signal for the timeslot allocated for the 26-multiframe, and FIG. 9 (a) shows the 26-multiframe as shown in FIG. 8 (a). (B) is a traffic channel strobe signal output from the traffic channel strobe signal generator 90, and (c) is an uplink strobe for the allocated timeslot as shown in FIG. (D) represents the uplink traffic channel strobe signal for the assigned timeslot output of the signals of (b) and (d) above, that is, the traffic channel strobe signal and the uplink time slot strobe signal are multiplied and output. will be.

That is, according to the above embodiment, first, a bit synchronization signal corresponding to each data bit is generated based on a 13 MHz clock signal, and the time slot synchronization signal having a period of 156.25 bits using the bit synchronization signal and the clock signal. Will generate

The uplink time slot straw signal for data transmission and reception is generated by comparing the time slot number delayed by three times slots from the count value of the timeslot synchronization signal and the timeslot number assigned thereto.

In addition, after calculating the current time slot number based on the count value of the time slot synchronization signal, a frame synchronization signal is generated using the calculated time slot number, and then the frame synchronization signal is counted to generate a frame number. .

After generating the traffic channel strobe signal for data transmission and reception by comparing the frame number with the assigned frame number, the uplink traffic channel strobe signal for the allocated time slot is logically multiplied with the uplink time slot strobe signal. Will generate

In addition, this invention is not limited to the said Example, It can implement in a various deformation | transformation in the range which does not deviate from the technical summary of this invention.

That is, for example, in the above embodiment, it is configured to include a clock signal output unit 80 that generates a clock signal based on the output signal of the comparator CP3, but this is simply a 26-multi output of the comparator CP3. It may be used as a synchronization signal for a frame.

As described above, according to the present invention, a strobe of an uplink traffic channel corresponding to a time slot for transmitting / receiving data to / from a base station is based on a frame start signal and a time slot number transmitted from the base station and a 13 MHz clock signal generated by itself. It is possible to realize an uplink traffic channel strobe signal generator for an assigned timeslot of a personal communication terminal intended to generate a signal.

Claims (1)

Clock generation means for generating a 13 MHz reference clock, bit synchronization signal generation means for generating a bit synchronization signal based on the reference clock and the frame start signal, and a time slot synchronization signal based on the bit synchronization signal and the reference clock. A personal communication terminal comprising time slot synchronous signal generating means for generating, comprising: time slot number counting means for counting the time slot synchronous signal and outputting a current time slot number, and a time slot number input through a data bus; Latch means for storing data, a first adder for adding 3 to the timeslot number counted by said timeslot number counting means, a timeslot number counted by said counting means and an output data value of said first adder A first comparator for outputting a first signal when the two data values match with each other, and a timeslot number registered in the latch means. An adder for adding 4 to the call data, a second comparator for comparing the timeslot number counted by the counting means with the output data value of the second adder and outputting a second signal when both data values match; An uplink time slot strobe signal generating means having a D flip-flop for outputting an uplink time slot strobe signal by using the first signal as a preset signal and a second clear signal; Frame synchronous signal generating means for outputting a frame synchronous signal based on the timeslot number data, frame number counting means for counting the frame synchronous signal outputted from the frame synchronous signal generating means, and outputting a frame number from the frame number counting means; A third comparator which detects whether the coefficient data of 12 is 12 and a third comparator which detects whether the coefficient data is 25 A traffic channel strobe signal generating means for generating a strobe signal corresponding to the frames other than the thirteenth and twenty-sixth comparators, and an uplink time slot strobe signal and the timeslot assigned by the traffic channel strobe signal; And an uplink traffic channel strobe signal generating means for generating an uplink traffic channel strobe signal for the uplink traffic channel strobe signal generator for the assigned timeslot of the personal communication terminal.