KR0179210B1 - Strobe signal generating device for mobile terminal - Google Patents

Abstract

The present invention generates a strobe signal for a traffic channel based on a time slot number allocated through the base station and a 13 MHz reference clock generated by itself in transmitting traffic data from the terminal to the base station in a half rate method. This invention relates to a traffic channel strobe signal generator of a personal communication terminal, which has a 48 clock length for each data bit based on a 13 MHz clock, and constitutes one time slot with 156.25 bits. In the system, a bit synchronization signal is generated based on the reference clock and the frame start signal, and then a time slot synchronization signal is generated based on the bit synchronization signal and the reference clock, and the time slot synchronization signal is counted to determine a current time slot. The number is calculated. Subsequently, a time slot strobe signal is generated when the time slot number obtained by adding 3 to the time slot number set from the outside coincides with the time slot number counted from the time slot number counting means. The frame synchronization signal is generated based on the counted timeslot number, the frame number is calculated based on the frame synchronization signal, and the strobe signal of the traffic channel is generated based on the frame number. The strobe signal of the corresponding traffic channel outputs the strobe signal of the corresponding traffic channel in two frame periods based on the signal and the frame synchronization signal.

Description

Traffic channel strobe signal generator of personal communication terminal

1 is a system configuration diagram showing the overall configuration of a personal communication system.

2 is a configuration diagram showing a frame structure of transmission / reception data in the personal communication system shown in FIG.

3 is a data configuration diagram showing a 26-multiframe configuration of a traffic channel for transmitting and receiving voice data between a base station and a terminal.

4 is a data configuration diagram showing a 51-multiframe configuration of a control channel for transmitting and receiving control data between a base station and a terminal.

5 is a circuit diagram showing the configuration of a traffic channel strobe signal generator of a personal communication terminal according to Embodiment 1 of the present invention.

6 to 10 are timing charts for explaining the operation of the apparatus shown in FIG.

* Explanation of symbols for main parts of the drawings

1: terminal 2 (2 ₁ ~2n): base station

3 (3 _{1 to} 3n): base station controller 4: switchboard

5: authentication center 10: bit synchronization signal generator

20: time slot synchronization signal generator 21: 156 bit signal generator

22: 12 clock counting unit 30: reset unit

40: timeslot number generator 50: timeslot strobe signal generator

60: frame synchronization signal generation unit 70: frame number counting unit

80: clock signal output unit 90: traffic channel strobe signal generator

AND1 to AND6: AND gates C1 to C8: Counter

CP1 to CP5: Comparators IV1 to IV22: Inverters

LA: Latch Circuit MUX: Multiplexer

ADD1, ADD2: Adder F1 to F4: Flip-flop

NAND1 to NAND4: NAND gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal communication device such as a portable telephone, and more particularly, to a traffic channel based on a frame start signal transmitted from a base station and a 13 MHz reference clock in transmitting data from a terminal to a base station in a half rate scheme. The present invention relates to a traffic channel strobe signal generator in a half rate method of a personal communication terminal capable of generating a strobe signal for.

Recently, with the rapid development of communication technology, a personal communication system has been developed and generalized so that an individual can communicate with another person while moving from an arbitrary place or from one place to another.

The personal communication system is largely divided into a time division multiple access (TDMA) system and a code division multiple access (CDMA) system. The TDMA system is widely used worldwide because of the high stability of the system and completeness of technology.

1 is a configuration diagram schematically showing the configuration of a personal communication system, in particular a TDMA system according to the TDMA scheme, in which reference numeral 1 denotes a terminal to be carried by an individual, and 2 (2 _{1 to} 2n) denotes a plurality of terminals ( 1) A base station which transmits / receives various data to and from the wireless signal to the terminal 1 and performs conversion and encryption / decryption of communication protocols, and 3 (3 _{1 to} 3n) are a plurality of base stations (2: 2 ₁ to 2). 2n), a base station controller which performs functions such as allocation control and handover decision of a communication channel for each terminal 1; An exchange that connects the authentication center 5 to be described, 5 is an authentication center that executes a license and charge processing for any terminal 1 by providing a unique number for each terminal 1 and the like.

In the personal communication system having the above configuration, when any terminal 1 is located in a specific area, the base station 2 having jurisdiction over the area confirms the existence of the terminal 1 and reports it to the base station controller 3. The base station controller 3 checks the registration status of the terminal 1 from the authentication center 5 and then assigns an encryption code or the like necessary for the call through the base station 2 to use the terminal 1 in a usable state. In addition, the call from the other terminal 1 is connected to the corresponding terminal 1.

In the above-described personal communication system, however, the base station 2 and the terminal 1 transmit and receive data through wireless communication, so that the base station 2 and the terminal 1 are provided. In order to transmit / receive data between them, it is necessary to match the transmission / reception method or the specification of the transmission / reception data. In consideration of this point, in general, in a TDMA type personal communication system, the system is configured according to the GSM (Global System for Mobile communication) standard.

According to the GSM standard, the base station controller 3 and the base station 2 transmit and receive data according to the LAPD protocol, and the base station 2 and the terminal 1 perform the LAPDm protocol.

In addition, according to the GSM standard, each base station (or terminal) has four radio carriers for data transmission and reception, and eight time slots (TS) for each radio carrier, and each time slot is 156.25. In this case, each time slot is allocated by the base station controller 3 for transmission of control data and traffic data of the terminal.

In addition, the base station 2 and the terminal 1 operate on the basis of a 13 MHz clock so that each bit constituting the timeslot TS has a length of 48 clocks, and as shown in FIG. Eight timeslots (TS) are used as one frame, and 51-multiframe or 102-multiframe including 51 or 102 frames for control data and 26 frames for traffic data (voice and data) It consists of a 26-multiframe including, and collects the 26-multiframe 51 or the 51-multiframe 26 or 102-multiframe 13 to form a super frame (Super Frame) .

In the above configuration, the base station 2 transmits to each terminal 1 a frame start signal for indicating the start time of the data frame and a time slot number to be used, and each terminal 1 transmits the frame start signal. By synchronizing data transmission / reception with the base station 2 on the basis of the following, and transmitting and receiving various data, for example, voice data or control data, with the base station 2 through the allocated time slot period of each data frame. It is intended to provide a call function to the user.

FIG. 3 is a data configuration diagram showing a 26-multiframe configuration of a traffic channel for transmitting and receiving voice data between the base station 2 and the terminal 1, and in FIG. Figure 1 shows the relationship between the data frame transmitted from 1) and the data frame transmitted from the terminal 1 to the base station 2, and (b) and (c) represent data received through the timeslot assigned to the specific terminal. (B) shows a case in which one terminal uses one timeslot, and (c) shows a time slot shared by two terminals. The case of use is shown.

As shown in FIG. 3 (a), the downlink and uplink have a frequency difference of 90 MHz, and the uplink is a time slot in which three timeslots are shifted with respect to the downlink. It is set automatically.

That is, according to the GSM standard, when the terminal 1 is assigned a frequency for the downlink and its timeslot number by the base station controller 3, the terminal 1 is upgraded to a time slot delayed by 90 MHz for the downlink frequency and a time slot delayed by 3 timeslots. It is intended to set the frequency and timeslot for the link.

As shown in FIG. 3 (b), after transmitting the voice channel T through 12 time slots, that is, 12 frames, the terminal 1 and the base station 2 adjust timing according to the transmission / reception distance. After transmitting a slow associated control channel (A: A) and then transmitting 12 voice channels, a time slot for idle is allocated.

In addition, in the case where one time slot is shared by two terminals as shown in FIG. 3 (c), after transmitting 12 voice channels T and t, the low speed combined control channel A for the first terminal is transmitted. And then transmit the 12 voice channels (T, t) again and then transmit the low speed combined control channel (a) for the second terminal.

On the other hand, Figure 4 shows the configuration of 51-multi-frame of the control channel for transmitting and receiving control data between the base station 2 and the terminal 1, which is shown in Figure 3 (b) and (c) in a specific terminal It shows the result of collecting the data received through the timeslot assigned to it.

In FIG. 4, reference numeral F denotes a frequency correction channel (FCCH) for frequency correction of the terminal, S denotes a synchronization channel (SCH) for the terminal to synchronize frame synchronization with the base station, and B denotes a base station for the terminal. A broadcast control channel (BCCH) for transmitting various data for a terminal to access a base station, such as various states of the base station and information of neighboring base stations, and C is an access permission channel (AGCH) for a response to an outgoing request from the terminal. Or a common control channel (CCCH) for transmitting and receiving various control data, such as a call channel (PCH) for transmitting a call signal to a terminal, a fast combined control channel (FACCH) for a handover function, and the like. A random access channel (RACH) for requesting an outgoing call or responding to a call signal from a base station, D0 to D7 proceeds with authentication or recommendation to register a terminal. Independent control channel (SDCCH) for transmitting and receiving various control data related to the transmission and reception, A0 to A7 transmits and receives a signal strength or timing advance value of a signal transmitted or received during the terminal's connection processing or communication with another terminal. As a low speed coupled control channel (SACCH), in a personal communication system, various control data necessary for transmitting and receiving are required by combining the various control channels as shown in FIG.

Therefore, in the above-described personal communication terminal, it is necessary to generate a timing signal for transmitting and receiving data through the various traffic channels and control channels.

Accordingly, the present invention has been made in view of the above circumstances, and based on a frame start signal transmitted from a base station and a 13 MHz reference clock in transmitting data from a terminal to a base station in a half rate method, a traffic channel is generated. It is an object of the present invention to provide a traffic channel strobe signal generator in a half-rate scheme of a personal communication terminal capable of generating a strobe signal for.

The low-speed combined control channel strobe signal generator of the personal communication terminal according to the present invention for realizing the above object has a length of 48 clocks and a time slot of 156.25 bits based on a clock of 13 MHz. A personal communication system configured to include: clock generating means for generating a reference clock of 13 MHz, bit synchronous signal generating means for generating a bit synchronous signal based on the reference clock and a frame start signal, and the bit synchronous signal and a reference; A time slot synchronizing signal generating means for generating a time slot synchronizing signal based on a clock; a time slot number counting means for counting the time slot synchronizing signal and outputting a current time slot number; By comparing the added timeslot number with the timeslot number counted by the timeslot number counting means, both data are added. A time slot strobe signal output means for outputting a time slot strobe signal corresponding to a period of time to be inputted, a frame sync signal generating means for outputting a frame sync signal based on the time slot number outputted from the time slot number counting means, and the frame sync A frame number counting means for counting a frame synchronization signal output from the signal generating means to output a frame number, and generating a strobe signal of the traffic channel based on the frame number counted by the frame number counting means, and then And output means for outputting a strobe signal of a corresponding traffic channel in two frame periods based on the signal and the frame synchronous signal output from the frame synchronous signal generating means.

That is, according to the above configuration, the time slot synchronizing signal is generated based on the reference clock of 13 MHz, the current time slot number is calculated based on the count value of the time slot synchronizing signal, and the calculated time slot number is used. By generating the time slot strobe signal and the frame synchronization signal, the strobe signal for the traffic channel can be generated based on the count value obtained by counting the time slot strobe signal and the frame synchronization signal.

FIG. 5 is a circuit diagram showing the configuration of a traffic channel strobe signal generator in a half-rate scheme of a personal communication terminal according to Embodiment 1 of the present invention. In FIG. Bit synchronization signal generator for counting the reference clock of 13 MHz and outputting a clock signal when the count value reaches 48, which is the first counter C1 of the 4-bit output that counts the reference clock of 13 MHz. The second counter C2 of the 4-bit output, which receives the most significant bit output of the first counter C1, counts it, the inverted output of the first counter C1, and the first and second counters of the second counter C2. And a NAND gate NAND1 for outputting a low level signal when the input signals are all high level when the second output is applied, and an inverter IV5 for inverting and outputting the output of the NAND gate NAND1. . Here, the output of the NAND gate NAND1 is to be used as a reset signal of the bit synchronous signal generator 10.

That is, as described above, according to the GSM standard, the terminal is synchronized with a 13 MHz clock signal so that 1 bit has a size of 48 clocks. The bit synchronous signal generator 10 may generate a 13 MHz reference clock. When the counter counts to the second counters C1 and C2 and the counter value reaches 48, that is, the output of the first counter C1 is 0 and the output of the second counter C2 becomes 11, so that the first and second counters ( When the output of C1, C2 is 0011 0000 as a whole, the clock signal indicating the bit synchronization signal is outputted.

The output of the NAND gate NAND1 is applied to the clear input terminals CLR of the first and second counters C1 and C2 through the AND gates AND2 and AND3 of the reset unit 30 to be described later. The first and second counters C1 and C2 are reset.

Next, reference numeral 20 denotes a time slot synchronization signal generator that generates a time slot synchronization signal based on the bit synchronization signal output from the bit synchronization signal generator 10 and a reference clock of 13 MHz, which generates the bit synchronization signal. A 156 bit counting unit 21 for counting the bit synchronization signal outputted from the unit 10 and outputting a clock signal when the count value is 156, and when the output of the 156 bit counting unit 21 becomes high level, And a 12 clock counting unit 22 for counting a reference clock of 13 MHz and outputting a clock signal as a time slot synchronizing signal when the count is 12.

Here, the 156 bit counter 21 is similar to the bit sync signal generator 10 described above, and the first and second 4-bit output counters C3 and C4 of the serial connection for counting the bit sync signal, and When the outputs of the first and second counters C3 and C4 become 1001 1100, that is, 156 as a whole, the outputs of the NAND gates NAND2 and the NAND gates NAND2 whose output levels are low level are inverted and outputted. It is comprised including the inverter IV10.

The 12 clock counting unit 22 also includes an AND gate AND1 for ANDing the output signal of the 156 bit counting unit 21 and the output signal of the NAND gate NAND3, which will be described later, from the AND gate AND1. 4 bit output counter (C5) that counts the reference clock of 13Mhz when the output signal is high level, NAND gate (NAND3) outputs a low level signal when the output of this counter (C5) is 1100, that is 12 And an inverter IV13 that inverts the output of the NAND gate NAND3 and outputs the inverted output. Here, the output of the NAND gate NAND3 is used as a clear signal of the first and second counters C3 and C4 constituting the counter C5 and the 156 bit counter 21.

Reference numeral 30 denotes a reset unit, which is a first end for performing an AND operation on the NAND1 output of the bit synchronization signal generator 10 and the NAND3 output of the 12 clock counter 22. And a second AND gate AND3 that logically multiplies the output of the first AND gate AND2 and the frame start signal, and the output of the second AND gate AND3 is the bit synchronization. It is input as a clear signal of the first and second counters C1 and C2 constituting the signal generator 10.

In FIG. 5A, reference numeral 40 denotes a time slot number generator for generating a time slot number by counting a time slot synchronization signal output from the time slot synchronization signal generator 20, which is the time slot. The counter C6 which counts the clock signal output from the synchronous signal generation part 20 is comprised. The counter C6 counts the timeslot numbers from 0 to 7 (0 to 111) by outputting the output value of the most significant bit output terminal QA4 to the clear input terminal CLR through the inverter IV14. When the count value reaches 8, that is, when the output terminals QA4 to QA1 reach 1000, the counting operation is cleared again.

Reference numeral 50 denotes a time slot strobe signal generator, which is a time slot number data input through a data bus, i.e., a rising time, when a recording control signal I / O WR is input (rising edge). A latch circuit LA for latching slot number data, a first adder ADD1 for adding '3' to a set time slot number output from the latch circuit LA, and the time slot number generator And a first comparator CP1 for outputting a high level comparison signal when both numbers are matched by comparing the timeslot number outputted from 40 with the timeslot number outputted from the first adder ADD1. Also, a second adder ADD2 for adding '4' to the set time slot number output from the latch circuit LA and outputting the generated time slot number and the time slot number output from the second adder ADD2. Output from section 40 Compares the timeslot numbers, and if the numbers match, the second comparator CP2 outputting a high level comparison signal and the inverters IV15, which inverts and outputs the outputs of the first and second comparators CP1 and CP2. IV16) and an active low D flip-flop (F1) in which preset and clear operations are performed by a low level.

Here, the signal output from the first comparator CP1 to the preset input terminal PR of the D-flop flop F1 is inverted through the inverter IV15 and is preset when the low level signal is applied. The level signal is output as a timeslot strobe signal, and the D-flip flop F1 is outputted from the second comparator CP2 to the clear input terminal CL through the inverter IV16 to invert the low level. When the signal is applied, the signal is cleared to lower the timeslot strobe signal to a low level.

On the other hand, reference numeral 60 is a frame synchronization signal generator for outputting a clock signal whenever the output value from the timeslot number generator 40 becomes 8, which is a counter provided in the timeslot number generator 40. Inverters IV17 to IV19 connected to the lower 3 bit outputs QA1 to QA3 of (C6), output values of the inverters IV17 to IV19, and output values output from the output terminal QA4 of the counter C6, respectively. A NAND gate NAND4 serving as an input and an inverter IV20 for inverting and outputting the output value of the NAND gate NAND4 are configured.

That is, the frame synchronization signal generation unit 60 outputs a clock signal having a predetermined pulse width whenever 1000, that is, 8 is input from the time slot number generation unit 40. At this time, the pulse width is set by the signal delay time by the inverter IV14 of the time slot number generator 40.

In FIG. 5B, reference numeral 70 denotes a frame number counting unit for generating a frame number by counting the frame synchronizing signal output from the frame synchronizing signal generating unit 60, which is the frame synchronizing signal generating unit ( The counters C7 and C8 of serial connection for counting clock signals outputted from 70) are provided, so that binary data corresponding to 5 bits of this counter is output as a frame number.

Reference numeral CP3 denotes data values input through the data input terminals P0 to P7, that is, frame number data and data input terminals Q0 to Q7 input from the counters C7 and C8 of the frame number counting unit 70. Is a comparator that outputs a high level signal when both data values coincide with each other, and the reference data values of the comparator CP3 set Q7 to Q0 to 0001 1010, that is, 26. have.

The output of the comparator CP3 is applied to the clock signal output unit 80 to be described later, and the counters C7 and C8 constituting the frame number counting unit 70 through the inverter IV21. Since the counters C7 and C8 are applied to the clear input terminal CLR, when the high level comparison signal is output from the comparator CP3, the counters C7 and C8 are cleared at the same time.

Also, in FIG. 5B, reference numeral 80 denotes a clock signal output unit which outputs a clock signal at a rising edge of the signal when a high level signal is output from the comparator CP3. The output signal of CP3) is coupled to the clock input terminal CLK, and the D input terminal has a D-flip flop F2 coupled to the power supply voltage Vcc, and this D-flip flop F2 is the inverted output thereof. ( ) And external reset signal ( ) Is applied through the AND gate AND4 to be cleared.

On the other hand, reference numeral 90 in FIG. 5 (b) is a traffic channel strobe signal generator for generating a strobe signal corresponding to the traffic channel from the frame number output from the frame number counting unit 70, which is a data input stage P0 to FIG. The data value input through P7), that is, the frame number data input from the counters C7 and C8 of the frame number counting unit 70 and the reference data value input to the data input terminals Q0 to Q7 are compared. If the values match, the first and second comparators CP4 and CP5 outputting a high level signal and a clock pulse signal (I / O WR signal) input from a microprocessor that controls the entire device (not shown). And a D-flip-flop F4 for outputting a high or low level selection signal to the multiplexer MUX, which will be described later, in accordance with the signal D0, and further comprising the first and second comparators CP4 and CP5. From An OR gate OR for ORing the output signal, an inverter IV21 for inverting an output signal of the OR gate OR, and an AND gate AND5 for ANDing the output signal from the inverter IV22 with the frame synchronization signal. ), Based on the input signal from the AND gate AND5, an output signal of the D-flip-flop F3 and the input signal from the D-flip-flop F4 for converting and outputting the output signal to the multiplexer MUX, which will be described later. Input signal Q, from the D-flip flop F3 according to (0 or 1) ), A multiplexer (MUX) for selectively outputting the output signal, an AND gate (AND6) for ANDing the output signal from the multiplexer (MUX) and the input signal from the inverter (IV22), and the input signal from the AND gate (AND6). And an AND gate (AND7) outputting a strobe signal for the traffic channel by ANDing the timeslot strobe signal inputted from the timeslot strobe signal generator 50.

Here, the reference data value of the first comparator CP4 is set to the data input terminals Q7 to Q0 connected to the power supply voltage Vcc to 0000 1100, that is, 12, and the reference data value of the second comparator CP5 is The data input terminals Q7 to Q0 are set to 0001 1001, that is, 25.

Next, the operation of the apparatus having the above-described configuration will be described in more detail using the timing chart shown in FIGS. 6 to 10.

As shown in FIG. 2, in a personal communication system, one time slot is composed of 156.25 bits, and each bit has 48 clock periods based on a 13 MHz clock.

Therefore, in the apparatus shown in FIG. 5, first, a clock of 13 MHz is counted to generate a synchronization signal according to each bit, 156 of these synchronization signals are counted, and then an additional 12 reference clocks are counted to generate a time slot synchronization signal. Will generate

After generating the current timeslot number by counting the timeslot synchronization signal, whenever the timeslot number becomes 8, the synchronization signal for the data frame consisting of eight timeslots is outputted. The frame number is generated by counting the synchronization signal, and then latched through the latch circuit LA1 to output the frame number.

That is, as shown in FIG. 6 (b), after the frame start signal drops to the low level and the first and second counters C1 and C2 of the bit synchronization signal generator 10 are cleared, the frame start signal Is raised to the high level again, the first and second counters C1 and C2 of the bit synchronization signal generator 10 perform the counting operation, and the count values corresponding thereto are output stages QA1 to QA4 and QB1 to QB4. Will output via

At this time, the output terminals QA to QA4 of the first counter C1 are connected to the NAND gate NAND1 directly through the inverters IV1 to IV4, and the output terminals QB1 and QB2 of the second counter C2 are directly connected. As a result, the NAND gate NAND1 has the outputs QA1 to QA4 of the first counter C1 all 0 and the outputs QB1 and QB2 of the second counter C2 11, respectively. When the output values QB4, QB3, QB2, QB1, QA4, QA3, QA2 and QA1 by the first and second counters C1 and C2 become 0011 0000, that is, 48, the low level signal is output.

In addition, the output of the NAND gate NAND1 is clear input terminal CLR of the first and second counters C1 and C2 through the first and third and gates AND2 and AND3 of the reset unit 30. It is applied to reset the first and second counters (C1, C2) and is output through the inverter IV5, so that the bit synchronization signal generator 10 in FIG. 6 (c) The bit synchronization signal corresponding to each bit signal as shown in FIG.

On the other hand, the clock signal output from the bit sync signal generator 10 is counted by the 156 bit counter 21 of the time slot sync signal generator 20, and the 156 bit counter 21 is Like the bit synchronization signal generator 10 described above, the input clock signal is counted using the first and second counters C3 and C4 connected in series.

The output terminals QA1, QA2, QB2, and QB3 of the first and second coefficient units C3 and C4 are coupled to the NAND gate NAND2 through the inverters IV6 to IV9. The gate NAND2 becomes low when the outputs QB4 to QB1 and QA4 to QA1 of the first and second counters C3 and C4 become 1001 1100, that is, 156.

That is, the 156 bit counter 21 outputs a high level signal when the bit synchronization signal is input 156 times as shown in FIG.

Subsequently, when the output from the 156 bit counter 21 becomes high level and the clear signal applied to the clear terminal CLR becomes high level, the 12 clock counter 22 receives a counter input clock ( The clock signal of 13 MHz inputted to CLK) is counted. When the count value of this counter C5 is 12, that is, the outputs QA4 to QA1 are 1100, the output of the NAND gate NAND3 is low. The level becomes so that the synchronization signal corresponding to the time slot section is output from the inverter IV13 as shown in FIG.

The low level output of the NAND gate NAND3 is applied to the bit synchronous signal generator 10 through the first and third AND gates AND2 and AND3 of the reset unit 30 and the first and third outputs. In addition to clearing the second counters C1 and C2, the first and second counters C3 and C4 of the 156 bit counter 21 and the counter C5 of the 12 clock counter 22 are cleared. Will be initialized.

That is, the bit sync signal generator 10 and the time slot sync signal generator 20 repeatedly execute the above-described operation to continuously generate and output a sync signal corresponding to the time slot. Accordingly, the time slot synchronizing signal generator 20 outputs a synchronizing signal corresponding to each time slot as shown in FIG.

Meanwhile, in FIG. 5 (a), the timeslot number generator 40 counts the timeslot sync signal output from the timeslot sync signal generator 20 to output the timeslot number data. In this case, since the output signal of the highest output terminal QA4 is used as the clear signal, the counter C6 outputs the time slot numbers of 1 to 7 (TS1 to TS7), that is, the time slot numbers of 001 to 111. After that, when the outputs QA4, QA3, QA2, and QA1 become 1000, the output is cleared to output 0, that is, the timeslot number of TS0.

The timeslot number outputted from the timeslot number generator 40 is compared with the timeslot numbers registered in the latch circuit LA of the timeslot strobe signal generator 50 in the comparators CP1 and CP2. For example, when the time slot number registered in the latch circuit LA is '4', that is, the outputs Q2, Q1 and Q0 of the latch circuit LA are 100, as shown in FIG. The D-flip flop F1 is preset by the high-level output from the comparison ratio CP1 at the time when the fourth clock signal is output from the time slot synchronizing signal generator 20. ) Output Q becomes high level, and then the fifth clock signal is output from the time slot synchronization signal generator 20 so that the output value of the time slot number generator 40 becomes '101'. D-flip-flop F1 is cleared by the high level output from It is to be dropped to the low level. Therefore, the timeslot strobe signal generator 50 outputs a strobe signal corresponding to the timeslot allocated through the base station.

Meanwhile, in FIG. 5 (b), the frame synchronization signal generating unit 60 outputs QA4 to QA1 of the counter C6 of the time slot number generating unit 40 in FIG. That is, when it reaches 8, the output of the NAND gate NAND4 becomes low level, and the output of the inverter IV20 becomes high level. Then, the counter C6 is driven by the inverter IV14 of the time slot number generator 40. When the counter C6 is cleared and the output of the counter C6 becomes 0, the output of the inverter IV18 goes back to the low level, so that the frame synchronous signal generator 60 responds to the data frame as shown in FIG. The synchronization signal is output.

Subsequently, the frame synchronizing signal output from the frame synchronizing signal generating unit 60 is counted by the frame number counting unit 70, and the count value of the frame synchronizing signal generating unit 60 outputs the output terminals QB4 to QB1 and QA4 to QA1 of the counters C7 and C8. It is output through and coupled to the data input terminals P0 to P7 of the comparator CP1.

On the other hand, the comparator CP3 compares the count value data by the counters C7 and C8 input to the data input terminals P0 to P7 and the reference data input to the data input terminals Q0 to Q7 to compare the input terminals Q7 to Q0. When the data to be input is 0001 1010 and becomes the same as the reference data value, that is, when the count value by the counters C7 and C8 is 26, a high level signal is output.

The high level signal is applied to the clear input terminal CLR of the counters C7 and C8 through the inverter IV21 to clear the counters C7 and C8 and to the clock signal output unit 80. To be authorized.

Then, the clock signal output unit 80 inverts the output of the D-flip flop F2 at the rising edge at which the output of the comparator CP3 becomes a high level. ) Becomes the low level, and then the low level output ( D-flip flop (F2) is cleared by ) Becomes high level again, thereby outputting a 26-multiframe synchronization signal for 26-multiframe as shown in FIG. In addition, the 26-multi-frame synchronization signal is inputted to the second and gate AND6 of the reset unit 30 described above, whereby the first and second counters C1 and C2 of the bit synchronization signal generator 10 are provided. Will be cleared.

On the other hand, the frame synchronization signal output from the frame synchronization signal generation unit 60 is counted by the frame number counting unit 70 and the frame number is the first and second comparators of the traffic channel strobe signal generator 90 to be described later. The first and second comparators CP4 and CP5 are inputted to the data input terminals P0 to P4 of the CP4 and CP5, and the counters C7 and C8 are input to the respective data input terminals P0 to P4. By comparing the frame number counted by < RTI ID = 0.0 >) < / RTI > and the reference data input to the reference data input terminals Q0 to Q4 coupled with the power supply voltage Vcc, the two data values match to output a high level output signal.

At this time, when the frame number data input from the frame number counting unit 70 to the data input terminals P4 to P0 is 0 1100, that is, 12 is input, the output signal from the first comparator CP4 is shown in FIG. ), An output signal appears, and the output signal from the second comparator CP5 has the frame number data input from the frame number counting unit 70 to the data input terminals P4 to P0 1 1001, that is, 25. When is inputted, the output signal appears as shown in FIG.

Subsequently, the output signals of the comparators CP4 and CP5 are ORed through the OR gate OR and then represented as an inverted output signal through the inverter IV22 as shown in FIG. 9E. Is a waveform that is logically multiplied with a frame synchronization signal as shown in FIG. 9 (b) input from the frame synchronization signal generator 60 so that an output signal for the low speed coupled control channel does not appear as shown in FIG. Will be output.

Subsequently, the D-flip-flop F3 divides and outputs a signal as shown in FIG. 9 (f) output through the AND gate AND5 to the multiplexer MUX. The output signal Q, in accordance with the control signal from the flip-flop F4; ) Are selectively output as waveforms of two frame periods, respectively, as shown in Figs. 9 (g) and (h).

Next, the signal Q, which is output from the multiplexer MUX, ) Are logically multiplied by the signal input through the inverter IV22 and the AND gate AND6 and output as shown in FIGS. 9 (i) and (j), respectively. By multiplying the timeslot strobe signal input from the signal generator 50 through the AND gate AND7, the strobe signal for each traffic channel of two frame periods as shown in FIGS. Will print.

That is, according to the above embodiment, a time slot synchronizing signal having a period of 156.25 bits is first generated based on a 13 MHz reference clock, and then the current time slot number is calculated based on the count value of the time slot synchronizing signal.

The time slot strobe signal and the frame synchronization signal are generated using the calculated time slot number, and then the strobe signal for the traffic channel is generated based on the count value obtained by counting the time slot strobe signal and the frame synchronization signal. .

In addition, this invention is not limited to the said Example, It can implement in a various deformation | transformation in the range which does not deviate from the technical summary of this invention.

As described above, according to the present invention, in transmitting the traffic data from the terminal to the base station in a half rate method, the traffic channel is allocated to the traffic channel based on the time slot number assigned through the base station and a 13 MHz reference clock generated by itself. A traffic channel strobe signal generator of a personal communication terminal capable of generating a strobe signal for a personal computer can be realized.

Claims (1)

In a personal communication system configured to form a time slot of 156.25 bits with each data bit having a length of 48 clocks based on a 13 MHz clock, clock generation means for generating a reference clock of 13 MHz, and the reference. A bit synchronous signal generating means for generating a bit synchronous signal based on a clock and a frame start signal, a time slot synchronous signal generating means for generating a time slot synchronous signal based on the bit synchronous signal and a reference clock, and the time slot synchronous signal A time slot number counting means for counting and outputting a current time slot number, a time slot number obtained by adding 3 to an externally assigned time slot number, and a time slot number counted by the time slot number counting means, thereby comparing both data; A time slot strobe signal output means for outputting a time slot strobe signal corresponding to a period in which the time period coincides with the time slot; Frame synchronous signal generating means for outputting a frame synchronous signal based on the time slot number output from the call counting means, frame number counting means for counting the frame synchronous signal outputted from the frame synchronous signal generating means and outputting a frame number; After generating the strobe signal of the traffic channel based on the frame number counted by the frame number counting means, the corresponding traffic of two frame periods based on the traffic channel strobe signal and the frame synchronous signal outputted from the frame synchronous signal generating means. Traffic channel strobe signal generator of a personal communication terminal, characterized in that it comprises an output means for outputting a strobe signal of the channel.