KR0166155B1 - Semiconductor esd protection circuit improved by constant current distribution - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

Electrostatic discharge protection circuit in semiconductor device.

2. The technical problem to be solved by the invention:

The present invention provides an electrostatic protection circuit capable of preventing thermal destruction of a semiconductor device by forming a current path by operating all of the MOS transistors.

3. Summary of the solution of the invention:

The drain electrode and the source electrode have ladder-type enmotransistors separated in the wells, and the source electrode and the drain electrode are constituted by an LDD-type en-diffusion junction, and the drain region of the first MOS transistor is formed by the second morse. It is to provide a structure separated from the source region of the transistor.

4. Important uses of the invention:

Circuit for protecting a semiconductor memory device.

Description

Improved Semiconductor Static Protection Circuit with Constant Current Distribution

FIG. 1 is a vertical cross-sectional view of an enmo transistor according to the prior art modeled by a resistor.

2A is a layout plan view of a conventional electrostatic discharge protection circuit.

FIG. 2B is an equivalent circuit diagram for FIG. 2A.

FIG. 2C is a cross-sectional view of FIG. 2A.

3A is a layout plan view of a MOS transistor according to the present invention.

FIG. 3B is an equivalent circuit diagram for FIG. 3A.

3c is a cross-sectional view of FIG. 3a.

4 is a diagram showing a simulation result when applying an electrostatic discharge stress voltage to a conventional electrostatic discharge protection circuit.

5 is a diagram showing a simulation result when the electrostatic discharge stress voltage is applied to the electrostatic discharge protection circuit according to the present invention.

6 compares the structure of the conventional static discharge protection circuit in the temperature distribution for the silicon single crystal of the MOS transistor with the structure of the static discharge protection circuit of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor electrostatic discharge protection circuit.

In general, when an electrostatic discharge (ESD) pulse is applied to a semiconductor memory device, a high current flows into the semiconductor memory device. In general, input and output protection circuits have a plurality of MOS transistors connected in parallel, and the ESD pulses are thermally dissipated within the device when the incoming high current flows uniformly into the plurality of MOS transistors. However, when the high current does not flow evenly through all MOS transistors, a local current path is formed which thermally destroys the device. After applying an ESD stress voltage (thousands of volts in the case of a Human Body Model (HBM)), the current path from the inside of the semiconductor memory device until the power supply voltage consumption region is used to examine the reaction inside the semiconductor memory device. It can be configured by dividing the first resistance effect with respect to the second resistance effect in the power supply voltage consumption region.

FIG. 1 is a vertical cross-sectional view of an enmo transistor according to the prior art modeled by a resistor.

Referring to FIG. 1, the first resistance effect may include a metal line resistor R1, a contact resistor R2, a diffusion resistor R3, and the like of the drain 1 region. The second resistor effect may include a continuous resistor such as spacer part resistors R4 and R6 and a channel resistor R5. In addition, the continuous resistance such as the metal line resistance R9, the contact resistance R8, and the diffusion resistance R7 on the source 2 region side is the same as the first resistance effect. On the other hand, as the first resistance increases within the metal line failure threshold, the input current decreases, and thus, the total current reaching the power supply voltage consumption region decreases, thus consuming lower currents, thereby exhibiting ideal ESD characteristics. have. In addition, when the ESD stress voltage is applied, the device has a parasitic NPN bipolar transistor operation between the drain 1, the bulk 3, and the source 2 to form a current path, so that the smaller the second resistance effect generated by the current path, the more ideal for the high current. ESD characteristics. That is, the ESD characteristics may be improved when a plurality of NMO transistors are turned on at the same time to consume an equal current in the power consumption region.

2A is a layout plan view of a conventional ESD protection device.

FIG. 2A will be described with reference to FIGS. 2B and 2C. FIG. 2B is an equivalent circuit diagram for FIG. 2A. 2c is a cross-sectional view of FIG. 2a. It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

Referring to FIGS. 2A, 2B, and 2C, enmotransistors 100, 101, 102, and 103, which are ESD protection elements, are formed on the substrate 10. The source regions 11 and the drain regions 12 are typically formed by diffusing a high concentration of Y-type impurities on the substrate 10, respectively. The contact between the source regions 11 and the drain regions 12 and the drain electrodes 13A and 13B, which are metal lines, and the source electrodes 14A, 14B, and 14C is the same as that shown in FIG. As formed by the contacts 15. In addition, the gate electrodes 16, 17, 18, and 19 overlapping the space between the source regions 11 and the drain regions 12 are separated by a thin film gate insulating layer 20. Field 11 is connected to a ground power supply VSS. Referring to the operation, when an ESD pulse is applied to the conventional NMOS transistors 100, 101, 102, and 103, the current path flows only in one direction of the source. In more detail, the conventional ESD protection devices, that is, the enMOS transistors 100, 101, 102, and 103, all operate before the avalanche breakdown occurs, so that a current path is formed. After generation, the movement of the hole among the electron-hole-pairs generated in the depletion region of the drain regions 12 affects the current path, thereby causing the substrate 15 to contact the substrate 15. The path is limited by the perfume of effective spreading resistance up to (10). That is, considering the effective dispersion resistance, the effective dispersion first resistance RS1 from the drain 13A to the source 14A of the enmo transistor 100 is source 14B at the drain 13A of the enmo transistor 101. Less than the overall effective dispersion second resistance (RS2). This means that the larger the effective dispersion resistance, the faster the voltage is triggered and the current is clamped in the snap-back region. Therefore, when a large amount of current flows from the drain 13A to the source 14B of the enmo transistor 101 and the enmo transistor 101, the potential of the enmo transistor 102 is raised to increase the potential of the enmo transistor. The source 14C potential of the MOS transistor 103 becomes smaller than the source 14B potential of the 102 so that the current of the MOS transistor 103 increases.

FIG. 4 is a diagram illustrating a simulation result when the ESD stress voltages of the NMO transistors 100, 101, 102, and 103 are applied.

Referring to FIG. 4, a human body model (HBM) static electricity of 3000 volts (V) as a ground power source is manufactured with a channel width of 300 μm, an input gate length of 1 μm, and an oxide thickness of 120 μm. When applied, the current distribution in the initial snap-back region is shown. Only two of the MOS transistors 101, 103, which are 1/2 of the MOS transistors 100, 101, 102, 103 configured in the initial snap-back region, operate, and the voltage flowing into the drains 3A, 3B is clamped and flows enough electrons. When a -hole-pair is generated, the enMOS transistors 100 and 102 which are not operated by affecting other transistors also form a current path.

As can be seen in FIG. 5, when the high current does not flow uniformly to all of the MOS transistors, there is a problem in that the device is thermally destroyed by forming a local current path.

Accordingly, an object of the present invention is to provide an electrostatic discharge protection circuit capable of uniformly forming a current path with MOS transistors, which are electrostatic discharge elements, when high current flows into a semiconductor memory device.

Another object of the present invention is to provide an electrostatic discharge protection circuit configured such that a parasitic effect of a MOS transistor, an electrostatic discharge element, extends to at least a neighboring MOS transistor.

It is still another object of the present invention to provide an electrostatic discharge protection circuit that can eliminate the cause of malfunctions when high current flows into the semiconductor memory device.

In the present invention to achieve the above object of the present invention, in the electrostatic discharge protection circuit, the drain region or source region of the first MOS transistor in the electrostatic discharge protection circuit and the source region or drain region of the second MOS transistor And wherein the drain region of the first MOS transistor is connected to an output pad and the source region is connected to a ground power source.

In addition, in the present invention to achieve the above object of the present invention, in the electrostatic discharge protection circuit, the gate electrode channel length of the first MOS transistor and the drain electrode and the second MOS transistor in the electrostatic discharge protection circuit The distance between the source electrode of the MOS transistor is different, and the distance between the contact for connecting the gate electrode and the drain electrode of the first MOS transistor and the distance between one interface of the contact and the drain electrode are different. The drain region or the source region of the first MOS transistor has a well separated from the drain region or the source region of the second MOS transistor.

In order to achieve the above object of the present invention, the present invention provides an electrostatic discharge protection circuit comprising: a high concentration of a second conductive drain region and a source region formed at regular intervals in a first conductive substrate; Insulating films formed on a portion of the substrate; Drain electrodes and source electrodes formed on the drain regions and a portion of the source regions, respectively; It provides a static discharge protection circuit having a gate electrode formed on a portion of the center in the insulating film.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

3A is a layout plan view of an electrostatic discharge protection circuit according to an embodiment of the present invention. 3a will be described with reference to FIGS. 3b and 3c. FIG. 3B is an equivalent circuit diagram for FIG. 3A. 3c is a cross-sectional view of FIG. 3a.

Referring to FIGS. 3A, 3B, and 3C, the drain electrode 13A and the source electrode 14B are separated into the wells, having substantially the same configuration as described in FIGS. 2A, 2b, and 2C. Ladder (Ladder) is a structure having the MOS transistors (100, 101, 102). In addition, the source electrode 14A and the drain electrode 13A are formed of an N + diffusion junction in the form of a lightly doped drain (LDD). Referring to FIG. 3C, the electrostatic discharge protection circuit includes the high concentration of the N-type drain regions 21, 22, 23 and the source regions 21 ′, 22 ′, 23 ′ formed at regular intervals in the substrate 10. ), Drain electrodes formed on portions of the substrate 10, the drain regions 21, 22, and 23, and portions of the source regions 21 ′, 22 ′, and 23 ′, respectively. Fields 13A, 13B, 13C, source electrodes 14A, 14B, and 14C, and gate electrodes 16, 17, and 18 formed in a central portion of the insulating layers 20. Meanwhile, when an ESD pulse is applied to the NMO transistors 100, 101, and 102, which are the electrostatic discharge elements, the channel length L1 of the gate electrode 16 may correspond to the drain electrode 13A and the source electrode. If the distance L2 between 14B is sufficiently smaller, a current path is formed in the direction of the gate electrode 16 so that the enmo transistor 100 is operated. Enmotransistors 101, 102 and enmotransistors 100, 101, and 102, which are not shown in the drawing, are also connected in parallel by the same method as the enmotransistor 100. It works. In addition, the distance L2 between the drain electrode 13A and the source electrode 14B is sufficiently larger than the channel length L1 so that parasitic bipolar transistors 100P, 101P, and 102P in the separated region are initially formed in the snap-back. Does not work enough. In addition, among the electron-hol-pairs generated in the drain depletion region of the enmo transistor 100, the effect of the bulk dispersion resistance due to the hole on the adjacent enmo transistor 101 is influenced by the channel region resistance. Since it is less than, it is possible to extinguish the ESD pulse while minimizing the influence of the adjacent NMO transistors 101 and 102. In the new electrostatic discharge protection circuit of the separated drain or source structure, the entire enmotransistors 100, 101, and 102 operate even in the snap-back region after the ESD pulse is applied. Therefore, it works as a better ESD protection circuit than conventional ESD protection circuit structure.

5 is a diagram showing a simulation result for the ESD protection circuit according to an embodiment of the present invention.

Referring to FIG. 5, the channel width is 300 mu m, the gate electrode length is 1 mu m, the distance L2 between the drain electrode 13A and the source electrode 14B is 2 mu m, and the oxide film thickness is 120 mu m. In this state, when 3000V HBM ESD pulse is applied as the VSS, the current distribution in the initial snap-back area for the ESD protection circuit is shown. It can be seen that the enmo transistors 100, 101, 102, and 103 of FIG. 5 operate only 1/2, while the enmo transistors 100, 101, and 102 of FIG. 4 all operate to form a current path. have. In addition, as time increases, the current increases, and the parasitic horizontal bipolar transistors 100P, 101P, and 102P operate in separate drain or source regions as well as the MOS transistors 100, 101, and 102.

6 compares the conventional ESD protection circuit structure in the temperature distribution for the silicon single crystal of the MOS transistor with the ESD protection circuit structure of the present invention.

Referring to FIG. 6, as can be seen from the figure, the structure according to the embodiment shows much better characteristics with respect to the temperature distribution than the conventional structure.

As described above, the ESD protection circuit according to the embodiment of the present invention has the advantage that all the MOS transistors are operated to form a current path, thereby preventing the semiconductor device from being thermally destroyed. There is also an advantage that the temperature distribution is better than the conventional structure. In addition, the performance of the semiconductor device can be improved regardless of process changes and environmental conditions.

Claims (7)

A semiconductor device having an electrostatic discharge protection circuit, wherein the drain region or source region of the first MOS transistor in the electrostatic discharge protection circuit is separated from the source region or the drain region of the second MOS transistor, and the drain region of the first MOS transistor. And a source region connected to a ground power source. The electrostatic discharge protection circuit according to claim 1, wherein the MOS transistor is an N-type transistor or a P-type transistor. A semiconductor device having an electrostatic discharge protection circuit, wherein the distance between the gate electrode channel length of the first MOS transistor and the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor are different in the electrostatic discharge protection circuit. And a distance between the contact for connecting the gate electrode and the drain electrode of the first MOS transistor and a distance between the contact and one interface of the drain electrode, wherein the drain region or the source region of the first MOS transistor is And a well separated from the drain region or the source region of the second MOS transistor. 4. The electrostatic discharge of claim 3, wherein a distance between the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor is about 1.2 times or more than the length of the gate electrode channel of the first MOS transistor. Protection circuit. 4. The electrostatic discharge protection circuit according to claim 3, wherein the gate electrode and the drain electrode (or source electrode) are connected to a ground power source. 4. The electrostatic discharge protection circuit according to claim 3, wherein the MOS transistor is an N-type transistor or an MOS transistor. An electrostatic discharge protection circuit in a semiconductor device, comprising: a high concentration of a second conductive drain region and a source region formed at regular intervals in a first conductive substrate; Insulating films formed on a portion of the substrate; Drain electrodes and source electrodes formed on the drain regions and a portion of the source regions, respectively; And a gate electrode formed at a central portion of the insulating layers.