KR0163866B1 - Wire error prevention type lead frame - Google Patents
Wire error prevention type lead frame Download PDFInfo
- Publication number
- KR0163866B1 KR0163866B1 KR1019950018130A KR19950018130A KR0163866B1 KR 0163866 B1 KR0163866 B1 KR 0163866B1 KR 1019950018130 A KR1019950018130 A KR 1019950018130A KR 19950018130 A KR19950018130 A KR 19950018130A KR 0163866 B1 KR0163866 B1 KR 0163866B1
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- Prior art keywords
- inner lead
- semiconductor package
- lead
- wire
- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 내부리드의 선단부분을 반도체 패키지의 두께 방향에 대하여 아래쪽으로 구부러지게 제작함으로써, 반도체 패키지를 장시간 열적 신뢰도 측정 등과 같은 가혹한 환경에 노출시킬 때에 있어서, 성형수지와 리드프레임간의 열팽창 계수의 차이로 인하여 내부리드의 반도체 패키지 나비 방향의 거동(擧動)과 반도체 패키지 내의 금선 불량(와이어 힐 크랙)을 방지하는 효과를 나타내는 것을 특징으로 한다.According to the present invention, the tip of the inner lead is bent downward with respect to the thickness direction of the semiconductor package, so that the thermal expansion coefficient between the molding resin and the lead frame is different when the semiconductor package is exposed to harsh environments such as thermal reliability measurement for a long time. Due to this, it is characterized in that it exhibits an effect of preventing the behavior of the inner lead in the direction of the semiconductor package butterfly and the failure of the wire wiring (wire heel crack) in the semiconductor package.
Description
제1도는 종래 기술에 따른 홈을 갖는 사두(巳頭)형 리드페리임을 도입한 반도체 패키지의 단면도.1 is a cross-sectional view of a semiconductor package incorporating a quadruple lead ferriment with grooves according to the prior art.
제2도는 종래 기술에 따른 홈을 갖는 사두형 리드프레임의 평면도.2 is a plan view of a quadruple leadframe with grooves according to the prior art.
제3도는 본 발명에 따른 리드프레임을 갖는 반도체 패키지의 단면도.3 is a cross-sectional view of a semiconductor package having a lead frame according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 반도체 칩 12 : 본딩 패드10 semiconductor chip 12 bonding pad
20 : 다이 패드 22 : 접착제20: die pad 22: adhesive
30 : 와이어 40,41 : 내부리드30: wire 40,41: inner lead
42 : 홈 50 : 외부리드42: groove 50: external lead
60 : 수지 90,100 : 반도체 패키지60: resin 90,100: semiconductor package
본 발명은 플라스틱 패키지의 리드프레임에 관한 것으로써, 더욱 상세하게는 내부리드의 와이어 힐 부분에 발생되는 힐 크랙을 방지하는 금선 불량 방지용 리드프레임에 관한 것이다.The present invention relates to a lead frame of a plastic package, and more particularly, to a lead wire for preventing a defect of gold wire preventing heel cracks generated in a wire heel portion of an inner lead.
와이어 본딩법은 반도체 칩상에 형성된 본딩 패드와 리드프레임의 내부리드를 와이에 의해 전기적으로 연결하는 방법으로써, 반도체 패키지의 대량 생산이나 제작 단가면에서 실용성이 높으나, 패키지가 수지의 성형 온도보다 낮은 온도에서 변화되는 열적 환경(예를 들면, 장시간 열적 신뢰도 측정, Temperature Cycling)에 노출되면, 패키지 내부의 내부리드 팁(Tip)상의 와이어 힐 부분이 인장력 또는 수축력을 주기적으로 받게 되어 크랙이 발생되는 단점이 있다.The wire bonding method is a method of electrically connecting a bonding pad formed on a semiconductor chip and an internal lead of a lead frame by wires. The wire bonding method has high practicality in mass production or manufacturing cost of a semiconductor package, but the package is lower than the molding temperature of the resin. When exposed to a thermal environment (e.g., temperature cycling, temperature cycling) for a long time, the wire heel on the inner tip of the package receives a tensile or contracting force periodically, causing a crack. have.
제1도는 종래 기술에 따른 홈을 갖는 사두형 리드프레임을 도입한 반도체 패키지의 단면도이다.1 is a cross-sectional view of a semiconductor package incorporating a quadruple lead frame having a groove according to the prior art.
제2도는 종래 기술에 따른 홈을 갖는 사두형 리드프레임의 평면도이다.2 is a plan view of a quadruple leadframe with grooves according to the prior art.
제1도 및 제2도를 참조하면, 반도체 패키지(90)는 다이 패드(20)와 반도체 칩(10)이 접착제(22)에 의해서 접착되어 있고, 상기 반도체 칩(10)상에 형성된 본딩패드(12)와 내부리드(40)가 와이어(30)에 의해서 전기적으로 연결되어 있고, 상기 반도체 칩(10), 다이 패드(20) 및 내부리드(40)가 수지(60)로 봉지되어 있고, 상기 내부리드(40)와 일체형인 외부리드(50)가 수지(60)에 대하여 노출된 구조를 갖는다.Referring to FIGS. 1 and 2, in the semiconductor package 90, a die pad 20 and a semiconductor chip 10 are bonded to each other by an adhesive 22, and a bonding pad formed on the semiconductor chip 10. 12 and the inner lead 40 are electrically connected by a wire 30, the semiconductor chip 10, the die pad 20 and the inner lead 40 is sealed with a resin 60, The outer lead 50 integral with the inner lead 40 has a structure exposed to the resin 60.
보다 상세히 말하면, 물결 모양으로 형성된 내부리드(40)는, 그의 와이어 본딩된 팁(Tip)부분이 사두(巳頭)형으로 형성되어 있고, 그 선단부의 외부리드(50) 방향으로 이웃하는 부분에 복수개의 홈(42)이 형성되어 있는 구조를 갖는다.More specifically, the wavy inner lead 40 is formed in the shape of a quadrangular tip of the wire bonded tip thereof, and is adjacent to a portion adjacent to the outer lead 50 in the tip portion thereof. It has a structure in which the some groove 42 is formed.
전술한 종래 기술에 따른 구조 및 그 의외에 여러 방법들이 제시되었으나 구체적인 방안이 되지못한 이유를 기술하면 다음과 같다.Although various methods have been proposed in addition to the structure according to the related art described above, the reason why the specific method is not described is as follows.
첫째, 성형수지의 열팽창 계수를 리드프레임의 열팽창 계수보다 크게 한다.First, the thermal expansion coefficient of the molding resin is made larger than the thermal expansion coefficient of the lead frame.
그러나, 현실적으로 성형수지의 물성을 변경한다는 것은 추가적인 비용 발생을 야기할 뿐 아니라 패키지 크랙을 유발시키는 요인이 되기도 한다.However, in reality, changing the properties of the molding resin not only incurs additional costs but also causes package cracks.
둘째, 리드프레임의 소재를 변경한다.Second, change the material of the lead frame.
그러나, 통상 사용되는 구리리드프레임은 전기적인 특성, 단가 및 작업성 또한 양호하기 때문에 소재의 변경은 곤란하다.However, since the commonly used copper lead frame is also excellent in electrical characteristics, unit cost and workability, it is difficult to change the material.
세째, 성형수지와 리드프레임의 접착력을 높인다.Third, increase the adhesion between the molding resin and the lead frame.
전술한 종래 기술에서 기술한 바와 같이, 내부리드는 스티치 본딩되는 부분을 사두형으로 제작되고, 그의 와이어 본딩되는 길이가 길며 그들간의 간격의 여유가 없을 때에는 그가 홈이 형성된 물결 형상으로 제작되지만, 현재의 추세인 다핀 반도체 패키지에서는 적용하기 곤란하며, 새로운 공정이 추가되어 작업성을 저하기키는 동시에 반도체 패키지 제작 단가의 증가를 야기한다.As described in the above-mentioned prior art, the inner lead is made into a quadruple stitch-bonded part, and its wire-bonded length is long and there is no space between them, but it is made into a wavy shape in which a groove is formed. It is difficult to apply in the multi-pin semiconductor package, which is a trend of the new technology, and a new process is added to reduce workability and increase the cost of manufacturing a semiconductor package.
또한, 내부리드의 폭이나 간격이 협소할 경우에 그 내부리드상의 홈을 스탬핑 또는 에칭공정으로 그 내부리드 두께의 절반 정도로 가공함으로써, 그 내부리드의 강도(强度)를 떨어뜨려 그의 변형을 야기하였다.In addition, when the width or spacing of the inner lead is narrow, the groove on the inner lead is processed to about half of the thickness of the inner lead by a stamping or etching process, thereby reducing the strength of the inner lead and causing its deformation. .
따라서 본 발명의 목적은 내부리드의 선단부를 굽은 형태로 제작함으로써, 그 내부리드와 수지간의 기계적인 결속을 강화하는 동시에 그 내부리드의 스티치 본딩 부분의 힐 크랙을 방지할 수 있는 금선 불량 방지용 리드프레임을 제공하는데 있다.Accordingly, an object of the present invention is to manufacture the leading end of the inner lead in a bent form, thereby strengthening the mechanical bond between the inner lead and the resin, and at the same time prevent the heel crack of the stitch bonding portion of the inner lead lead wire preventing defects To provide.
상기 목적을 달성하기 위하여, 다이 패드와; 상기 다이패드와 접착제에 의해서 접착된 반도체 칩과; 상기 반도체 칩상에 형성된 복수개의 본딩 패드와; 상기 본딩 패드와 와이어에 의해서 전기적으로 연결된 물결 형상의 내부리드로서, 그의 선단부가 사두(巳頭)형으로 형성되고, 그 선단부와 이웃하는 부분에 복수개의 홈이 형성된 내부리드와; 상기 내부리드와 일체형인 외부리드를 포함하는 반도체 패키지에 있어서, 상기 반도체 패키지 나비 방향의 거동을 방지하는 위해 상기 내부리드의 선단부가 구부러지게 형성된 것을 특징으로 하는 금선 불량 방지용 리드프레임을 제공한다.In order to achieve the above object, a die pad; A semiconductor chip bonded by the die pad and an adhesive; A plurality of bonding pads formed on the semiconductor chip; An inner lead of a wavy shape electrically connected by the bonding pad and the wire, the leading end of which is formed in a quadrangular shape, and the plurality of grooves formed in a portion adjacent to the leading end; A semiconductor package including an external lead integrated with the inner lead, wherein the front end portion of the inner lead is bent to prevent a behavior of the semiconductor package in a butterfly direction.
이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제3도는 본 발명에 따른 리드프레임을 갖는 반도체 패키지의 단면도이다.3 is a cross-sectional view of a semiconductor package having a lead frame according to the present invention.
제3도를 참조하면,, 반도체 패키지(100)의 내부리드(41)는 직선형으로 형성되어 있고, 그의 와이어 본딩된 팁부분이 상기 반도체 패키지(100)의 두께 방향으로 구부러진 구조를 갖으며, 그 이외의 구조는 상기 제1도의 구조와 동일하다.Referring to FIG. 3, the inner lead 41 of the semiconductor package 100 has a straight shape, and a wire bonded tip portion thereof has a structure bent in the thickness direction of the semiconductor package 100. The other structure is the same as that of FIG.
전술한 본 발명의 장점을 기술하면 다음과 같다.The advantages of the present invention described above are as follows.
첫째, 통산적인 리드프레임의 제작은 스탬핑(Stamping) 또는 에칭(Etching)공정으로 제작되는데, 스탬핑 공정을 이용하는 리드프레임은 동일한 공정을 이용하여 리드프레임의 내부리드 선단부를 구부림으로써 공정의 단순화 및 작업 시간의 단축을 기할 수 있다.First, manufacture of lead frame in general is made by stamping or etching process. Lead frame using stamping process uses the same process to bend the inner lead end of lead frame to simplify the process and work time. Can shorten.
둘째, 반도체 패키지를 장시간 열적 신뢰도 측정 등과 같은 가혹한 환경에 노출시킬 때에, 성형수지와 리드프레임간의 열팽창 계수의 차이로 인하여 발생하는 반도체 패키지 나비 방향의 거동(擧動)을 반도체 패키지의 두께 방향으로 굽은 내부리드를 제작함으로써, 내부리드의 반도체 패키지 나비 방향의 거동이 방지되고, 결과적으로 내부리드 팁부분의 와이어 힐에 발생되는 힐 크랙을 방지할 수 있다.Second, when the semiconductor package is exposed to harsh environments such as measuring thermal reliability for a long time, the behavior of the semiconductor package butterfly caused by the difference in thermal expansion coefficient between the molding resin and the lead frame is bent in the thickness direction of the semiconductor package. By manufacturing the inner lead, the behavior of the inner lead in the semiconductor package butterfly direction can be prevented, and as a result, the heel crack generated in the wire heel of the inner lead tip portion can be prevented.
따라서, 본 발명에 따른 구조에 따르면, 내부리드의 스티치 본딩 부분의 와이어 힐 크랙을 방지하는 동시에 리드프레임의 제작공정을 단순화시키며 반도체 패키지의 신뢰성을 향상시킬 수 있는 이점(利點)이 있다.Therefore, according to the structure according to the present invention, there is an advantage that can prevent the wire heel crack of the stitch bonding portion of the inner lead, while simplifying the manufacturing process of the lead frame and improve the reliability of the semiconductor package.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950018130A KR0163866B1 (en) | 1995-06-29 | 1995-06-29 | Wire error prevention type lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950018130A KR0163866B1 (en) | 1995-06-29 | 1995-06-29 | Wire error prevention type lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970003901A KR970003901A (en) | 1997-01-29 |
| KR0163866B1 true KR0163866B1 (en) | 1998-12-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950018130A KR0163866B1 (en) | 1995-06-29 | 1995-06-29 | Wire error prevention type lead frame |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0163866B1 (en) |
-
1995
- 1995-06-29 KR KR1019950018130A patent/KR0163866B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970003901A (en) | 1997-01-29 |
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