KR0163145B1 - A switch apparatus of a digital exchanger - Google Patents

Abstract

The present invention relates to a switch structure of a digital electronic switching system, wherein the processor matching control board includes a buffer for receiving 6-bit control data from a space switch processor; A memory for sequentially storing the output of the buffer; First and second latches for reading and latching control data stored in the memory at a predetermined address; The data latched by the first and second latches receives the D0 to D5 bits according to a clock, converts them into 16.384 MHz 3x2 bits, and outputs the bits. The D6 bit is a control word bit 0 (CWB0) during the clock CP3 low period. A first PLD output as a signal); The data latched by the first and second latches receives the D0 to D5 bits according to a clock, converts them into 16.384 MHz 3x2 bits, and outputs them. The D6 bit is a control word bit 0 (CWB0) during the clock CP3 high period. A second latch for outputting the signal as a second signal to process 7-bit control data, and the space switch matrix comprises: a first latch for receiving the CWBE0 signal and latching the same when / CP3 rising; A second latch configured to receive the CWBE0 signal and latch the CPBE rising signal to output a chip enable 1 signal; A third latch is provided to receive the output of the first latch and latch the CP3 rising signal to output a chip enable 0 signal. Therefore, there is an effect that the space switch capacity can be increased from 64 × 64 to 128 × 128 without changing the conventional SSW self-structure.

Description

Switch structure of digital electronic exchanger

1 is a block diagram showing a switch structure of a general digital electronic exchanger.

FIG. 2 is a partial block diagram of a processor matching portion shown in FIG. 1 when configuring a 128 × 128 switch in accordance with the present invention.

3 is a partial block diagram of the space switch matrix portion shown in FIG. 1 when configuring a 128 × 128 switch according to the present invention.

* Explanation of symbols for the main parts of the drawings

110,130: Central data link block 111,132: Optical transmitter (OTRD)

112,131: Space Switch Link Registration Board (SLIA)

113,133 Photoelectric Converters (OECD)

114,134: Clock and Processor Matching Board (CPIA)

120: space switch block

121,123: Highway Matching Board (HWIA)

122: Space Switch Matrix Board (SMXA)

124: processor matching control board (PICA)

201: Buffer 202: Memory

203,205,301,302,303: Latch 204,206: PLD

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a space switch structure of a digital electron exchanger, and more particularly to a structure constituting a 128 × 128 space switch.

In general, there are a time switch (T) and a space switch (S) in a switch of a digital electronic switch, and the time switch (T) stores a subscriber's information in a memory and then connects time slots to each other in order to connect the call paths with each other. On the other hand, the space switch (S) plays a role of exchanging the highway by tying information coming from the time switch into a bit stream called a highway. In a large-capacity exchanger, a switch composed of only a time switch not only requires complicated hardware but also has limitations due to the speed of memory. Therefore, the switch has a T-S-T structure with a space switch in the middle.

FIG. 1 is a block diagram showing a switch structure of a general digital electronic switching device (e.g., a TDX-10 type). The input central data link (CDL) block, the space switch block (SSW), and the output central data link (CDL) are shown in FIG. Is composed of blocks.

The input central data link (CDL) block consists of an optical transceiver (OTRD: 111), a space switch link matching board (SLIA: 112), a photoelectric converter (OECD: 113), a clock and a processor matching board (CPIA: 114). It receives 131.072Mbps CMI data from the access switching subsystem (ASS) over the optical link and decodes it to output 8.192Mbps, parallel 10-bit subscriber PCM data.

The space switch block (SSW) 120 is composed of a highway matching board (HWIA: 121, 123), a space switch matrix board (SMXA: 122), and a processor matching control board (PICA: 124). 10-bit subscriber PCM data is input and converted from the input highway matching board 121 into 46.3 bits of parallel data of 16.384 Mbps, and then 64 × 64 space switching is performed on the space switch matrix board 122 and output through the output highway matching board. do. At this time, in the space switch matrix board 122, PCM parallel 8-bit data is controlled and output by 16.384Mbps, 3x2 bit 16 parallel control data from the processor matching control board 124, and this output data is output highway. The matching board 123 is supplied. The output highway matching board 123 adds PCM 8-bit data, parity bits, and valid bits and outputs them to the output central data link (CDL) block.

Here, one highway is processed per input and output highway matching board, and the capacity per space switch matrix board is 16 highway input / output processing. Therefore, four space switch matrix boards are required to configure 64 × 64 switching capacity.

In addition, the 3x2 bit control data format supplied from the processor matching control board 124 to the space switch matrix board 122 is as follows.

However, in the conventional switch structure as described above, since the maximum space capacity is 64 × 64, the subscriber of the electronic switchboard is limited accordingly. Therefore, in order to increase the capacity of the subscriber, it is necessary to expand the capacity of the space switch.

Accordingly, an object of the present invention is to provide a switch structure in which the space switch capacity is expanded to 128 × 128 while utilizing the conventional space switch (SSW) structure as it is.

In order to achieve the above object, the device of the present invention,

The predetermined input highway inputted through the central data link is space-divided switched in the space matrix mode according to the control data of the processor matching control board to output the predetermined output highway to the central data link as a predetermined output highway. The processor matching control board,

A buffer for receiving 6-bit control data from the space switch processor;

A memory for sequentially storing the output of the buffer;

First and second latches for reading and latching control data stored in the memory by a predetermined address;

The data latched by the first and second latches receives the D0 to D5 bits according to a clock, converts them into 16.384 MHz 3x2 bits, and outputs the bits. The D6 bit is a control word bit 0 (CWB0) during the clock CP3 low period. First PLC output as a signal):

The data latched by the first and second latches receives the D0 to D5 bits according to a clock, converts them into 16.384 MHz 3x2 bits, and outputs them. The D6 bit is a control word bit 0 (CWB0) during the clock CP3 high period. A second PLC to output as a signal is provided to process 7-bit control data,

The space switch matrix is

A first latch configured to receive the CWBE0 signal and latch it when / CP3 rises;

A second latch configured to receive the CWBE0 signal and latch the CPBE rising signal to output a chip enable 1 signal;

And a third latch for receiving the output of the first latch and latching the CP3 when the CP3 rises to output a chip enable 0 signal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

First, in order to increase the space switch capacity to 128 × 128 without changing the conventional switch block according to the present invention, a control bit should be added by one bit, and thus, the processor matching control board 124 and the space switch matrix board 122 changed accordingly. The interface part of the

That is, for the 128 × 128 switch, the space switch matrix board 122 is increased from four to eight, and the data format for controlling the space switch should be changed as follows.

As shown in the data format proposed in the present invention, the control data D6 bit is added for 128 × 128 switching, and the processor matching control board 124 and the space switch matrix are added to add this bit without changing the edge pin of the conventional SSW block. The board 122 should be improved as shown in FIGS. 2 and 3.

2 is a partial block diagram of the processor matching controller shown in FIG. 1, wherein the processor matching control board 124 includes a buffer 201 for receiving 6-bit control data from a space switch processor (SSP); A memory 202 for sequentially storing the output of the buffer 201; First and second latches 203 and 205 for reading and latching control data stored in the memory 202 by a predetermined address; The data latched by the first and second latches 203 and 205 receives the D0 to D5 bits according to the clock CP3, converts the data into 16.384 MHz 3x2 bits, and outputs the D6 bits in the clock CP3 low period. A first programmable logic device (PLD) 204 for outputting as a control word bit 0 (CWB0) signal; The data latched by the first and second latches 203 and 205 receives the D0 to D5 bits according to the clock CP3, converts them into 16.384MHz 3x2 bits, and outputs the bits. A second PLD 206 for outputting as a control word bit 0 (CWB0) signal is provided to process 7-bit control data.

In FIG. 2, the bits D0 to D6 supplied from the processor are sequentially stored in the memory 202 via the buffer 201. The stored data is read by the address and supplied to the latch circuits 203 and 205. The latch circuits 203 and 205 are output at the CP3 rising timing and supplied to the PLD circuits 204 and 206. The PLD circuit 204 converts the D0 to D5 bits into 16.384 MHz 3x2 bits and outputs them, and outputs the D6 bits to CWBE0 (control word bit enable) in the CP3 low period. The PLD circuit 206 also converts the D0 to D5 bits by 3x2 bits and outputs them, and the D6 bits are output as CWBE0 during the CP3 high period.

3 is a partial block diagram of the space switch matrix unit shown in FIG. 1, the first latch 301 which receives the CWBE0 signal and latches it when / CP3 rises; A second latch 303 which receives the CWBE0 signal and latches it when CP3 rising to output a chip enable 1 signal CEI; A third latch 302 is provided which receives the output of the first latch 301 and latches the CP3 rising signal to output the chip enable 0 signal CE0.

In FIG. 3, the latch 301 is operated when the CWBE0 signal is received and / CP3 rises, and this output signal is supplied to the latch 302 input. When the CP3 rises, the latches 302 and 303 are operated to output CE0 and CE1. .

In the conventional electronic switchboard, the edge pins of the space switch matrix board 122 are 300 pins in total, and 292 pins are in use, and the pins that can be used are 8 pins. Therefore, if the 16 D6 bits supplied from the processor matching board 124 are speed-converted and sent to the space switch matrix board 122 in 8 × 2 bits in parallel, the space switch matrix board 122 passes through the decoding circuit and 16 CE0 to CE15 is created and controlled.

As described above, according to the present invention, a processor matching control board includes a D6 bit additional circuit and a decoding circuit for converting 8 bits x 2 bits into 16 bits in a space switch matrix board is added. There is an effect that the space switch capacity can be increased from 64 × 64 to 128 × 128 without changing the self structure.

Claims (1)

The predetermined input highway inputted through the central data link is space-divided switched in the space matrix mode according to the control data of the processor matching control board, and outputs to the central data link as a predetermined output highway to the space switch device of the digital electronic switch. The processor matching control board may include: a buffer configured to receive 6-bit control data from a space switch processor; A memory for sequentially storing the output of the buffer; First and second latches for reading and latching control data stored in the memory at a predetermined address; The data latched by the first and second latches receives the D0 to D5 bits according to a clock, converts them into 16.384 MHz 3x2 bits, and outputs the bits. The D6 bit is a control word bit 0 (CWB0) during the clock CP3 low period. 1PLD output as a signal: The data latched by the first and second latches receives the D0 to D5 bits according to the clock, converts them into 16.384MHz 3x2 bits, and outputs the D6 bits. A second PLC for outputting a control word bit 0 (CWB0) signal in a period to process 7-bit control data, and the space switch matrix receives the CWBE0 signal and latches it when / CP3 rises; A second latch configured to receive the CWBE0 signal and latch the CPBE rising signal to output a chip enable 1 signal; And a third latch for receiving the output of the first latch and latching the CP3 when the CP3 rises to output a chip enable 0 signal.