KR0161195B1 - Method of planarizing interlayer insulating film of upper part capacitor - Google Patents
Method of planarizing interlayer insulating film of upper part capacitor Download PDFInfo
- Publication number
- KR0161195B1 KR0161195B1 KR1019950019120A KR19950019120A KR0161195B1 KR 0161195 B1 KR0161195 B1 KR 0161195B1 KR 1019950019120 A KR1019950019120 A KR 1019950019120A KR 19950019120 A KR19950019120 A KR 19950019120A KR 0161195 B1 KR0161195 B1 KR 0161195B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- film
- interlayer insulating
- capacitor
- oxide film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000003990 capacitor Substances 0.000 title claims abstract description 14
- 239000011229 interlayer Substances 0.000 title claims abstract description 12
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 239000011521 glass Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000005368 silicate glass Substances 0.000 abstract description 2
- 239000012530 fluid Substances 0.000 abstract 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910008938 W—Si Inorganic materials 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술 분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자 제조 방법Semiconductor device manufacturing method
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
스텍형 구조의 캐패시터와 상부 금속층 사이의 층간절연막을 평탄화시키는 공정으로 종래에는 보로-포스포러스-실리케이트-글래스막을 고온에서 유체로 흐르게 하는 처리법을 사용하여 산화탄탈막이 손상되고 누설전류가 생긴다는 문제점을 해결하고자 함.A process of planarizing an interlayer insulating film between a capacitor having a stack structure and an upper metal layer. A problem of conventionally using a treatment method in which a boro-phosphorus-silicate-glass film is flowed into a fluid at a high temperature causes damage of the tantalum oxide film and leakage current. To solve.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
층간절연막의 평탄화 공정으로 저온으로 절연막을 형성하고 엣치백을 사용하여 표면 평탄화를 이루므로서 전류의 누설을 방지하고 산화탄탈막이 손상되지 않게 평탄화 공정을 수행하고자 함.As the planarization of the interlayer insulating film, the insulating film is formed at low temperature and the surface is planarized using the etching back to prevent the leakage of current and to perform the planarization process so that the tantalum oxide film is not damaged.
4. 발명의 주요한 용도4. Main uses of the invention
반도체 소자의 캐패시터 상부의 절연막 평탄화 공정에 주로 이용됨.Mainly used for the insulating film planarization process on the capacitors of semiconductor devices.
Description
제1a도 내지 제1d도는 본 발명의 캐패시터 상부의 층간절연막 평탄화 방법에 따른 공정도.1A to 1D are process drawings according to the method for planarizing an interlayer insulating film on a capacitor.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 폴리실리콘 전극1 semiconductor substrate 2 polysilicon electrode
3 : 산화탄탈막 (Ta2O5) 4 : 티타늄나이트라이드(TiN)3: tantalum oxide film (Ta2O5) 4: titanium nitride (TiN)
5 : 텅스텐 실리사이드(W-Si) 6, 8 : 산화막(SiO2)5: tungsten silicide (W-Si) 6, 8: oxide film (SiO 2)
7 : 스핀온글래스막(SOG ; Spin On Glass)7: Spin On Glass (SOG)
본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서 특히 유전층으로 산화탄탈(Ta2O5)을 사용하는 캐패시터(Capacitor) 상부의 절연막의 평탄화 공정을 저온으로 실시하므로써, 캐패시터의 전류의 누설을 방지하고 수율을 높이는 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of fabricating a semiconductor device. In particular, the planarization process of an insulating film on a capacitor using tantalum oxide (Ta2O5) as a dielectric layer is performed at a low temperature, thereby preventing leakage of the current and increasing the yield of the capacitor. It relates to a planarization method.
반도체 소자가 고집적화됨에 따라 유전층으로 고유전율을 갖고 스텝커버리지(step coverage)도 개선시킬 수 있는 산화탄탈을 사용하여 왔다. 그런데 스텍(stack)형 구조의 캐패시터와 상부 금속층 사이의 층간절연막을 평탄화시키는 공정으로 종래에는 보로-포스포러스-실리케이트-글래스(BPSG ; Boro-Phosphorous-Silicate-Glass)막을 약 900℃의 고온에서 유체로 흐르게 하는 처리법을 사용하였다.As semiconductor devices have been highly integrated, tantalum oxide has been used, which has a high dielectric constant and improves step coverage as a dielectric layer. However, in the process of planarizing the interlayer insulating film between the stack-type capacitor and the upper metal layer, a conventional Boro-Phosphorous-Silicate-Glass (BPSG) film is fluidized at a high temperature of about 900 ° C. Treatment was used.
이 고온 공정에서 산화탄탈막은 손상(degradation)되고, 누설전류(leakage current)가 생겨 캐패시터의 신뢰성이 떨어진다는 문제점을 가지고 있었다.In this high temperature process, the tantalum oxide film has a problem of being degraded and having a leakage current, thereby reducing the reliability of the capacitor.
따라서, 전술한 바와 같은 문제점을 해결하기 위해 안출된 본 발명은 종래와 마찬가지로 평탄화를 이루면서 저온 처리법을 사용하므로써 전류의 누설을 방지하고 산화탄탈막이 손상되지 않게 하는 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention devised to solve the above problems is to provide a method of preventing the leakage of current and damage to the tantalum oxide film by using a low temperature treatment method while forming a flattening as in the prior art.
본 발명에 따른 캐패시터 상부의 층간 절연막 평탄화 방법은, 반도체 기판에 폴리실리콘 전하저장 전극과 산화탄탈의 유전층과 금속 플래이트 전극으로 이루어진 캐패시터 구조 상에 층간 절연을 위한 제 1 산화막을 증착하는 단계와, 평탄화를 위한 스핀온글래스막을 형성하는 단계와, 상기 산화막과 스핀온글래스막을 엣치백하여 평탄화를 실시하는 단계 및 층간 절연을 위한 제 2 산화막을 증착하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of planarizing an interlayer insulating film on a capacitor, comprising: depositing a first oxide film for interlayer insulation on a capacitor structure including a polysilicon charge storage electrode, a dielectric layer of tantalum oxide, and a metal plate electrode on a semiconductor substrate; Forming a spin-on glass film for etching, performing a planarization by etching back the oxide film and the spin-on glass film, and depositing a second oxide film for interlayer insulation.
이제 본 발명의 캐패시터 상부의 층간 절연막 평탄화 방법의 한 실시예에 대하여 첨부도면을 참조하여 보다 상세하게 살펴보게 된다.An embodiment of the method of planarizing the interlayer insulating film on the capacitor of the present invention will now be described in more detail with reference to the accompanying drawings.
먼저 제1a도에 도시된 바와 같이 반도체 기판(1)에 폴리실리콘 전하저장 전극(Polysilicon storage electrode)(2)이 형성되고 약 200Å의 산화탄탈(Ta2O5)막(3)이 증착되고 티타늄나이트라이드(TiN)(4)와 텅스텐 실리사이드(W-Si)(5)의 플래이트 전극이 형성된 캐패시터 구조 상에 플라즈마 화학기상증착(Cemical Vapor Deposition) 방식으로 약 450℃ 내지 500℃의 온도에서 산화막(SiO2)(6)을 증착한다.First, as shown in FIG. 1A, a polysilicon storage electrode 2 is formed on the semiconductor substrate 1, and a tantalum oxide (Ta 2 O 5) film 3 of about 200 kV is deposited and titanium nitride ( On the capacitor structure on which the plate electrodes of TiN) 4 and tungsten silicide (W-Si) (5) are formed, an oxide film (SiO 2) (at a temperature of about 450 ° C. to 500 ° C. in a plasma vapor deposition method is used. 6) Deposit.
다음으로 제1b도에 도시된 바와 같이 평탄화를 위한 스핀온글래스(SOG ; Spin-On-Glass)막(7)을 형성한다.Next, as shown in FIG. 1B, a spin-on-glass (SOG) film 7 for planarization is formed.
다음으로 제1c도에 도시된 바와 같이 상기 산화막(6)과 스핀온글래스(SOG)막을 엣치백(Etchback)하여 평탄화를 실시한다.Next, as shown in FIG. 1C, the oxide film 6 and the spin on glass (SOG) film are etched back to planarization.
다음으로 제1d도에 도시된 바와 같이 화학기상증착 방식으로 약 450℃ 내지 500℃의 온도에서 산화막(SiO2)(8)을 증착한다.Next, as illustrated in FIG. 1D, an oxide film (SiO 2) 8 is deposited at a temperature of about 450 ° C. to 500 ° C. by chemical vapor deposition.
반도체 소자 제조시, 전술한 바와 같은 본 발명에 따라 층간 절연막의 평탄화를 이루면서 산화탄탈막이 손상되는 것을 방지하고 전류가 누설되는 것을 방지할 수 있다.In manufacturing the semiconductor device, it is possible to prevent the tantalum oxide film from being damaged and prevent current from leaking while the interlayer insulating film is planarized according to the present invention as described above.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019120A KR0161195B1 (en) | 1995-06-30 | 1995-06-30 | Method of planarizing interlayer insulating film of upper part capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019120A KR0161195B1 (en) | 1995-06-30 | 1995-06-30 | Method of planarizing interlayer insulating film of upper part capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970003637A KR970003637A (en) | 1997-01-28 |
| KR0161195B1 true KR0161195B1 (en) | 1999-02-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950019120A KR0161195B1 (en) | 1995-06-30 | 1995-06-30 | Method of planarizing interlayer insulating film of upper part capacitor |
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| Country | Link |
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| KR (1) | KR0161195B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101009019B1 (en) * | 2003-12-29 | 2011-01-17 | 주식회사 포스코 | Sludge ejection device of fluidized reduction furnace |
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1995
- 1995-06-30 KR KR1019950019120A patent/KR0161195B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970003637A (en) | 1997-01-28 |
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