KR20000045367A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20000045367A KR20000045367A KR1019980061925A KR19980061925A KR20000045367A KR 20000045367 A KR20000045367 A KR 20000045367A KR 1019980061925 A KR1019980061925 A KR 1019980061925A KR 19980061925 A KR19980061925 A KR 19980061925A KR 20000045367 A KR20000045367 A KR 20000045367A
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- metal wiring
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 고온공정이 불가능한 Ta2O5막을 유전체막으로 사용하는 캐패시터공정후 상기 캐패시터의 상부전극과 접속되는 금속배선을 셀영역과 주변회로영역의 단차부분에 스페이서형태로 형성하여 상기 금속배선이 리프팅되거나 인접한 금속배선과 브리지되는 것을 방지하여 소자의 특성 및 신뢰성을 향상시키고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, and in particular, a stepped portion of a cell region and a peripheral circuit region connected to a metal wiring connected to an upper electrode of the capacitor after a capacitor process using a Ta 2 O 5 film, which cannot be a high temperature process, as a dielectric film. The present invention relates to a method of forming a spacer in the form of a spacer to prevent the metal wires from being lifted or bridged with adjacent metal wires, thereby improving the characteristics and reliability of the device, thereby enabling high integration of the semiconductor device.
최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.
특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자에서는 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막의 두께를 얇게하거나 또는 전하저장전극의 표면적을 증가시키는 등의 방법이 있다.In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.
도시되어 있지는 않지만, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 살펴보면 다음과 같다.Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.
먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터 및 비트라인을 형성한 후, 상기 구조의 전표면에 층간절연막을 형성한다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, a MOS field effect transistor and a bit line including a gate electrode and a source / drain electrode are formed, and then an interlayer insulating film is formed on the entire surface of the structure.
그 다음 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분 상측의 층간절연막을 제거하여 전하저장전극 콘택홀을 형성하고, 상기 콘택홀을 통하여 소오스/드레인전극과 접촉되는 전하저장전극을 다결정실리콘층 패턴으로 형성한 후, 상기 전하저장전극의 표면에 산화막이나 질화막 또는 산화막-질화막-산화막의 적층구조로된 유전체막을 형성하고, 상기 유전체막상에 플레이트전극을 형성하여 캐패시터를 완성한다.Next, a charge storage electrode contact hole is formed by removing an interlayer insulating layer on an upper portion of the source / drain electrode, which is intended to be a charge storage electrode contact, and polycrystalline a charge storage electrode contacting the source / drain electrode through the contact hole. After forming a silicon layer pattern, a dielectric film having an oxide film, a nitride film, or an oxide film-nitride film-oxide film laminated structure is formed on the surface of the charge storage electrode, and a plate electrode is formed on the dielectric film to complete the capacitor.
상기와 같은 반도체소자의 캐패시터에서 유전체막은 고유전율, 저누설전류밀도, 높은 절연파괴전압 및 상하측 전극과의 안정적인 계면특성 등이 요구되는데, 상기 산화막은 유전상수가 약 3.8 정도이고 질화막은 약 7.2 정도로 비교적 작고, 전극으로 사용되는 다결정실리콘층은 비저항이 800 ∼ 1000μΩ㎝ 정도로 비교적 높아 정전용량이 제한된다.In the capacitor of the semiconductor device, the dielectric film requires high dielectric constant, low leakage current density, high dielectric breakdown voltage, and stable interfacial property with the upper and lower electrodes. The oxide film has a dielectric constant of about 3.8 and the nitride film of about 7.2. It is relatively small, and the polysilicon layer used as an electrode has a relatively high resistivity of about 800 to 1000 mu OMEGA cm.
따라서, 캐패시터의 정전용량을 증가시키기 위하여 기가 비트(giga bit)의 DRAM용 유전체막으로 Ta2O5막과 같은 고유전체막을 사용한다. 상기 Ta2O5막을 이용하여 면적이 작은 셀영역에서 충분한 정전용량을 확보하기 위하여 저장전극을 실린더형으로 형성하고, 또 표면적을 증가시키기 위하여 반구형 실리콘(hemispherical silicon, HSG)을 형성하기도 한다.Therefore, in order to increase the capacitance of the capacitor, a high dielectric film such as a Ta 2 O 5 film is used as a gigabit DRAM dielectric film. The Ta 2 O 5 film is used to form a storage electrode in a cylindrical shape to secure sufficient capacitance in a small area of the cell, and to form a hemispherical silicon (HSG) to increase the surface area.
그러나, 종래기술에 따른 반도체소자의 제조방법에서 유전체막으로 사용되는 Ta2O5막은 저온에서 형성되며, 상부전극 형성후 절연막을 형성한 다음, 평탄화를 위하여 상기 절연막을 고온에서 플로우시키면 상기 Ta2O5막의 특성을 저하되고, 금속배선형성 공정시 소자가 형성되는 셀영역과 주변회로영역간의 단차부분에 불필요한 스페이서형태의 금속층이 형성되면 리프팅되거나 인접한 금속배선과 브리지를 일으키는 문제점이 있다.However, being formed at a low temperature film Ta 2 O 5 is used as a dielectric film in the manufacturing method of a semiconductor device according to the prior art, the formation of the after forming the upper electrode insulating film if the flow to the next, the insulating film for planarization at high temperatures the Ta 2 If the O 5 film is deteriorated, and an unnecessary spacer-type metal layer is formed in the stepped portion between the cell region and the peripheral circuit region in which the device is formed during the metal wiring forming process, there is a problem of lifting or adjacent metal wiring and a bridge.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 고유전물질을 사용하는 캐패시터의 형성공정에서 캐패시터의 상부전극을 형성한 다음, 저온에서 절연막을 형성하여 셀영역과 주변회로영역 간에 단차를 형성한 다음, 상기 상부전극과 접속되는 금속배선 형성시 금속층을 형성한 후 상기 주변회로영역에서 금속배선으로 예정되는 부분을 노출시키는 감광막 패턴을 형성하여 상기 금속층을 식각하여 상기 단차부분에 상기 상부전극과 접속되는 스페이서형태의 금속배선을 형성함으로써 금속배선의 리프팅되거나 인접한 금속배선과 브리지를 일으키는 것을 방지하여 소자의 특성 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the upper electrode of the capacitor is formed in the process of forming a capacitor using a high dielectric material, and then an insulating film is formed at a low temperature to form a step between the cell region and the peripheral circuit region. Next, a metal layer is formed when the metal wiring connected to the upper electrode is formed, and then a photoresist pattern is formed to expose a predetermined portion of the peripheral circuit region to the metal wiring. The metal layer is etched to etch the metal layer. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which prevents lifting of metal wires or bridges with adjacent metal wires by forming a spacer-type metal wire to be connected, thereby improving the characteristics and reliability of the device.
도 1 내지 도 4 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 4 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
10 : 반도체기판 20 : 제1층간절연막10 semiconductor substrate 20 first interlayer insulating film
30 : 하부전극 40 : 상부전극30: lower electrode 40: upper electrode
50 : 제2층간절연막 60 : 금속배선 콘택플러그50: second interlayer insulating film 60: metal wiring contact plug
70a : 금속층 70b : 금속배선70a: metal layer 70b: metal wiring
80 : 제3층간절연막80: third interlayer insulating film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
게이트 전극, 비트라인 캐패시터등 소정의 하부구조물이 형성되어 있는 반도체기판 상부에 제1층간절연막을 형성하되, 상기 소정의 하부구조물이 형성되어 있는 셀영역과 주변회로영역 간에 단차를 형성하는 공정과,Forming a first interlayer insulating film on a semiconductor substrate on which a predetermined substructure, such as a gate electrode and a bit line capacitor, is formed, and forming a step between a cell region and a peripheral circuit region in which the predetermined substructure is formed;
상기 주변회로영역에서 금속배선 콘택으로 예정되는 상기 캐패시터의 상부전극을 노출시키는 금속배선 콘택마스크를 식각마스크로 이용하여 상기 제1층간절연막을 식각하여 금속배선 콘택홀을 형성하는 공정과,Forming a metal wiring contact hole by etching the first interlayer insulating layer using a metal wiring contact mask that exposes an upper electrode of the capacitor, which is intended as a metal wiring contact, in the peripheral circuit region as an etching mask;
상기 금속배선 콘택홀을 통하여 상기 캐패시터의 상부전극과 접속되는 금속배선 콘택플러그를 형성하는 공정과,Forming a metal wiring contact plug connected to the upper electrode of the capacitor through the metal wiring contact hole;
전체표면 상부에 금속층을 형성하는 공정과,Forming a metal layer on the entire surface,
상기 주변회로영역에서 금속배선으로 예정되는 부분을 노출시키는 금속배선 마스크를 식각마스크로 사용하여 상기 금속층을 전면식각하여 상기 금속배선 콘택플러그와 접속되는 금속배선을 형성하되, 상기 금속배선은 상기 단차부분에서 스페이서형태로 형성되도록 하는 공정과,The metal layer is entirely etched by using a metal wiring mask that exposes a predetermined portion of the peripheral circuit area as a metal wiring as an etching mask to form a metal wiring connected to the metal wiring contact plug, wherein the metal wiring is the stepped portion. To form a spacer in the form,
전체표면 상부에 제2층간절연막을 형성하여 평탄화하는 공정을 포함하는 것을 특징으로 한다.And forming a second interlayer insulating film over the entire surface to planarize it.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 소정의 하부구조물이 형성되어 있는 반도체기판(10) 상부에 저장전극 콘택으로 예정되는 영역을 노출시키는 저장전극 콘택홀(도시안됨)이 구비되는 제1층간절연막(20)을 형성한다.First, a first interlayer insulating layer 20 having a storage electrode contact hole (not shown) that exposes a region intended as a storage electrode contact is formed on the semiconductor substrate 10 on which a predetermined substructure is formed.
다음, 상기 제1층간절연막 상부에 상기 저장전극 콘택홀을 매립하는 제1도전층을 형성하고, 전면식각 또는 CMP공정으로 제거하여 상기 저장전극 콘택홀을 통하여 상기 반도체기판(10)과 접속되는 저장전극 콘택플러그(도시안됨)를 형성한다.Next, a first conductive layer is formed on the first interlayer insulating layer to fill the storage electrode contact hole, and is removed by front surface etching or a CMP process to be connected to the semiconductor substrate 10 through the storage electrode contact hole. An electrode contact plug (not shown) is formed.
그 다음, 전체표면 상부에 제2도전층을 형성하고, 하부전극 마스크를 이용한 식각공정으로 상기 저장전극 콘택플러그와 접속되는 하부전극(30)을 형성한다.Next, a second conductive layer is formed on the entire surface, and a lower electrode 30 connected to the storage electrode contact plug is formed by an etching process using a lower electrode mask.
다음, 상기 구조 전표면에 유전체막과 제3도전층을 형성하고, 상부전극 마스크를 이용한 식각공정으로 유전체막 패턴 및 상부전극(40)을 형성한다. 이때, 상기 유전체막은 고유전물질인 Ta2O5막으로 형성하고, 상기 상부전극(40)은 반도체기판(10)의 셀영역 및 주변회로영역에 걸쳐서 형성된다.Next, a dielectric film and a third conductive layer are formed on the entire surface of the structure, and a dielectric film pattern and an upper electrode 40 are formed by an etching process using an upper electrode mask. In this case, the dielectric film is formed of a Ta 2 O 5 film, which is a high dielectric material, and the upper electrode 40 is formed over the cell region and the peripheral circuit region of the semiconductor substrate 10.
그 다음, 전체표면 상부에 제2층간절연막(50)을 형성한다. 상기 제2층간절연막(50)은 비.피.에스.지.(borophospho silicate glass, 이하 BPSG 라 함) 또는 피.에스.지.(phospho silicate glass, 이하 PSG 라 함) 산화막을 사용하여 형성한 다음, 400 ∼ 650℃에서 열처리공정을 실시하거나, 테오스(tetra ethyl ortho silicate glass, 이하 TEOS 라 함) 또는 고밀도플라즈마 유.에스.지.(high density plasma undoped silicate glass, 이하 HDP-USG 라 함) 산화막으로 형성하되, 상기 반도체기판(10)의 셀영역과 주변회로영역 간에 단차가 형성되도록 하여 후속공정에서 형성되는 금속배선 콘택홀이 깊이가 얕게 형성되도록 한다. 그리고, 상기 제2층간절연막(50)은 3000 ∼ 7000Å 범위에서 조절하면서 형성하여 상기 주변회로영역 상의 상부전극(40)과 후속공정에서 형성되는 금속배선 콘택홀이 오버랩되도록 한다.Next, a second interlayer insulating film 50 is formed over the entire surface. The second interlayer insulating film 50 may be formed using an oxide film of borophospho silicate glass (hereinafter referred to as BPSG) or an oxide film of phospho silicate glass (hereinafter referred to as PSG). Then, heat treatment is performed at 400 to 650 ° C., or called tetraethyl ortho silicate glass (TEOS) or high density plasma undoped silicate glass (HDP-USG). ) To form a step between the cell region and the peripheral circuit region of the semiconductor substrate 10 so that the metal wiring contact hole formed in a subsequent process has a shallow depth. The second interlayer insulating film 50 is formed to be adjusted in the range of 3000 to 7000 so that the upper electrode 40 on the peripheral circuit region and the metal wiring contact hole formed in a subsequent process overlap.
다음, 상기 주변회로영역 상의 상부전극(40)에서 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 이용하여 상기 제2층간절연막(50)을 식각하여 금속배선 콘택홀을 형성한다.Next, the second interlayer insulating layer 50 is etched using a metal wiring contact mask that exposes a predetermined portion of the upper electrode 40 on the peripheral circuit area as a metal wiring contact as an etching mask to form a metal wiring contact hole. do.
그 다음, 상기 제2층간절연막(50) 상부에 상기 금속배선 콘택홀이 매립되도록제1금속층을 형성한 다음, 전면식각공정을 실시하여 상기 상부전극(40)과 접속되는 금속배선 콘택플러그(60)를 형성한다.Subsequently, a first metal layer is formed on the second interlayer insulating layer 50 to fill the metal wiring contact hole, and then a front surface etching process is performed to connect the metal wire contact plug 60 to the upper electrode 40. ).
다음, 전체표면 상부에 제2금속층(70a)을 형성한다.Next, a second metal layer 70a is formed on the entire surface.
그리고, 상기 주변회로영역에서 금속배선으로 예정되는 부분을 노출시키는 금속배선 마스크를 식각마스크로 이용하여 상기 제2금속층(70a)을 식각하여 상기 셀영역과 주변회로영역 간의 단차부분에 상기 금속배선 콘택플러그(60)와 접속되는 금속배선(70b)을 스페이서 형태로 형성한다.The second metal layer 70a is etched by using a metal wiring mask that exposes a portion of the peripheral circuit area, which is intended for metal wiring, as an etch mask, and the metal wiring contact is formed at a step portion between the cell region and the peripheral circuit region. The metal wiring 70b connected to the plug 60 is formed in the form of a spacer.
그 후, 상기 구조 전표면에 HDP-USG 또는 에스.오.지.(spin on glass, 이하 SOG 라 함)산화막을 사용하여 제3층간절연막(80)을 형성한다. 이때, 상기 반도체기판(10)의 셀영역과 주변회로영역간에는 스페이서형태의 금속배선(70b)으로 인해 단차부분이 완만해져서 평탄화공정이 용이하다.Thereafter, a third interlayer insulating film 80 is formed on the entire surface of the structure by using an HDP-USG or S.O.O. oxide film. At this time, the stepped portion is smoothed between the cell region and the peripheral circuit region of the semiconductor substrate 10 due to the spacer-type metal wiring 70b, so that the planarization process is easy.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 고유전물질인 Ta2O5막을 유전체막으로 사용하는 캐패시터에서 상부전극을 형성하고, 층간절연막을 형성한 다음, 반도체기판의 셀부와 주변회로부 사이에 발생하는 단차부분에 스페이서 형태의 금속배선을 형성함으로써 상기 금속배선이 리프팅되거나, 인접한 다른 금속배선과 브리지가 발생하는 것을 방지하고 불필요한 금속층을 제거하여 소자의 크기를 줄일 수 있으므로 반도체소자의 고집적화를 가능하게 하고 그에 따른 소자의 특성 및 수율을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, an upper electrode is formed in a capacitor using a Ta 2 O 5 film, which is a high dielectric material, as a dielectric film, an interlayer insulating film is formed, and then a cell portion of a semiconductor substrate is formed. The semiconductor device can be formed by forming a spacer-type metal wiring in the stepped portion between peripheral circuit parts, thereby preventing the metal wiring from being lifted or the occurrence of bridges with other adjacent metal wiring, and reducing the size of the device by removing unnecessary metal layers. There is an advantage to enable high integration of the device and thereby improve the characteristics and yield of the device.
Claims (6)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100804145B1 (en) * | 2001-12-31 | 2008-02-19 | 주식회사 하이닉스반도체 | Method for fabricating capacitor |
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| KR100804145B1 (en) * | 2001-12-31 | 2008-02-19 | 주식회사 하이닉스반도체 | Method for fabricating capacitor |
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