KR0161115B1 - Formation method of wiring layer in semiconductor device - Google Patents
Formation method of wiring layer in semiconductor device Download PDFInfo
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- KR0161115B1 KR0161115B1 KR1019950024992A KR19950024992A KR0161115B1 KR 0161115 B1 KR0161115 B1 KR 0161115B1 KR 1019950024992 A KR1019950024992 A KR 1019950024992A KR 19950024992 A KR19950024992 A KR 19950024992A KR 0161115 B1 KR0161115 B1 KR 0161115B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015572 biosynthetic process Effects 0.000 title claims description 4
- 239000002184 metal Substances 0.000 claims abstract description 96
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 239000000460 chlorine Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 8
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 230000002265 prevention Effects 0.000 claims description 7
- 230000003667 anti-reflective effect Effects 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 87
- 238000001020 plasma etching Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 6
- 239000011148 porous material Substances 0.000 description 5
- 239000006117 anti-reflective coating Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Abstract
본 발명에 의한 반도체 소자의 금속배선층 형성방법은 반도체기판 상부에 장벽금속층을 형성시키고, 장벽금속층 위에 금속층을 형성시키고, 금속층 위에 광반사방지막을 형성시키는 단계와, 장벽금속층과 금속층과 광반사방지막을, 염소(Cl2)가스의 유량이 30 에서 70[sccm], 염화붕소(BCl3)가스의 유량은 10 에서 20[sccm]의 조건에서 선택식각하여 금속배선층을 형성시키는 단계를 포함하여 이루어진다.The method for forming a metallization layer of a semiconductor device according to the present invention includes forming a barrier metal layer on an upper surface of a semiconductor substrate, forming a metal layer on the barrier metal layer, and forming an antireflection film on the metal layer, and forming a barrier metal layer, a metal layer, and an antireflection film. The flow rate of the chlorine (Cl 2 ) gas is 30 to 70 [sccm], the flow rate of boron chloride (BCl 3 ) gas is selectively etched under the conditions of 10 to 20 [sccm] to form a metal wiring layer.
Description
제1도는 종래의 반도체 소자의 금속배선층 형성방법을 설명하기 위한 도면.1 is a view for explaining a metal wiring layer forming method of a conventional semiconductor device.
제2도는 본 발명에 의한 반도체 소자의 금속배선층 형성방법을 설명하기 위한 도면.2 is a view for explaining a metal wiring layer forming method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10,20 : 층간절연막 11,11',21,21' : 장벽금속층10,20: interlayer insulating film 11,11 ', 21,21': barrier metal layer
12,12',22,22' : 금속층 13,13',23,23' : 광반사방지막12,12 ', 22,22': Metal layer 13,13 ', 23,23': Anti-reflective film
14,24 : 금속배선층 15,25 : 절연물질막14,24 metal wiring layer 15,25 insulation film
26 : 반도체기판 A,A' : 배선영역26: semiconductor substrate A, A ': wiring area
본 발명은 반도체 소자의 금속배선층 형성방법에 관한 것으로, 특히 반도체 소자의 제조공정에 있어서 금속배선층을 형성시킨 후에 진행시키는 평탄화공정에 적당하도록 한 반도체 소자의 금속배선층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring layer of a semiconductor device, and more particularly to a method for forming a metal wiring layer of a semiconductor device suitable for a planarization step of advancing after forming a metal wiring layer in a semiconductor device manufacturing process.
반도체 소자의 제조공정에서 금속배선층을 형성시키기 위한 금속층의 식각은 반응성 이온 식각(RIE; reactive ion etching) 또는 플라즈마 식각(plasma etching)방법을 이용하고 있다.The etching of the metal layer for forming the metallization layer in the manufacturing process of the semiconductor device uses a reactive ion etching (RIE) or plasma etching (plasma etching) method.
제1도는 종래의 반도체 소자의 금속배선층 형성방법을 설명하기 위한 도면으로, 종래의 반도체 소자의 금속배선층 형성방법의 각 단계를 도시한 도면이다.FIG. 1 is a view for explaining a method for forming a metal wiring layer of a conventional semiconductor device, and shows each step of the method for forming a metal wiring layer for a conventional semiconductor device.
이하 첨부된 도면을 참고로 종래의 반도체 소자의 금속배선층 형성방법을 설명하면 다음과 같다.Hereinafter, a metal wiring layer forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.
종래의 반도체 소자의 금속배선층을 형성시키기 위해서는 우선 제1도의 (a)와 같이, 반도체기판 또는 반도체기판에 형성시킨 반도체소자의 상면에서 콘택(contact)부위에 콘택홀(contact hole)을 형성시킨 층간절연막(이하 층간절연막이라함)(10)의 위에 장벽금속층(barrier metal)(11)과 금속층(12)과 광반사방지막(anti reflective coating)(13)을 순차적으로 형성시킨다.In order to form a metal wiring layer of a conventional semiconductor device, first, as shown in FIG. 1A, an interlayer in which contact holes are formed in a contact portion on a semiconductor substrate or an upper surface of a semiconductor device formed on the semiconductor substrate is formed. A barrier metal layer 11, a metal layer 12, and an anti reflective coating 13 are sequentially formed on the insulating film 10 (hereinafter referred to as an interlayer insulating film).
이어서 제1도의 (b)와 같이, 광반사방지막(13)의 상면에 배선영역(A영역)을 정의하는 포토레지스트패턴(PR; photoresist pattern)을 형성시킨다.Subsequently, as shown in FIG. 1B, a photoresist pattern PR defining a wiring region A region is formed on the upper surface of the light reflection preventing film 13.
그리고 제1도의 (c)와 같이, 포토레지스트패턴을 마스크(mask)로 하여 층간절연막(10) 위의 장벽금속층과 금속층과 광반사방지막을 선택식각하여 금속배선층(14)을 형성시킨다. 이때, 금속배선층(14)의 최상부에는 광반사 방지막(13')이, 중간에는 금속층(12')이, 최하부에는 장벽금속층(11')으로 이루어지는데, 이는 최상부의 광반사방지막과 최하부의 장벽금속층에 비해 금속층의 식각율이 높아, 금속층(12')은 장벽금속층(11')과 광반사방지막(13')에 비해 더 좁은 폭을 갖게 되어, 금속배선층(14)의 측면 프로파일(profile)에 단차가 형성된다.As shown in (c) of FIG. 1, the metallization layer 14 is formed by selectively etching the barrier metal layer, the metal layer, and the antireflective film on the interlayer insulating film 10 using the photoresist pattern as a mask. At this time, the light reflection prevention layer 13 'is formed at the top of the metal wiring layer 14, the metal layer 12' is at the middle, and the barrier metal layer 11 'is formed at the bottom thereof, which is the top light reflection prevention layer and the bottom barrier. Since the etching rate of the metal layer is higher than that of the metal layer, the metal layer 12 'has a narrower width than the barrier metal layer 11' and the anti-reflective film 13 ', so that the side profile of the metal wiring layer 14 Steps are formed in the.
이어서 제1도의 (d)와 같이, 금속배선층(14)을 형성시킨 층간절연막(10)의 전면에 평탄화를 위한 절연물질층(15)을 형성시킨다.Next, as shown in FIG. 1D, an insulating material layer 15 for planarization is formed on the entire surface of the interlayer insulating film 10 on which the metal wiring layer 14 is formed.
즉, 종래의 반도체 소자의 금속배선층 형성방법에서는 플라즈마 식각장비에서 배선영역을 정의하는 포토레지스트패턴을 마스크로하여 반도체기판 또는 소자형성층(10) 상의 장벽금속층과 금속층과 광반사방지막을 선택식각하여 금속배선층(14)을 형성시키며, 금속층의 식각에 사용되는 식각가스(etch gas)로는 주로 염소(이하 Cl2라 함)가스의 염화붕소(이하 BCl3라 함)의 혼합가스가 주로 사용되고 있다.That is, in the conventional method of forming a metal wiring layer of a semiconductor device, a barrier metal layer, a metal layer, and an antireflection film on a semiconductor substrate or the device forming layer 10 are selectively etched using a photoresist pattern defining a wiring area in a plasma etching apparatus as a mask. The wiring layer 14 is formed, and a mixed gas of boron chloride (hereinafter referred to as BCl 3 ) of chlorine (hereinafter referred to as Cl 2 ) gas is mainly used as an etching gas used to etch the metal layer.
이때, 식각가스인 BCl3와 Cl2의 혼합가스에서 Cl2가스가 금속층 식각의 주가스(main-gas)로 사용되고 있고, BCl3가스는 보조가스(sub-gas)로서 금속층의 내부로 침투(breakthrough)하는 등의 역할을 하게 되며, 플라즈마식각장비의 반응실 내로 주입되는 Cl2가스는 유량이 25 에서 30[sccm]의 범위이고, BCl3가스는 유량이 40 에서 50[sccm]의 범위이다.In this case, Cl 2 gas is used as the main gas of the metal layer etching in the mixed gas of the etching gas BCl 3 and Cl 2 , and BCl 3 gas penetrates into the metal layer as a sub-gas (sub-gas). Cl 2 gas injected into the reaction chamber of the plasma etching equipment has a flow rate in the range of 25 to 30 [sccm], and BCl 3 gas has a flow rate in the range of 40 to 50 [sccm]. .
그러나 종래의 반도체 소자의 금속배선층 식각방법에서는 금속배선층의 수직한 측면 프로파일이 형성되지 않고, 장벽금속층과 광반사방지막의 사이에서의 금속층에 의해 단차가 형성되므로, 고집적화된 반도체 집적회로의 평탄화를 위한 절연물질층에서는 인접한 금속배선층간에 기공(void)(부위)이 발생되었으며, 이러한 기공은 소자의 전기적인 특성을 약화시키고, 반도체 소자제조의 금속배선층 형성 이후의 공정에서 물리적인 충격이 가해지는 경우 소자가 파손되는 크랙 소오스(crack source)로서 작용하게 되는 문제가 발생되었다.However, in the conventional method of etching a metal wiring layer of a semiconductor device, since a vertical side profile of the metal wiring layer is not formed and a step is formed by the metal layer between the barrier metal layer and the anti-reflective coating film, the planarization of the highly integrated semiconductor integrated circuit is performed. In the insulating material layer, voids (sites) are generated between adjacent metal wiring layers, and these pores weaken the electrical characteristics of the device, and when the physical impact is applied in the process after forming the metal wiring layer of semiconductor device manufacturing There is a problem that acts as a crack source (crack source) is broken.
본 발명은 이러한 문제를 해결하기 위해 안출된 것으로, 반도체 소자의 금속배선층 형성방법을 개선하여 평탄화을 위한 절연물질층에 기공이 형성되지 않도록 하는 것이 그 목적이다.The present invention has been made to solve such a problem, and an object thereof is to improve a method of forming a metal wiring layer of a semiconductor device so that pores are not formed in an insulating material layer for planarization.
본 발명에 의한 반도체 소자의 금속배선층 형성방법은 반도체기판 상부에 장벽금속층을 형성시키고, 장벽금속층 위에 금속층을 형성시키고, 금속층 위에 광반사방지막을 형성시키는 단계와, 장벽금속층과 금속층과 광반사방지막을, 염소(Cl2)가스의 유량이 30 에서 70[sccm], 염화붕소(BCl3)가스의 유량은 10 에서 20[sccm]의 조건에서 선택식각하여 금속배선층을 형성시키는 단계를 포함하여 이루어진다.The method for forming a metallization layer of a semiconductor device according to the present invention includes forming a barrier metal layer on an upper surface of a semiconductor substrate, forming a metal layer on the barrier metal layer, and forming an antireflection film on the metal layer, and forming a barrier metal layer, a metal layer, and an antireflection film. The flow rate of the chlorine (Cl 2 ) gas is 30 to 70 [sccm], the flow rate of boron chloride (BCl 3 ) gas is selectively etched under the conditions of 10 to 20 [sccm] to form a metal wiring layer.
제2도는 본 발명에 의한 반도체 소자의 금속배선층 형성방법을 설명하기 위한 도면으로, 본 발명에 의한 반도체 소자의 금속배선층 형성방법의 각 단계를 도시한 도면이다. 이하 첨부된 도면을 참고로 본 발명에 의한 반도체 소자의 금속배선층 형성방법을 설명하면 다음과 같다.2 is a view for explaining a method for forming a metal wiring layer of the semiconductor device according to the present invention, and shows each step of the method for forming a metal wiring layer for the semiconductor device according to the present invention. Hereinafter, a method for forming a metal wiring layer of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
본 발명에 의한 반도체 소자의 금속배선층 형성방법에서는 우선, 제2도의 (a)와 같이, 반도체기판(26) 상부의 층간절연막(20)의 위에 장벽금속층(21)과 금속층(22)과 광반사방지막(23)을 순차적으로 형성시킨다.In the method for forming a metal wiring layer of a semiconductor device according to the present invention, first, as shown in FIG. 2A, the barrier metal layer 21, the metal layer 22, and the light reflection on the interlayer insulating film 20 on the semiconductor substrate 26 are first shown. The prevention film 23 is formed sequentially.
이어서 제2도의 (b)와 같이, 광반사방지막(23)의 상면에 배선영역(A'영역)을 정의하는 포토레지스트패턴(PR')을 형성시킨다.Subsequently, as shown in FIG. 2B, a photoresist pattern PR ′ defining a wiring region A ′ region is formed on the upper surface of the light reflection prevention film 23.
그리고 제2도의 (c)와 같이, 포토레지스트패턴을 마스크로 장벽금속층과 금속층과 광반사방지막을 식각선택성이 없이 식각하여, 장벽금속층(21')과 금속층(22')과 광반사방지막(23') 간의 측면 프로파일에 단차가 형성되지 않은 금속배선층을 형성시킨다.As shown in FIG. 2C, the barrier metal layer, the metal layer, and the antireflective coating layer are etched without etching selectivity using the photoresist pattern as a mask, so that the barrier metal layer 21 ', the metal layer 22', and the antireflective coating layer 23 are formed. A metal wiring layer is formed in which no step is formed in the side profile between the ')'.
이때, 금속배선층은 상단의 폭이 하단의 폭보다 작은 값을 갖도록 형성되어, 단면이 사다리형태로 형성되며, 장벽금속층과 금속층과 광반사방지막을 BCl3가스와 Cl2가스의 혼합가스와, 금속층의 식각을 억제시키기 위한 첨가가스로 이루어진 식각가스로 식각하여 형성되고, 식각가스에서 혼합가스는 Cl2가스의 유량이 30 에서 70[sccm]의 범위이고, BCl3가스의 유량은 10 에서 20[sccm]의 범위로 혼합된 것을 사용하며, 첨가가스는 질소(이하 N2라 함)가스를 사용하여 금속배선층의 측벽에서 금속층의 측벽에 폴리머가 생성되어, 금속층의 식각을 억제시키도록 하기 위하여 N2가스의 유량은 10 에서 30[sccm]의 범위로 하여 사용한다.At this time, the metal wiring layer is formed so that the width of the upper end is smaller than the width of the bottom, the cross section is formed in the form of a ladder, the barrier metal layer, the metal layer and the anti-reflective film is a mixed gas of BCl 3 gas and Cl 2 gas, the metal layer It is formed by etching with an etching gas consisting of additive gas to suppress the etching of the mixed gas, the flow rate of Cl 2 gas in the range of 30 to 70 [sccm], the flow rate of BCl 3 gas is 10 to 20 [ sccm], and the additive gas uses nitrogen (hereinafter referred to as N 2 ) gas to form a polymer on the sidewall of the metal layer at the sidewall of the metallization layer to suppress the etching of the metal layer. 2 Gas flow rate is used in the range of 10 to 30 [sccm].
이어서 제2도의 (d)와 같이, 금속배선층(24)을 형성시킨 층간절연막(20)의 전면에 평탄화를 위한 절연물질층(25)을 형성시킨다.Next, as shown in FIG. 2D, an insulating material layer 25 for planarization is formed on the entire surface of the interlayer insulating film 20 on which the metal wiring layer 24 is formed.
즉, 본 발명에 의한 반도체 소자의 금속배선층 형성방법에서는 종래의 플라즈마 식각장비를 사용하면서, 식각가스의 혼합가스에서는 Cl2가스를 주가스로 사용하면서 BCl3가스를 보조가스로 사용하되, 금속층의 식각을 억제하는 측벽 폴리머를 형성시키기 위한 첨가가스로서 N2가스를 부가하여 금속배선층의 측벽 프로파일에 단차가 형성되지 않도록 하며, 측벽 프로파일의 각도는 플라즈마 식각장비에 인가되는 전력조절과 식각가스의 혼합비율의 조정으로 평탄화를 위한 절연물질층의 형성시에 인접한 금속배선층의 사이에서 기공의 발생이 최대한 방지되는 값을 갖도록 한다.That is, in the method for forming a metal wiring layer of the semiconductor device according to the present invention, while using a conventional plasma etching equipment, in the mixed gas of the etching gas, while Cl 2 gas is used as the main gas, BCl 3 gas is used as an auxiliary gas, N 2 gas is added as an additive gas to form sidewall polymers to suppress etching so that a step is not formed in the sidewall profile of the metallization layer, and the angle of the sidewall profile is a mixture of power control and etching gas applied to the plasma etching equipment. By adjusting the ratio, the formation of the insulating material layer for planarization has a value that prevents the generation of pores as much as possible between adjacent metal wiring layers.
본 발명에 의한 반도체 소자의 금속배선층 형성방법은 종래의 플라즈마 식각장비에서의 실시가 가능하며, 장벽금속층과 반사방지막의 사이에서의 금속층에 의해 금속배선층의 측벽 프로파일에 발생되는 단차의 방지와 측벽 프로파일의 각도조절을 용이하게 할 수 있고, 또한 금속배선층 간에는 평탄화를 위한 절연물질의 형성시에 기공 발생이 억제되어서, 기공발생으로 인한 소자의 동작특성악화 또는 파손 등에 의한 불량율이 저하된다.The method for forming a metal wiring layer of a semiconductor device according to the present invention can be implemented in a conventional plasma etching equipment, and the prevention of the step difference and the sidewall profile generated in the sidewall profile of the metal wiring layer by the metal layer between the barrier metal layer and the antireflection film. The angle can be easily adjusted, and the generation of pores is suppressed during the formation of the insulating material for the planarization between the metal wiring layers, so that the defective rate due to the deterioration or breakdown of the operation characteristics of the device due to the pore generation is reduced.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950024992A KR0161115B1 (en) | 1995-08-14 | 1995-08-14 | Formation method of wiring layer in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950024992A KR0161115B1 (en) | 1995-08-14 | 1995-08-14 | Formation method of wiring layer in semiconductor device |
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| Publication Number | Publication Date |
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| KR970013026A KR970013026A (en) | 1997-03-29 |
| KR0161115B1 true KR0161115B1 (en) | 1999-02-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10629639B2 (en) | 2017-11-16 | 2020-04-21 | Samsung Display Co., Ltd. | Wire including organic layer, display device including the same and method of manufacturing the same |
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1995
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10629639B2 (en) | 2017-11-16 | 2020-04-21 | Samsung Display Co., Ltd. | Wire including organic layer, display device including the same and method of manufacturing the same |
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| KR970013026A (en) | 1997-03-29 |
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