KR0157856B1 - Fabricating method of cmos integrated circuit - Google Patents
Fabricating method of cmos integrated circuit Download PDFInfo
- Publication number
- KR0157856B1 KR0157856B1 KR1019890018566A KR890018566A KR0157856B1 KR 0157856 B1 KR0157856 B1 KR 0157856B1 KR 1019890018566 A KR1019890018566 A KR 1019890018566A KR 890018566 A KR890018566 A KR 890018566A KR 0157856 B1 KR0157856 B1 KR 0157856B1
- Authority
- KR
- South Korea
- Prior art keywords
- manufacturing
- oxide film
- cmos transistor
- polysilicon
- etched
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
내용없음.None.
Description
제1도의 (a) 내지 (d)는 종래 기술에 의한 씨모스(CMOS) 트랜지스터 제조방법을 순차적으로 보인 공정도.(A) to (d) of FIG. 1 are process diagrams sequentially showing a CMOS transistor manufacturing method according to the prior art.
제2도의 (a) 내지 (g)는 본 발명에 의한 CMOS 트랜지스터 제조방법을 순차적으로 보인 공정도.2 (a) to 2 (g) are process diagrams sequentially showing a method of manufacturing a CMOS transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : Si기판 12 : 다결정실리콘11 Si substrate 12 polysilicon
13, 13' : 1,2차 응력이완 산화막 14, 14' : 질화막13, 13 ': 1st and 2nd stress relaxation oxide film 14, 14': nitride film
15 : CVD 산화막 17 : 필드산화막15: CVD oxide film 17: field oxide film
본 발명은 초대규모 집적회로 씨모스(이하, VLSI CMOS라 칭함) 트랜지스터 제조방법에 관한 것으로, 특히, 다결정실리콘(Si)의 회생산화 및 식각을 이용하여 Si반응성 이온식각에 의한 표면손상(surface damage)을 줄일 수 있으며, 새부리(bird's beak)부위를 보다 효과적으로 제거할 수 있게 한 VLSI CMOS 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a super-scale integrated circuit CMOS (hereinafter, referred to as VLSI CMOS) transistor, and in particular, surface damage by Si reactive ion etching using the ash production and etching of polysilicon The present invention relates to a method of manufacturing a VLSI CMOS transistor that can reduce the number of steps and remove the bird's beak more effectively.
일반적으로 VLSI CMOS 트랜지스터는 여러가지 제조방법에 의하여 제조되는 바, 그 중에서 sidewall masked isolation(이하, SWAMI라 칭함)공정에 의한 VLSI CMOS 트랜지스터의 제조방법을 설명하면 다음과 같다.In general, a VLSI CMOS transistor is manufactured by various manufacturing methods. Among them, a method of manufacturing a VLSI CMOS transistor by a sidewall masked isolation (hereinafter referred to as SWAMI) process will be described below.
제1도의 (a)에 도시한 바와 같이, Si기판(1)에 1차 응력이완 산화막(1st stress relief oxide)(2) 및 질화막(3)을 형성하고, 패턴을 형성한 다음, 에칭하며, 붕소 채널 스톱(Boron channel stop)이온을 주입한 후, 레지스트(resist)를 제거하고, (b)에 도시한 바와 같이 2차 응력이완 산화막(4) 및 질화막(5)을 형성한 다음, CVD 산화보호막(6)을 형성하며, (c)에 도시한 바와 같이, CVD 산화보호막(6)을 이방성식각(anisotropic etch)한 다음, CVD 산화보호막(6)을 제거하여 사이드월(sidewall)(7)을 형성하고, (d)에 도시한 바와 같이, 필드(field)산화막(8)을 형성하여 제조하게 된다.As shown in FIG. 1A, a first stress relief oxide 2 and a nitride film 3 are formed on the Si substrate 1, a pattern is formed, and then etched. After implanting the boron channel stop ions, the resist is removed, and as shown in (b), the secondary stress relaxation oxide film 4 and the nitride film 5 are formed, followed by CVD oxidation. A protective film 6 is formed, and as shown in (c), the CVD oxide protective film 6 is anisotropically etched, and then the CVD oxide protective film 6 is removed to remove the sidewall 7. Is formed, and as shown in (d), a field oxide film 8 is formed and manufactured.
그러나 상기한 바와같은 종래의 CMOS 트랜지스터 제조방법은 C2F6등의 반응성이온식각에 의하여 Si기판(1)을 일정깊이로 식각제거함으로써 Si기판(1)에 가해지는 충격에 의하여 결함(defect)이 발생되어 트랜지스터의 특성을 저하시킬 뿐만 아니라 LOCOS 공정시 새부리 부위를 효과적으로 제거하지 못하는 문제점이 있었다.However, in the conventional method of manufacturing a CMOS transistor as described above, the Si substrate 1 is etched away to a certain depth by reactive ion etching such as C 2 F 6 , thereby causing defects due to the impact applied to the Si substrate 1. In addition to the deterioration of the transistor characteristics, there was a problem that can not effectively remove the beak portion during the LOCOS process.
따라서, 본 발명은 상기한 바와 같은 종래의 문제점을 해소하기 위하여 창안한 것으로, 기존의 Si반응성 이온식각에 의한 표면손상을 줄일 수 있으며, 새부리 부위를 보다 효과적으로 제거할 수 있도록 한 것인바, 본 발명을 첨부한 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Therefore, the present invention was devised to solve the conventional problems as described above, it is possible to reduce the surface damage caused by the existing Si reactive ion etching, to be able to remove the beak portion more effectively, the present invention When described in more detail with reference to the accompanying drawings as follows.
본 발명에 의한 VLSI CMOS 트랜지스터 제조방법은 제2도의 (a)에 도시한 바와 같이, Si기판(11)에 다결정실리콘(12), 1차 응력이완 산화막(13), 질화막(14)을 순차로 증착하고, (b)에 도시한 바와 같이 R.I.E(reactive ion etch)를 적용하여 패턴을 형성하며, 붕소 채널 스톱이온을 주입하고, (c)에 도시한 바와 같이, 채널에 2차 응력이완 산화막(13'), 질화막(14'), 전체적으로 CVD 산화막(15)을 증착한 다음, (d)에 도시한 바와 같이 CVD 산화막(15)을 이방성 식각한 후, CVD 산화막(15)을 제거하여, 사이드월(16)을 형성하며, (e)에 도시한 바와 같이, 필드 산화막(17)을 성장시킨다. 이때, 필드 산화막(17)의 새부리(bird's beak) 부분은 다결정실리콘(12)의 내부에 형성되며 에치백(etch back)에 의하여 필드 산화막(17)을 다결정실리콘(12)과 Si기판(11)의 계면까지 식각한 후, 다결정실리콘(12)을 식각하여 (f)에 도시한 바와 같이 액티브영역과 필드분리영역을 형성함과 아울러 LOCOS(local oxidation on silicon)의 새부리 부위를 완전하게 제거시킨다.In the method for manufacturing a VLSI CMOS transistor according to the present invention, as shown in FIG. 2A, the polycrystalline silicon 12, the primary stress relaxation oxide film 13, and the nitride film 14 are sequentially placed on the Si substrate 11. Depositing, applying a reactive ion etch (RIE) as shown in (b) to form a pattern, implanting boron channel stop ions, and as shown in (c), a secondary stress relaxation oxide film ( 13 '), the nitride film 14' and the CVD oxide film 15 as a whole are deposited, and then the CVD oxide film 15 is anisotropically etched as shown in (d), and then the CVD oxide film 15 is removed, The month 16 is formed, and as shown in (e), the field oxide film 17 is grown. At this time, a bird's beak portion of the field oxide film 17 is formed inside the polycrystalline silicon 12 and the field oxide film 17 is etched back to form the polycrystalline silicon 12 and the Si substrate 11. After etching to the interface of, the polysilicon 12 is etched to form an active region and a field separation region as shown in (f) and to completely remove the beak portion of local oxidation on silicon (LOCOS).
이후의 제조공정은 통상적인 방법에 의하여 진행되며, (g)는 제조가 완료된 VLSI CMOS 트랜지스터를 보인 것으로, 도면 중 미설명 부호 18, 18'는 CVD 산화막, 19, 19', 19는 전극을 각각 보인 것이다.Subsequent manufacturing processes are performed by a conventional method, and (g) shows a completed VLSI CMOS transistor, in which, reference numerals 18, 18 'denote CVD oxide films, 19, 19', and 19 electrodes respectively. It is seen.
상기한 바와 같은 본 발명에 의한 VLSI CMOS 트랜지스터 제조방법은 Si기판(11)에 다결정실리콘(12)을 증착하고 패터닝하며, 다결정실리콘(12)의 단차를 형성하여 Si기판(11)의 식각을 대체함으로써 기존의 Si반응성 이온식각에 의한 표면 손상을 줄일 수 있으며, 또한 LOCOS의 새부리 부위만을 다결정실리콘(12)에 형성하고, 필드 산화막(17)을 에치백함과 아울러 다결정실리콘(12)의 식각을 행함으로써 새부리 부위를 보다 효과적으로 완전하게 제거할 수 있는 것이다.In the method of manufacturing a VLSI CMOS transistor according to the present invention as described above, the polycrystalline silicon 12 is deposited and patterned on the Si substrate 11, and a step of the polysilicon 12 is formed to replace the etching of the Si substrate 11. Thus, surface damage due to conventional Si reactive ion etching can be reduced, and only the beak portion of LOCOS is formed in the polysilicon 12, the field oxide film 17 is etched back, and the polysilicon 12 is etched. By doing so, the beak part can be removed more effectively and completely.
이상에서 설명한 바와 같은 본 발명에 의한 VLSI CMOS 트랜지스터 제조방법은 기존의 SWAMI 공정에서와 같은 Si반응성 이온식각에 의한 표면 손상을 감소시킬 뿐만 아니라 새부리 부위를 보다 효과적으로 제거할 수 있는 효과가 있게 된다.The VLSI CMOS transistor manufacturing method according to the present invention as described above not only reduces the surface damage caused by Si reactive ion etching as in the conventional SWAMI process, it is effective to remove the beak portion more effectively.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890018566A KR0157856B1 (en) | 1989-12-14 | 1989-12-14 | Fabricating method of cmos integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890018566A KR0157856B1 (en) | 1989-12-14 | 1989-12-14 | Fabricating method of cmos integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910013474A KR910013474A (en) | 1991-08-08 |
| KR0157856B1 true KR0157856B1 (en) | 1999-02-01 |
Family
ID=19292901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019890018566A KR0157856B1 (en) | 1989-12-14 | 1989-12-14 | Fabricating method of cmos integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0157856B1 (en) |
-
1989
- 1989-12-14 KR KR1019890018566A patent/KR0157856B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR910013474A (en) | 1991-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4746630A (en) | Method for producing recessed field oxide with improved sidewall characteristics | |
| US5747377A (en) | Process for forming shallow trench isolation | |
| US4098618A (en) | Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation | |
| US5512509A (en) | Method for forming an isolation layer in a semiconductor device | |
| US5937310A (en) | Reduced bird's beak field oxidation process using nitrogen implanted into active region | |
| KR0157856B1 (en) | Fabricating method of cmos integrated circuit | |
| US6074933A (en) | Integrated circuit fabrication | |
| KR100186514B1 (en) | Isolation method of semiconductor device | |
| US5962914A (en) | Reduced bird's beak field oxidation process using nitrogen implanted into active region | |
| US5614434A (en) | Method for minimizing the encroachment effect of field isolation structure | |
| KR930005237B1 (en) | Manufacturing method of isolation regions in semiconductor | |
| KR930010096B1 (en) | Isolation method of semiconductor device | |
| KR0161858B1 (en) | Method for isolation of a semiconductor device | |
| GB2237445A (en) | "semiconductor device fabrication using masks" | |
| KR100311172B1 (en) | Method for isolating semiconductor device | |
| KR100446279B1 (en) | Method of etching trench of semiconductor device for forming isolation layer by using shallow trench | |
| KR0140658B1 (en) | Manufacture of element isolation for semiconductor integrated circuit device | |
| KR100242380B1 (en) | Method of forming a field isolation film in a semiconductor device | |
| KR100198600B1 (en) | Method of forming planar isolation area for semiconductor device | |
| KR930010726B1 (en) | Isolation method of semiconductor | |
| KR930008845B1 (en) | Device for seprating method of semiconductor apparatus | |
| KR0151225B1 (en) | Device isolation method of semicondcutor device | |
| KR0182918B1 (en) | Method of fabricating ldd structure of mos transistor | |
| KR100382551B1 (en) | Method for Forming Dual Deep Trench of a Semiconductor Device | |
| KR100400329B1 (en) | Method for forming isolation oxide layer of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20090727 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |