KR0156919B1 - Time measurement and circuit between two non-synchronous pulses - Google Patents

Abstract

A metastable state circuit is provided that detects that when the data edge is too close to the clock edge, it results in a metastable state in the time measurement circuit. When a potential metastable state is detected, the metastable circuit delays the data edge with respect to the clock edge by a known amount to avoid the metastable state. The delayed edge is used to start the time measurement circuit, and the next clock edge is used to stop the time measurement circuit. The known delay is subtracted from the measured time to yield a precise measurement of the elapsed time between the rise of the data edge and the rise of the clock edge when the known delay is added.

Description

Time measuring circuit and method for measuring time between two asynchronous pulses

1 is a timing diagram illustrating a problem involved in time measurement.

2 is a partial view of a timing circuit of the prior art.

3 is a timing diagram for explaining a waveform shown in the circuit of FIG.

4 is a schematic diagram of a non- metastable circuit of the invention.

5-8 are timing diagrams of various states occurring in the non- metastable circuit of FIG.

* Explanation of symbols for main parts of the drawings

11: clock 12,13: data edge

16: flip-flop 17: lamp circuit

18: Start input 19: Stop input

21: metastable window 26, 27, 29: delay

28: multiplexer

The present invention relates generally to time measuring circuits, and more particularly to circuits for measuring elapsed time between two asynchronous electric pulses.

Measurement and use of electronic circuits require that parameters such as switching speed and gate delay time be precisely measured. Usually, the time measurement circuit produces an output proportional to the amount of time that passes between the two events. Typically, each such event is represented by a transition from a logic low state to a logic high state or vice versa. Almost most often the transition or pulse edge is used to trigger the time measurement circuit. The term pulse edge, as will be used herein below, is intended to encompass any transition between logic low state and logic high state or vice versa. Most logic devices recognize floating or falling edges and rarely require both floating or falling edges. Depending on the type of logic device used, the term pulse edge may have been chosen to mean a floating edge, a falling edge, or a combination thereof. A simple way to measure the time between two asynchronous pulse edges, or data edges, is to provide a clock and count the number of clock edges that occur between the data edges. This simple method results in a time measurement as is, which is precisely limited to the speed of the clock used. Since the typical clock period is one nanosecond, the method can hardly be used for picosecond measurement accuracy.

To improve precision, the elapsed time between each data edge and the next clock edge must be measured. This can be done by providing a ramp circuit with an output signal that increases linearly with time. One of the data edges is used to start the ramp circuit, while the subsequent clock edge is used to stop the ramp circuit. One such ramp circuit should be used for each of the two data edges. The ramp circuit has an analog output proportional to the elapsed time between the data edge and the next clock edge. The analog data may be converted to digital data and included in the count of clock pulses described above herein. It should be noted that the lamp circuit can often be taken hundreds or even thousands times longer than the actual event taken to make a measurement. For example, if the elapsed time between the data edge and the next clock edge was 0.5 nanoseconds, a typical lamp circuit may take 500 nanoseconds to measure the elapsed time. In addition, the physical size of the lamp circuit is a function of the length of time to be measured. Therefore, it is useful to minimize the time that should be output by the lamp circuit.

To select the next clock pulse edge that occurs after the data edge, a D-type flip-flop with a data edge coupled to the data (D) input and a clock edge coupled to the clock input is used. Using the device, once the data edge appears on the D input, the D flip-flop output Q will be switched after the next clock edge is applied to the clock input. Thus, the output Q of the D flip-flop will be high when a first clock edge occurs after the data edge. Thus the output of the D flip-flop is coupled to the lamp circuit and used to stop the lamp circuit.

While the basic circuitry works well in theory, a real problem arises when the clock edge and the data edge occur too close together. When the clock edge and the data edge are too close to disturb the setup or lock time of the flip flop, the output of the flip flop is uncertain. The uncertain output is also called metastable. The metastable output may or may not trigger to stop the ramp circuit. Also, the propagation delay of the D-type flip-flop is known to be metastable, so precise time measurement is not possible. The metastable state will eventually drift to a logic high or logic low state, but it may take a number of clock cycles to occur.

Circuits have been devised to reduce the occurrence of metastable states. Usually, three or four D flip-flops in series are used instead of the single D flip-flop described above. By using three flip-flops, the likelihood that the metastable state will reach a logic high or logic low within a clock period is greatly improved. There remains a clear possibility that the metastable state will be transported through a series of flip-flops, but will eventually reach the time measurement circuit. When short clock cycles are used, this is more and more likely.

In order to compensate for the possibility of metastable states, thousands of measurements are usually made and averaged to improve accuracy. Although the method eventually averaged the false data caused by the metastable state, it was chosen to be much longer than a single measurement. Many measurements may actually take several milliseconds or seconds to obtain a precise measurement of an event that only takes a few picoseconds. When thousands or tens of thousands of measurements have to be taken, the additional time cannot be accepted as is for testing semiconductor integrated circuits. In addition, some transient events cannot be repeated and thus repeated measurements cannot be taken. In this case, time measurement in which the error caused by the metastable state is impossible is precisely performed.

It is therefore an object of the present invention to provide a time measurement circuit with improved precision.

Another object of the present invention is to provide a method for measuring elapsed time on the order of several picoseconds.

Another object of the present invention is to provide a time measurement system that reduces the time required for the lamp circuit to be measured.

It is a further object of the present invention to provide a method for measuring elapsed time precisely so that a large number of measurements are not necessary.

It is another object of the present invention to provide a time measurement system that eliminates errors caused by variations in propagation delay of flip-flops operating in a metastable state.

The above and other objects and advantages of the present invention are to detect when the data edge is too close to the next clock edge that will result in a metastable state, and delay the data edge with respect to the clock by a known amount to avoid the metastable state. Is achieved by a rat stable state circuit. The delayed edge is used to start the time measurement circuit, and the next clock edge is used to stop the time measurement circuit. By changing the position of the data edge relative to the clock edge, the time that must be measured by the ramp circuit is minimized. When the known delay is added, producing a precise measurement of the elapsed time between the data edge and the clock edge is subtracted from the measured time.

FIG. 1 shows a basic timing diagram illustrating the difficulty of measuring the elapsed time between the first data edge 12 and the second data edge 13. The present invention will be described with respect to positive edge trigger electronics.

The terms edge and pulse edge are intended to encompass any change in logic state, including rising and falling edges. Positive edge trigger electronics change the state of the floating edge of the clock. Other types of flip-flops and counters are known and equally applicable to the present invention.

Tasks often occur in electronic circuitry, particularly in semiconductor testing equipment that requires the measurement of elapsed time between two pulse edges. As shown in FIG. 1, data edge 12 starts at T1 and data edge 13 starts at T3. Clock 11 is a floating edge of a rectangular cycle with a period of about 1 to 10 nanoseconds. Occurs. Although we know that any clock period is applicable, the stabilization circuit will be described with respect to one nanosecond clock.

As shown in FIG. 1, T1 and T3 occur asynchronously of clock edge 11. That is, even if a match is possible, T1 and T3 do not always coincide with the floating clock edge. The as-is approximation of the time between T1 and T3 can be done by counting clock edge 11 between T1 and T3. This approximation will result in measurement accuracy of ± 1 clock period. In order to obtain a more accurate measurement of elapsed time, it is necessary to measure the time difference between T1 and T2 as well as the next clock edge occurring at T3 and the next floating clock edge at T4. Thus, the problem of precisely measuring the elapsed time between the asynchronous edges at T1 and T3 is summarized as the problem of measuring the elapsed time between the first intervals T1 to T2 and the elapsed time between the second intervals T3 to T4. The time between T2 and T4 counts clock edges so it can be easily measured. The method and apparatus for measuring the first and second intervals are the same and will therefore only be described in relation to the first interval. However, the circuits shown in FIGS. 2 and 4 are duplicated to measure the second gap.

The gap measurement may have been made using a ramp circuit as shown in FIG. The ramp circuit 17 outputs an analog output which is a function of the elapsed time between the start signal received at the start input 18 and the stop signal received at the stop input 19. The analog output can be converted to a digital output that can be added and subtracted from other measurements. From the waveform shown in FIG. 1, one lamp circuit 17 should be provided to measure the elapsed time between T1 and T2, and another lamp circuit should be provided to measure the elapsed time between T3 and T4. do. In order to measure the elapsed time between T1 and T2 shown in FIG. 1, the data line 12 must be coupled directly to the start input 18, while the stop input 19 allows the data to enter the data line 12. It must be coupled to the next clock edge that occurs after it appears. Flip-flop 16 acts to select the next clock edge at T2. When the clock signal appears with the floating edge at the clock input, flip-flop 16 outputs the data at the data (D) input. D-type flip-flop that feeds The D-type flip-flop also has an automatic output Q with an inverse logic value from the Q output.

The data edge 12 is coupled to the D input and the start input 18 of the flip-flop 16, the clock 11 is coupled to the clock input of the flip-flop 16, the Q output of the flip-flop 16 Coupled to a stop input 18. In this arrangement, the data edge 12 starts the ramp circuit 17. When the next clock edge 11 appears at the clock input of flip-flop 16, the Q output goes high. The logic high output shuts off the lamp circuit 17 and the analog output from the lamp circuit 17 represents the elapsed time between T1 and T2 shown in FIG. The propagation delay of flip-flop 16 is added to the elapsed time between T1 and T2, but as long as the propagation delay is constant, the delay can be compensated for.

As illustrated in FIG. 3, when the data inputs of the data line 12 and the clock edge 11 coincide, the Q output of the flip-flop 16 may proceed in an indeterminate or metastable state. . The data edge 12 and the clock edge 11 must not exactly match as any data edge 12 while the metastable window 21 surrounding the clock edge can result in a metastable state. As all flip-flops are set up and breached, a metastable window 21 results as a result of maintaining a time state that results in a metastable output. The metastable output described by the Q waveform of FIG. 3 will vary indefinitely between logic low and logic high and can eventually determine the logic state. However, there is no guarantee that the logical state will be reached within a single clock period, and no guarantee that the last logical state will be correct. Also, because the propagation delay of flip-flop 16 is uncertain to a metastable state, the delay cannot be compensated even when the correct logic state is reached.

4 illustrates the ratification stabilizer circuit of the present invention. The lamp circuit 17 and the flip-flop 16 are similar to the device shown in FIG. The circuit shown on the left side of the flip-flop 16 serves to pre-adjust the data edge 12, so that the metastable state of the flip-flop 16 is impossible.

Start input 18 is coupled to output 34 of multiplexer 28. The signal of the control input 33 of the multiplexer 28 is selected between the inputs 31 and 32 and places the selected input at the output 34. Input 31 is coupled to data edge 12 by a short data path. The short data path has a programmable delay 26 that adequately delays the data edge 12 by 3.25 clock periods. Data input 32 is coupled to what is called a long data path and incorporates an additional delay 27 which is suitably approximately one half clock period. The delay 27 must be at least as long as the metastable window 21 shown in FIG. 3, and the delay 29 described later as appropriate is of the same length. The data input 31 is selected when appearing at the logic low cost control input 33 and the data input 32 is selected when appearing at the logical high cost control input 33. For ease of explanation, any propagation delay through the multiplexer 28 has been summed up in terms of the delay 26 as well as any delay associated with the coupling between transmission lines or components. Since delay 26 is programmable, taking into account additional delays can be easily measured.

As described, when one nanosecond clock period is used, the multiplexer 28 acts to select between a 3.25 nanosecond delay or a 3.75 nanosecond delay. Thus, data input edge 12 will appear at ramp start input 18 and at the D input of flip-flop 16 after a 3.25 nanosecond or 3.75 nanosecond delay after appearing at the D input of flip-flop 22.

As can be seen, a selectable delay is used to locate the data edge 12 so that a metastable state cannot occur at flip-flop 16.

Flip-flops 22-24 act to test the relationship between data edge 12 and clock edge 11 with delay 29 and when a metastable state appears at flip-flop 16, the data edge ( A signal for correcting 12) is output to the multiplexer 28. Clock 11 is coupled to the clock input of flip-flop 16 as well as each flip-flop 22-24. The D input of flip-flop 23 is coupled to data input 12 via delay 29 while the D input of flip-flop 22 is directly coupled to data edge 12.

Although only the delay 29 is needed more than the metastable window 21 for the flip-flop shown in FIG. 3, the delay 29 is conveniently selected in half clock periods. For one nanosecond, the delay 29 would be 0.5 nanoseconds. Typically, 0.5 nanosecond delay includes about 200% guard band around metastable window 21. When a data edge appears at the D input of flip-flop 22, a data edge will appear at the D input of flip-flop 23 after 0.5 nanoseconds. Flip-flop (22) The output is coupled to the Q output of flip-flop 23 and the D input of flip-flop 24. Flip-flop (22) The coupling between the output and the Q output of flip-flop 23 is commonly referred to as a hard wire or the flip-flop 22 An output or flip-flop 23 results in the D input of flip-flop 24 where the Q output is at the highest logic level.

Flip-flop (24) The output is coupled to the reset input 36 of the flip flop 24. When the reset input 36 receives a logic high, the clock input of the flip-flop 24 is disabled and the flip-flop 24 The output goes to the logic block. The flip-flop 24 of the By coupling the output to its reset 36, a positive feedback loop is generated to The metastable signal on the output will turn on at reset 36, thus disabling the clock input of flip-flop 24 and removing the metastable state from the metastable state. Force the output to a logic fault. Once reset input 36 is latched to a logic high state, any edge that occurs at the D input of flip-flop 24 will not affect the output. This means that at most D input of flip-flop 24 will remain at a logic low state for one clock period, so that even if the D input of flip-flop 24 changes, the output of flip-flop 24 is stable. It is important that they be latched to

Above of flip-flop 24 The output is also coupled to the control input of the multiplexer 28.

Once the positive feedback loop is a reminder of the flip-flop 24 When the output is latched to a logic go, the circuit operation provides a logic signal to the set input (not shown) of the flip-flop 24 and needs to be restored. The set input may be required to initialize flip-flop 24 when the stabilization circuit is first turned on. Flip-flop 24 should be shaped with a set input that overrides reset input 36. One such flip-flop is part number MC 10E131 manufactured by Motorola.

The operation of the stabilization circuit shown in FIG. 4 observes the waveforms shown in FIGS. 5 through 8 that illustrate the function of the stabilization circuit with various relationships between the data edge 12 and the clock edge 11. It is easily understood. 5 illustrates a state in which the data edge 12 occurs more than a half clock cycle before the metastable window 21A. The waveform labeled D23 describes the waveform shown at the D input of the flip-flop 23, and is thus delayed by 0.5 clock periods by the delay 29 shown in FIG.

The hash mark 37 on the data edge 12 waveform when the short data path is used describes the time that the data edge 12 will reach the D input of the clock 16, while the long data path will be used. When used, the hash mark 38 describes the time for which the data edge will reach the D input of clock 16. When data edge 12 reaches metastable window 21B, flip-flop 16 may enter metastable state. This is the state to be avoided by the ratification stabilizer.

In the case where the quantum of the edge D23 delayed by the data edge 12 occurs in FIG. 5, which occurs before the metastable window 21A, the flip-flop 22 While the output will be forced to logic low, the Q output of flip-flop 23 will be forced to logic high. Thus, the D input of flip-flop 24 will be logic high and the flip-flop 24 The output will be forced to logic low. In this case a short data path is selected. As shown in FIG. 5, a short data path is needed to be selected to avoid the metastable window 21B.

6 shows waveforms when data edge 12 occurs before metastable window 21A, while delayed edge D23 occurs during metastable window 21A. Flip-flop 22 whose state is logic low While causing an output, the Q output of flip-flop 22 will enter a metastable state.

Thus, the D input of flip-flop 24 appears to be metastable. Since the hash marks 37 and 38 are observed, it is not a problem that either of the passages should be selected so that in this state neither the short data passage nor the long data passage will cause the metastable state of the flip-flop 16. You should know that However, it is important that these or other data paths be selected to avoid time measurement errors.

Referring to FIG. 4, the subsequent clock edge causes the metastable state of the D input of the flip-flop 24 to be flipped. Will be forced to output, as described above, the positive feedback loop Will force the output to a logic fault. Often, this will occur before the next clock edge and thus appear at the logic high control input 33. Even if the above does not occur, the next clock edge is increased by the time since the D output of flip-flop 24 is stabilized at a logic high. Will force the output to logic. If this happens, a short data path has been selected. In both cases, the data path is suitably selected before the data reaches the multiplexer 28 to protect the integrity of the data provided to the flip-flop 16. 7 illustrates the relationship between the data edge 12 and the clock edge 11 that should result in the long data path selected. Here, data edge 12 occurs before metastable window 21A, while delayed edge D23 occurs after the window. Of the flip-flop 22, which is forced to logic low Not only the output but also the Q output of the flip-flop 23. Thus flip-flop 24 The output forces the logic multiplexer 28 to select a long data path. As can be seen in FIG. 7, the long data path 38 should be selected when the relationship exists between the data edge 12 and the clock edge 11. Flip-flop (24) The positive feedback loop formed by coupling the output to reset 36 remains until the flip-flop 24 is reinitialized. It acts to lock the output to a logic block. Without the positive feedback loop shown in FIG. 4, before the data edge 12 reaches the multiplexer 28, the flip-flop 24 may be removed. The output will change to logic low.

FIG. 8 describes a state similar to that shown in FIG. 6, but in this case a metastable state on the D input of flip-flop 24 is caused by flip-flop 22. The stabilization circuit functions similarly to ensure that the multiplexer 28 properly selects the data path before the data path is required, even if the data path is not a problem. Although flip-flops 22 to 24 may enter a metastable state, the propagation delay of the flip-flop is not added to the data edge or clock edge and thus not added to affect the precision of the time measurement circuit. You should know Since only flip-flop 16 is in the data path and it cannot enter metastable state, no measurement error occurs.

It should be noted that the circuit shown in FIG. 4 serves to place the data pulse 12 in the range of 0.25 to 0.75 clock periods from the next clock edge 11. Thus it would never be necessary to measure the time that the lamp circuit 17 is outside of this range. The magnitude of this range is the same as delay 29 and delay 27. In addition to delay 29, flip-flops 22 and 23 serve to detect a window that is as wide as delay 29. Additional windows can be detected if additional flip-flops and delays are used that function similar to flip-flops 22 and 23 and delay 29 and are coupled to the flip-flops and delays. In this way, data edges 12 can be placed in an increasingly smaller range with respect to the next clock edge 11, which will greatly reduce the time the ramp circuit 17 needs to measure.

It will now be appreciated that circuits and methods are provided for measuring elapsed time between two asynchronous edges. Since the two edges test the relationship, a metastable state can be avoided before the edge is used in the time measurement circuit. In this way, greater precision can be achieved by the measuring circuit and it becomes possible to precisely measure an event by only a few picoseconds of continuation. It is contemplated that a precision of ± 5 picoseconds can be achieved by a single measurement using one nanosecond clock period. Eliminating the need for multiple measurements greatly reduces the time needed to measure an event, resulting in a time measurement system that can be effectively used for integrated circuit testing.

Claims (3)

Providing a time measurement circuit coupled to the first and second edges, and for the first edge relative to the second edge to determine whether the edge will cause a metastable state to the time measurement circuit. And delaying the first edge by a set amount if a metastable state appears. A first flip-flop having a data input coupled directly to the data signal; A first data line having a set time delay coupled to the data signal; A second flip-flop having a data input coupled to the first data line (the first flip-flop An output is coupled to the output of the second flip-flop Q; The Q output of the second flip-flop and the first flip-flop A third flip-flop having a data input coupled to an output (having a clock input coupled to the clock signal of said first, second and third flip-flops); A multiplexer having two data inputs, an output, and a control input for selecting between the two data inputs, the control input being the Coupled to the output); A second delay line coupling the data signal to one of the multiplexer data inputs; A third delay line coupling said data signal to a next input of said multiplexer data input, said third delay line being longer than said second delay line; And a time measurement circuit coupled to the multiplexer and to the output of the clock signal. Program the first pulse edge against means for detecting a metastable window coupled to first and second pulse edges and for the second pulse edge controlled by the means for detecting a metastable window. And a ramp circuit having means for possibly delaying and a start input coupled to the means for programmally delaying the first pulse and a stop input coupled to a second pulse edge. .