KR0156155B1 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- KR0156155B1 KR0156155B1 KR1019950023850A KR19950023850A KR0156155B1 KR 0156155 B1 KR0156155 B1 KR 0156155B1 KR 1019950023850 A KR1019950023850 A KR 1019950023850A KR 19950023850 A KR19950023850 A KR 19950023850A KR 0156155 B1 KR0156155 B1 KR 0156155B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- source
- thin film
- polysilicon layer
- insulating film
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- 239000010408 film Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000001301 oxygen Substances 0.000 claims abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- -1 oxygen ions Chemical class 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 230000003213 activating effect Effects 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Abstract
본 발명은 박막트랜지스터 제조방법에 관한 것으로, 동작전류의 온도 의존성을 줄이고 대기 전류를 감소시키기 위한 것이다.The present invention relates to a thin film transistor manufacturing method, and to reduce the temperature dependence of the operating current to reduce the standby current.
본 발명은 반도체기판상에 제1절연막을 형성하는 공정과, 상기 제1절연막상부에 게이트전극을 형성하는 공정, 기판 전면에 게이트절연막과 비정질실리콘층을 차례로 형성하는 공정, 열처리를 공정에 의해 상기 비정질실리콘층을 결정화시켜 폴리실리콘층을 형성하는 공정, 상기 게이트전극 일측단의 상기 폴리실리콘층 소정부위에 산소 이온을 선택적으로 주입하여 오프셋영역을 형성하는 공저, 상기 게이트전극 양단의 상기 폴리실리콘층 부위에 불순물을 이온주입하여 소오스 및 드레인영역을 형성하는 공정, 및 열처리를 행하여 상기 소오스 및 드레인 영역을 활성화시켜 소오스 및 드레인전극을 형성하는 공정으로 이루어지는 박막트랜지스터 제조방법을 제공한다.According to the present invention, a process of forming a first insulating film on a semiconductor substrate, a process of forming a gate electrode on the first insulating film, a process of sequentially forming a gate insulating film and an amorphous silicon layer on the entire surface of the substrate, and heat treatment Crystallizing an amorphous silicon layer to form a polysilicon layer, a process of selectively injecting oxygen ions into a predetermined portion of the polysilicon layer at one end of the gate electrode to form an offset region, and the polysilicon layer at both ends of the gate electrode A method of manufacturing a thin film transistor is provided, which comprises forming a source and a drain region by ion implanting impurities into a site, and forming a source and a drain electrode by activating the source and drain regions by performing heat treatment.
Description
제1도는 종래의 박막트랜지스터 제조방법을 도시한 공정순서도.1 is a process flowchart showing a conventional thin film transistor manufacturing method.
제2도는 본 발명에 의한 박막트랜지스터 제조방법을 도시한 공정순서도.2 is a process flowchart showing a method of manufacturing a thin film transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 기판 11 : 제1절연막10 substrate 11 first insulating film
12A : 게이트전극 13 : 게이트절연막12A: gate electrode 13: gate insulating film
14 : 폴리실리콘층 15 : 제2절연막14 polysilicon layer 15 second insulating film
16 : 오프셋 영역 18 : 드레인영역16: offset region 18: drain region
19 : 소오스영역19: source area
본 발명은 박막트랜지스터 제조방법에 관한 것으로, 특히 동작 전류(on current)의 온도 의존성을 줄이고, 대기 전류(standby current)를 감소시키는데 적당하도록 한 폴리실리콘 박막트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a polysilicon thin film transistor that is suitable for reducing the temperature dependency of an on current and reducing a standby current.
종래의 박막트랜지스터 제조방법을 제1도를 참조하여 설명하면 다음과 같다.A conventional thin film transistor manufacturing method will be described with reference to FIG. 1 as follows.
먼저, 제1a도에 도시된 바와 같이 실리콘기판(1)에 절연층으로서 산화막(2)을 형성하고 이위에 CVD(Chemical Vapor Deposition)방법등에 의하여 비정질실리콘층을 형성한 후, 열처리를 행하여 결정화시켜 폴리실리콘층(3)으로 만든 다음, 그 위에 다시 절연막으로서 산화막(4)을 형성하고 이를 선택적으로 식각하여 상기 폴리실리콘층(3)의 소정부분을 노출시킨다.First, as shown in FIG. 1A, an oxide film 2 is formed on the silicon substrate 1 as an insulating layer, and an amorphous silicon layer is formed thereon by CVD (Chemical Vapor Deposition) method, and then subjected to heat treatment to crystallize. After the polysilicon layer 3 is formed, an oxide film 4 is again formed as an insulating film thereon and selectively etched to expose a predetermined portion of the polysilicon layer 3.
이어서 제1(b)도에 도시된 바와 같이 상기 산화막(4)상의 소정부분에 게이트전극(5)을 형성하고, 상기 노출된 폴리실리콘층(3) 부위에 불순물을 주입하여 소오스 및 드레인영역(6)을 형성한다.Subsequently, as shown in FIG. 1 (b), a gate electrode 5 is formed in a predetermined portion on the oxide film 4, and impurities are injected into the exposed polysilicon layer 3 to supply source and drain regions ( 6) form.
다음에 제1도(c)에 도시된 바와 같이 상기 소오스 및 드레인영역(6) 상부에 각각 소오스전극 및 드레인전극(7)을 형성함으로써 박막트랜지스터 제조를 완료한다.Next, as illustrated in FIG. 1C, a thin film transistor is completed by forming a source electrode and a drain electrode 7 on the source and drain regions 6, respectively.
상기와 같이 제작한 박막트랜지스터는 실리콘 벌크(bulk)를 이용하여 제작한 MOS트랜지스터와는 달리 절연막 또는 그 밖의 기판위에도 형성이 가능하며, 증착하는 폴리실리콘 박막의 두께를 조절함으로써 완전 공핍형 채널(fully depleted channel)로 이용할 수 있다는 큰 장점이 있다.Unlike the MOS transistors fabricated using silicon bulk, the thin film transistors manufactured as described above can be formed on an insulating film or other substrates, and are fully depleted channels (fully) by controlling the thickness of the deposited polysilicon thin film. The advantage is that it can be used as a depleted channel.
반면에 폴리실리콘 박막은 벌크 실리콘에 비해 상당수의 결함(defect)을 가지고 있기 때문에 폴리실리콘 박막으로 만든 트랜지스터는 벌크 실리콘을 이용한 트랜지스터의 성능보다 훨씬 뒤떨어진다는 단점을 가진다.On the other hand, since polysilicon thin films have a large number of defects compared to bulk silicon, transistors made of polysilicon thin films are far behind performance of transistors using bulk silicon.
한편, 상기 종래방법에 의해 제조된 폴리실리콘 박막트랜지스터는 동작시 온전류가 온도의 변화에 따라 크게 변하며, 오프전류(off current)는 드레인 접합부에 있어서의 전계분포에 의한 누설 전류로 인해 증가하여 결과적으로는 동작 전류가 온도에 따라 크게 변하는 문제점과 직접도를 높이기 위해 누설전류를 감소시켜야 한다는 문제점을 갖는다.On the other hand, in the polysilicon thin film transistor manufactured by the conventional method, the on-current changes greatly with the change of temperature during operation, and the off current increases due to the leakage current due to the electric field distribution at the drain junction. As a result, the operating current varies greatly with temperature and the leakage current must be reduced to increase the directivity.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, 동적 전류의 온도 의존성을 줄이고 대기 전류를 감소시킬 수 있는 폴리실리콘 박막트랜지스터의 제조방법을 제공하느데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a polysilicon thin film transistor which can reduce the temperature dependence of dynamic current and reduce the standby current.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터 제조방법은 반도체기판상에 제1절연막을 형성하는 공정과, 상기 제1절연막상부에 게이트전극을 형성하는 공정, 기판 전면에 게이트절연막과 비정질실리콘층을 차례로 형성하는 공정, 열처리를 공정에 의해 상기 비정질실리콘층을 결정화시켜 폴리실리콘층을 형성하는 공정, 상기 게이트전극 일측단의 상기 폴리실리콘층 소정부위에 산소 이온을 선택적으로 주입하여 오프셋영역을 형성하는 공정, 상기 게이트전극 양단의 상기 폴리실리콘층 부위의 불순물을 이온주입하여 소오스 및 드레인 영역을 형성하는 공정, 및 열처리를 행하여 상기 소오스 및 드레인영역을 활성화시켜 소오스 및 드레인전극을 형성하는 공정으로 이루어진다.A thin film transistor manufacturing method of the present invention for achieving the above object is a step of forming a first insulating film on a semiconductor substrate, a step of forming a gate electrode on the first insulating film, a gate insulating film and an amorphous silicon layer on the entire surface of the substrate Forming a polysilicon layer by crystallizing the amorphous silicon layer by a step of forming a heat treatment and a heat treatment step, and selectively forming an offset region by selectively injecting oxygen ions into a predetermined portion of the polysilicon layer at one end of the gate electrode A process of forming a source and a drain region by ion implantation of impurities in the polysilicon layer portions across the gate electrode, and a process of activating the source and drain region to form a source and a drain electrode by performing heat treatment.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 폴리실리콘 박막트랜지스터 제조방법을 공정순서에 따라도시하였다.2 shows a method for manufacturing a polysilicon thin film transistor according to the present invention according to the process sequence.
먼저, 제2도(a)에 도시된 바와 같이 반도체기판(10)상에 제1절연막(11)으로서, 산화막을 형성하고, 이위에 도전층(12)으로서, 도우프드(doped) 폴리시리콘층을 형성한다.First, as shown in FIG. 2A, an oxide film is formed on the semiconductor substrate 10 as the first insulating film 11, and a doped polysilicon layer is formed thereon as the conductive layer 12. As shown in FIG. To form.
이어서 제2도(b)에 도시된 바와 같이 상기 도전층(12)을 소정패턴으로 패터닝하여 게이트전극(12A)을 형성한다.Subsequently, as illustrated in FIG. 2B, the conductive layer 12 is patterned to form a gate electrode 12A.
다음에 제2도(c)에 도시된 바와 같이 기판 전면에 게이트절연막(13)을 형성하고, 이위에 500 내지 550℃, 예컨대 530℃정도의 온도에서 SiH4가스를 이용하여 비정질실리콘층을 형성한 후, 이를 550℃ 내지 650℃, 예컨대 600℃의 온도로 N2분위기에서 10시간 내지 13시간, 예컨대 12시간 정도 열처리를 행하여 결정화시켜 폴리실리콘층(14)을 만든다.Next, as shown in FIG. 2C, a gate insulating film 13 is formed on the entire surface of the substrate, and an amorphous silicon layer is formed thereon using SiH 4 gas at a temperature of about 500 to 550 ° C., for example, about 530 ° C. After that, the polysilicon layer 14 is crystallized by heat treatment at a temperature of 550 ° C. to 650 ° C., such as 600 ° C. for 10 hours to 13 hours, for example, 12 hours, in an N 2 atmosphere.
이어서 제2도(d)에 도시된 바와 같이 상기 폴리실리콘층(14)상에 제2절연막(15)을 형성한 후, 이를 선택적으로 식각하여 게이트전극(12A) 일측의 상기 폴리실리콘층(14)의 소정부분(후에 오프셋(off set)영역으로 되는 부분)을 노출시킨 다음, 이 노출된 폴리실리콘층 부위에 산소 이온을 주입하여 오프셋영역(16)을 형성한다. 이때, 산소 이온의 주입량은 폴리실리콘층 속의 산소 농도가 1×1020㎝-3내외가 되도록 한다.Subsequently, as shown in FIG. 2D, a second insulating layer 15 is formed on the polysilicon layer 14, and then selectively etched to form the polysilicon layer 14 on one side of the gate electrode 12A. ), A predetermined portion (which will later be an offset region) is exposed, and then oxygen ions are implanted into the exposed polysilicon layer to form an offset region 16. At this time, the injection amount of oxygen ions is such that the oxygen concentration in the polysilicon layer is about 1 × 10 20 cm -3 .
다음에 제2도 (e)에 도시된 바와 같이 상기 제2절연막(15)을 소정패턴으로 패터닝하여 소오스 및 드레인영역을 정의한다. 즉, 소오스 및 드레인영역이 될 폴리실리콘층(14)부분의 제2절연막(15)을 선택적으로 제거한 후, 불순물을 이온주입하여 상기 폴리실리콘층(14)에 소오스영역(19) 및 드레인 영역(18)을 형성한 다음, 이 소오스 및 드레인영역의 전기적 활성화 및 이온주입에 의해 생긴 결함 회복을 위해 약 950℃의 온도에서 8분 내지 12분, 예컨대 10분 정도 열처리를 행함으로써 소오스영역(19) 및 드레인영역(18)을 형성한다.Next, as shown in FIG. 2E, the second insulating layer 15 is patterned to define a source and drain region. That is, after selectively removing the second insulating film 15 in the portion of the polysilicon layer 14 to be the source and drain regions, impurities are implanted into the polysilicon layer 14 so that the source region 19 and the drain region ( 18), and then heat treatment for 8 to 12 minutes, for example, 10 minutes at a temperature of about 950 ° C. to recover defects caused by electrical activation and ion implantation of the source and drain regions. And a drain region 18.
이와 같이 제조되는 본 발명의 박막트랜지스터의 동작에 있어서는 산소이온을 주입하여 형성한 오프셋 영역이 중요한 역할을 하게 된다.In the operation of the thin film transistor of the present invention manufactured as described above, an offset region formed by injecting oxygen ions plays an important role.
먼저, 박막트랜지스터가 온(on)되었을 경우에는 다음과 같이 동작한다.First, when the thin film transistor is turned on, the following operation is performed.
산소를 포함한 폴리실리콘은 온도에 변화에 대한 전류의 변화가 작은 특성을 갖는다. 그 이유는 폴리실리콘을 흐르는 전류의 기구(mechanism)에 따르기 때문이다. 즉, 산소를 포함하지 않는 폴리실리콘의 경우, 폴리실리콘의 전도기구는 열전자 방출(thermionic emission)기구에 의하여 지배되며, 온도의 변화에 대해 상당히 민감한 특성을 보인다.Polysilicon containing oxygen is characterized by a small change in current with respect to a change in temperature. This is because it depends on the mechanism of the current flowing through the polysilicon. That is, in the case of polysilicon that does not contain oxygen, the conduction mechanism of the polysilicon is governed by a thermoionic emission mechanism, and exhibits a very sensitive characteristic against temperature changes.
한편, 산소를 포함하는 폴리실리콘의 경우에는 열전자 방출보다는 호핑(hopping)기구에 의해 지배된다. 이 경우에 전류는 온도에 대한 의존성이 작아지며, 산소량을 변화시킴으로써 활성화 에너지(activation energy)를 제어할수 있다.On the other hand, polysilicon containing oxygen is dominated by a hopping mechanism rather than hot electron emission. In this case, the current is less dependent on the temperature, and the activation energy can be controlled by changing the amount of oxygen.
따라서 본 발명의 박막트랜지스터의 경우, 종래 기술에 의한 박막트랜지스터 보다 온도 의존성을 줄일 수 있다.Therefore, in the case of the thin film transistor of the present invention, it is possible to reduce the temperature dependency than the thin film transistor according to the prior art.
한편, 박막트랜지스터의 오프(off)시에는 다음과 같이 동작한다.On the other hand, when the thin film transistor is off (off) it operates as follows.
오프시 박막트랜지스터를 흐르는 전류는 폴리실리콘 자체의 저항과 드레인 접합부측의 채널영역에 형성된 pn접합의 역방향 전류에 지배된다. 따라서 폴리실리콘에 산소를 주입함으로써 폴리실리콘 박막 자체의 저항을 높여 주어 오프시의 전류를 줄일 수 있다. 또한, 드레인 접합부에 오프셋영역을 둠으로써 역방향 전계를 완화하여 열전계 방출(thermionic field emission) 전류를 감소시켜 누설전류를 줄일 수 있다. 특히, 산소를 주입하면 폴리실리콘의 밴드갭(bandgap)이 커지게 되는데, 이로 인해 박막트랜지스터의 브레이크다운 전압이 증가하게 되는 장점도 있다.The current flowing through the thin film transistor during off is governed by the resistance of the polysilicon itself and the reverse current of the pn junction formed in the channel region on the drain junction side. Therefore, by injecting oxygen into the polysilicon, the resistance of the polysilicon thin film itself is increased to reduce the current at the time of off. In addition, by providing an offset region at the drain junction, the reverse electric field may be relaxed to reduce the thermal field emission current to reduce the leakage current. In particular, when oxygen is injected, the bandgap of polysilicon is increased, which may increase the breakdown voltage of the thin film transistor.
이상 상술한 바와 같이 본 발명에 의하면, 소자 구조를 크게 변화시키지 않으면서도 산소 이온주입에 의해 드레인영역에 오프셋영역을 형성함으로써 온전류의 온도의존성을 감소시키고, 오프전류를 감소시키며, 브레이트다운 전압을 증가시킬 수 있다. 따라서 고집적 SRAM(Static Random Access Memory)의 부하 저항에 유용하게 이용할 수 있다.As described above, according to the present invention, by forming the offset region in the drain region by oxygen ion implantation without greatly changing the device structure, the temperature dependency of the on-current is reduced, the off-current is reduced, and the breakdown voltage is reduced. Can be increased. Therefore, it can be usefully used for load resistance of highly integrated static random access memory (SRAM).
Claims (5)
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