KR0155756B1 - Digital noise depreciation method and circuit of magnetic recording/reproducing apparatus - Google Patents

Abstract

In the image recording and reproducing apparatus, the digital noise reduction circuit and method according to the present invention can reduce the overall hardware as well as reduce the overall hardware by sharing the feedback noise reduction unit (YNR) and the line correlation noise reduction unit (Y-com). By employing the above, it is possible to solve the problems of the conventional noise canceler, such as aliasing, gain reduction, crushing of edges, etc., and employing the TSC algorithm has the effect of faithfully restoring the small signal near the large signal.

Description

Digital Noise Reduction Method and Circuit in Magnetic Recording and Reproducing Equipment

1 is a block diagram showing a line-correlated noise reducer (Y-com) among the components of a conventional noise reduction circuit.

2 is a block diagram showing a feedback noise reducer (YNR) among the components of a conventional noise reduction circuit.

3 is a block diagram according to an embodiment of the digital noise reduction circuit according to the present invention in the video recording and reproducing apparatus.

* Explanation of symbols for main parts of the drawings

100, 110: first and second switching means 120: adaptive K control unit

130, 150: first and second TSC algorithm unit 140: HI algorithm unit

160: drop out compensation means 21, 27: the first and second delay

23, 25, 39, 51, 53: multiplexer 29: correlation detector

31, 33: Multiplier 35, 47: Adder

37, 49: TSC detector 41: high pass filter

43: subtractor 45: core ring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital noise reduction method and circuit in a video recording and reproducing apparatus. In particular, a feedback noise reduction unit (YNR) and a line-correlation noise reduction unit (Y-com) using TSC and HI algorithms are used. The present invention relates to a digital noise reduction method and circuit which reduces hardware size and improves noise reduction performance by sharing.

Generally, video signals are highly correlated between fields or frames, but noise signals are not. Therefore, circuits have been proposed to reduce noise signals incorporated into video signals by using such a property. The digital noise reduction circuit is a device for separating a video signal and a noise signal by digital signal processing (DSP) and reducing a noise signal included in the video signal by using the separated noise signal. Such noise reduction circuits using digital technology are described in broadcasting technology (1991, 2 P141 to 143), digital signal processing of images (prepared by Japan Daily Newspaper P115-118).

In addition, the noise reduction circuit is different from the noise canseller in that a memory is used. That is, the noise reduction circuit uses a filter, and the noise reduction circuit uses a memory such as a line memory, a field memory, a frame memory, etc. according to the manufacturer.

In addition, in order to increase the noise reduction effect or reduce the side effects in the noise reduction circuit, a feedback noise reducer (YNR), a line correlation noise reducer (YNR), and a line correlation noise reducer (Y-com) are commonly used. Configure.

FIG. 1 is a block diagram showing a line shape and a noise reducer (Y-com) among components of a conventional noise reduction circuit.

Referring to FIG. 1, the differential amplifier 3 obtains and amplifies a difference between the reproduction luminance signal of which the noise signal is piggybacked and the reproduction luminance signal delayed by 1H by the 1H delayer 1, and outputs the difference to the limiter 5. . The signal output from the differential amplifier 3 is a noise signal without line correlation. However, since this noise signal also contains a weak correlation signal, only the weak correlation signal is adjusted by the limiter 5 and then adjusted to a predetermined level by the level adjuster 7 so that the lyrics 9 and the original reproduction luminance signal are different from each other. By combining, a signal with reduced noise is output.

2 is a block diagram showing a feedback noise reducer (YNR) among the components of a conventional noise reduction circuit.

Referring to FIG. 2, the first adder 11 adds the reproduction luminance signal and the signal fed back from the output terminal to delay the 1H delay in the 1H delayer 13, and the second adder 15 A signal with reduced noise is output by adding the signal before 1H output from the 1H delay unit 13.

As described above, the line-correlation noise reducer (Y-com) is designed to have no feedback effect to remove crosstalk, and the feedback-type noise reducer (YNR) increases the noise reduction effect by using the feedback effect. It is aimed at letting.

However, the signal output by reducing noise through the conventional noise reduction circuit has a good signal-to-noise (S / N) ratio, but a part of the signal representing the detail of the image included in the high frequency microsignal. Also, as the noise signal is limited, the gain of the high frequency signal is reduced, so that the minute portion of the screen is somewhat distorted.

In addition, since the reproduction luminance signal is limited together when limiting the noise signal, the rising and falling edges of the reproduction luminance signal corresponding to the contour portion of the image are smoothed, so that the outline of the image is not clear. It also generates aliases when implementing digital circuits.

Accordingly, an object of the present invention is to reduce the overall size of the hardware and improve the noise reduction performance by sharing the circuit components of the feedback noise reduction unit and the line-correlated noise reduction unit in the image recording and reproducing apparatus to solve the above problems. It is to provide a digital noise reduction method.

It is another object of the present invention to provide a circuit most suitable for realizing the digital noise reduction method.

In order to achieve the above object, the digital noise reduction method according to the present invention includes a first switching step for switching an input signal applied to reduce noise and a first predetermined time delayed signal according to a YNR / Y-com operation selection signal. ; A second switching step for switching the current input signal and the feedback signal output in the first switching step according to the YNR / Y-com operation selection signal; TSC signal generation for generating a TSC signal when the difference between the absolute value of the current input signal and the absolute value of the input signal before 1H is obtained and the difference is equal to or greater than a predetermined set value which is a reference for non-line-correlated microsignal erasure prevention. step; The correlation between the current input signal and the 1H previous signal output in the second switching step is detected to calculate a K factor value, and when the TSC signal is generated, multiply the (1-K) factor value by the current input signal. A first noise reduction step of outputting a signal obtained by multiplying a K factor value by the 1H previous signal and selectively outputting the current input signal when the TSC signal is not generated; The high pass filtered signal is subtracted from the signal output from the first noise reduction step to generate a signal with agglomerated edges, and the high pass filtered signal is subjected to a predetermined core. A second noise reduction step of reducing noise again and outputting the signal as the feedback signal by selectively outputting a signal added to the signal with the edges crushed after the level and selectively outputting the signal output in the first noise reduction step; And compensating for the dropout by outputting a signal obtained by delaying the signal output in the second switching step by a second predetermined time instead of the signal output in the second noise reduction step when a signal for dropout compensation processing is applied by the user. It characterized in that it comprises a dropout compensation step for.

In order to achieve the above object, the digital noise reduction circuit according to the present invention is a video recording / reproducing apparatus, in which an input signal applied to reduce noise in accordance with a YNR / Y-com operation selection signal and an input signal delayed by a first predetermined time. First switching means for switching the; Second switching means for switching the current input signal and the feedback signal outputted from the first switching means in accordance with the YNR / Y-com operation selection signal; TSC signal generation for generating a TSC signal when the difference between the absolute value of the current input signal and the absolute value of the input signal before 1H is obtained and the difference is equal to or greater than a predetermined set value which is a reference for non-line-correlated microsignal erasure prevention. Way; Detecting the correlation between the current input signal and the 1H previous signal output from the second switching means, a K factor value is calculated, and the (1-K) factor value calculated according to the presence or absence of the TSC signal is output to the current input signal. First noise reduction means for reducing noise by multiplying and multiplying a K factor value by the 1H previous signal and selectively outputting the current input signal; A high pass filtered signal is subtracted from the signal output from the first noise reduction means to generate a lumped edge signal, and the high pass filtered signal is a predetermined core. Second noise reduction means for reducing noise again and outputting the signal as the feedback signal by selectively outputting the signal added to the crushed signal after leveling and the signal output from the first noise reduction means; And compensating the dropout by outputting a signal obtained by delaying a signal output from the second switching means by a second predetermined time instead of a signal output from the second noise reduction means when a signal for dropout compensation processing is applied by a user. It characterized in that it comprises a dropout compensation means for.

Next, the configuration and operation of a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. 3 is a block diagram according to an embodiment of a digital noise reduction circuit according to the present invention.

The configuration of the block diagram shown in FIG. 3 is a first switching means 100 for switching an input signal applied to reduce noise according to a YNR / Y-com operation selection signal and an input signal delayed by a first predetermined time. ), Second switching means 110 for switching the current input signal and the feedback signal output from the first switching means 100 according to the YNR / Y-com operation selection signal, and the current input signal and the second switching means. Detects the correlation of the 1H previous signal output from 110 to calculate the K factor value, multiplies the (1-K) factor value calculated according to the presence or absence of the TSC signal by the current input signal, and transfers the K factor value to 1H before. A signal subjected to high pass filtering with respect to a signal output from the first noise reduction means 120 and the first noise reduction means 120 for reducing noise by selectively outputting a signal multiplied by the signal and a current input signal. Is subtracted from the signal output from the first noise reduction means 120 To generate a signal having a clumped edge, and to perform a high-pass filtered signal for a predetermined core level, and then add a signal added to the crumpled signal and a signal output from the first noise reduction means (120, 130). By selectively outputting the second noise reduction means (140, 150) for reducing the noise again to output as a feedback signal, and the second noise reduction means (140, 150) when a signal for dropout compensation processing is applied by the user The drop out compensation means 160 compensates the drop out by outputting a signal delayed by a second predetermined time instead of the signal output from the second switching means 110.

Among the components of the first noise reduction means 120 and 130, the correlation detector 29 and the first TSC detector 37 correspond to TSC signal generation means for generating a TSC signal.

An operation according to the above configuration will be described.

In the first multiplexer 23, which is the first switching means 100, the YNR / Y-com is applied to the selection terminal by inputting the reproduction luminance signal and the signal in which the reproduction luminance signal is delayed by the first delay unit 21 for a predetermined time. Selectively switch according to the signal and output.

In the second multiplexer 25, which is the second switching means 110, the output signal of the first multiplexer 23 and the output signal of the fourth multiplexer 51, which will be described later, are input as YNR / Y-com applied to the selection terminal. Selectively switch according to the signal and output.

That is, Y-com is activated by default on the selection terminals of the first multiplexer 23 and the second multiplexer 25 so that the first multiplexer 23 generates a reproduction luminance signal, and the second multiplexer 25 is made of the second multiplexer 25. The output signal of the multiplexer 23 is switched and output.

On the other hand, when the YNR is operated by the user's selection, the first multiplexer 23 switches the output luminance signal delayed by a predetermined time, and the second multiplexer 25 switches the output signal of the fourth multiplexer 51.

In this case, the reason why the first delay unit 21 is used when the YNR is operated is that the signal is delayed by the system delay time to the output terminal of the first multiplexer 23 because the feedback structure is used in the YNR. Therefore, in order to synchronize the output terminal of the first multiplexer 23, the signal is demonstrated to the first multiplexer 23 by the system delay time during YNR operation.

In the adaptive K control unit 120, the correlation detector 29 includes the current signal input P output from the first multiplexer 23 and the second multiplexer 25 delayed by 1H by the second delay unit 27. The correlation is detected for output M to determine the K factor value. That is, if the absolute value of the current signal input P and the signal input M before 1H is input, if the current signal input P is larger than the signal input M before 1H, the value of (MP) is K. If the current signal input P is less than or equal to the signal input M before 1H, the PM value is determined as the K factor value.

The (1-K) multiplier 31 corresponds to the K factor value determined by the correlation detector 29 and multiplies the output signal of the first multiplexer 23 to apply it to the first adder 35.

The K multiplier 33 corresponds to the K factor value determined by the correlation detector 29 and multiplies the output signal of the second multiplexer 25 by the signal delayed by 1H in the second delay unit 27 to add the first adder 35. Is applied.

The first adder 35 adds the output signal of the (1-K) multiplier 31 and the output signal of the K multiplier 33 and applies it as an input signal of the third multiplexer 39.

In the first TSC algorithm unit 130, the first TSC detector 37 is employed to prevent the non-line-correlated microsignal deletion in the third multiplexer 39. That is, when the correlation detector 29 obtains the difference between the absolute value of the current signal input P and the absolute value of the signal input M before 1H, the difference is a set value which is a reference for preventing non-line-correlated microsignals. If abnormal, the TSC signal is generated and applied as the selection signal of the third multiplexer 39. That is, the size of the non-line correlated small signal that is noise compensated is changed according to the magnitude of the above set value.

The third multiplexer 39 inputs the output signal of the first multiplexer 23 and the output signal of the first adder 35 to output the TSC signal from the first TSC detector 37. The output signal is switched, and if the TSC signal is not output, the output signal of the first multiplexer 23 is switched and output.

In the HI algorithm unit 140, the high pass filter 41 high-pass filters the output signal of the third multiplexer 39 to a subtractor 43 for a predetermined band.

The subtractor 43 subtracts the output signal of the high pass filter 41 from the output signal of the third multiplexer 39 and applies it to the second adder 47.

The core ringer 45 applies the output signal of the high pass filter 41 to the second adder 47 by ringing the core signal for a predetermined core level.

The second adder 47 adds the output signal of the subtractor 43 and the output signal of the core ringer 45 and applies it to the input of the fourth multiplexer 51.

In the second TSC algorithm unit 150, the second TSC detector 37 is employed to prevent the deletion of the small high frequency signal in the fourth multiplexer 51. That is, the TSC signal is output when there is a small high frequency signal component in the core level during the core ring process in the core ring machine 45, and the TSC signal is not output when the micro high frequency signal component is deleted in the core level.

The fourth multiplexer 41 inputs the output signal of the third multiplexer 39 and the output signal of the second adder 47 and outputs a TSC signal from the second TSC detector 49. The output signal is switched, and if the TSC signal is not output, the output signal of the third multiplexer 39 is switched and output.

The fifth multiplexer 53, which is the dropout compensation means 160, is used for dropout compensation processing when the Doc signal is applied to the selection terminal. The stored value of (27) is held, and the stored value is continuously read to select the output signal of the second delay unit 27. If the Doc signal is not applied, the fifth multiplexer 53 selects the output signal of the fourth multiplexer 51.

Next, the time plus ^{2 and} minus ² sample correction detectors 37 and 49 will be described.

The TSC detectors 37 and 49 output the TSC signal during the correlation detection in the correlation detector 29 or during the coreing process in the core ringer 45. First, the principle of the core ring is as follows.

1) When a small high frequency signal is input to the core ring machine 45, the small high frequency signal within the core level is removed and output.

2) When the small high frequency noise is input to the core ring machine 45, the small high frequency noise within the core level is removed and output.

That is, a large signal may be determined while performing a core ring by using a comparator (not shown) and a multiplexer (not shown) constituting the core ringer 45. When the micro signal near the zero level of the large signal is cored, the TSC signal is output while controlling the multiplexer after comparing with the core level at the contracted value. On the other hand, the high frequency noise is cored and does not output the TSC signal. Each TSC signal is ringed by an oar gate (not shown) to generate a TSC synthesized signal and output the selected signal of the third and fourth multiplexers 39 and 51.

The H.I algorithm unit 140 will be described in more detail as follows.

An input signal in which noise is mixed is applied to the high pass filter 41, and the subtractor 43 subtracts the output of the high pass filter 41 from the input signal to output an input signal in which noise is removed but all edges are crushed. Therefore, the core ringer 45 cores the output signal of the high pass filter 41 to remove the minute noise but adds the signal having the small signal component to the output signal of the subtractor 43 from the second adder 47. A signal from which noise is removed from the input signal is output. At this time, the second TSC detector 49 generates a TSC signal only when the micro noise is removed from the core ringer 45 and outputs the TSC signal to the fourth multiplexer 51. When the TSC signal is output, the fourth multiplexer 51 switches the output signal of the second adder 47 and outputs the converted signal.

As described above, in the video recording and reproducing apparatus, the digital noise reduction method and circuit according to the present invention can reduce the overall hardware by sharing the feedback-type noise reducer (YNR) and the line-correlated noise reducer (Y-com). It works.

In addition, according to the user's selection, the dropout compensation processor may be shared with the noise reduction circuit.

In addition, by employing the HI algorithm, there is an effect that can solve the problems of the conventional noise reduction, the alias, the gain reduction, the edge crushing.

In addition, by employing the TSC algorithm, it is possible to faithfully restore the small signal near the large signal.

Claims (6)

A first switching step of switching an input signal applied to reduce noise and an input signal delayed by a first predetermined time according to the YNR / Y-com operation selection signal; A second switching step for switching the current input signal and the feedback signal output in the first switching step according to the YNR / Y-com operation selection signal; TSC signal generation for generating a TSC signal when the difference between the absolute value of the current input signal and the absolute value of the input signal before 1H is obtained and the difference is equal to or greater than a predetermined set value which is a reference for non-line-correlated microsignal erasure prevention. step; The correlation between the current input signal and the 1H previous signal output in the second switching step is detected to calculate a K factor value, and when the TSC signal is generated, multiply the (1-K) factor value by the current input signal. A first noise reduction step of outputting a signal obtained by multiplying a K factor value by the 1H previous signal and selectively outputting the current input signal when the TSC signal is not generated; The high pass filtered signal is subtracted from the signal output from the first noise reduction step to generate a signal with agglomerated edges, and the high pass filtered signal is subjected to a predetermined core. A second noise reduction step of reducing noise again and outputting the signal as the feedback signal by selectively outputting a signal added to the signal with the edges crushed after the level and selectively outputting the signal output in the first noise reduction step; And compensating for the dropout by outputting a signal obtained by delaying the signal output in the second switching step by a second predetermined time instead of the signal output in the second noise reduction step when a signal for dropout compensation processing is applied by the user. Digital noise reduction method comprising a drop out compensation step for. An image recording and reproducing apparatus, comprising: first switching means for switching an input signal applied to reduce noise and an input signal delayed by a first predetermined time in accordance with a YNR / Y-com operation selection signal; Second switching means for switching the current input signal and the feedback signal outputted from the first switching means in accordance with the YNR / Y-com operation selection signal; TSC signal generation for generating a TSC signal when the difference between the absolute value of the current input signal and the absolute value of the input signal before 1H is obtained and the difference is equal to or greater than a predetermined set value which is a reference for non-line-correlated microsignal erasure prevention. Way; Detecting the correlation between the current input signal and the 1H previous signal output from the second switching means, a K factor value is calculated, and the (1-K) factor value calculated according to the presence or absence of the TSC signal is output to the current input signal. First noise reduction means for reducing noise by multiplying and multiplying a K factor value by the 1H previous signal and selectively outputting the current input signal; A high pass filtered signal is subtracted from the signal output from the first noise reduction means to generate a lumped edge signal, and the high pass filtered signal is a predetermined core. Second noise reduction means for reducing noise again and outputting the signal as the feedback signal by selectively outputting the signal added to the crushed signal after leveling and the signal output from the first noise reduction means; And compensating for the dropout by outputting a signal obtained by delaying a signal output from the first switching means by a second predetermined time instead of a signal output from the second noise reduction means when a signal for dropout compensation processing is applied by a user. Digital noise reduction circuit comprising a drop out compensation means for. 3. The digital switching device according to claim 2, wherein the first switching means selects the input signal when the Y-com operation is selected, and selects the input signal delayed by the first predetermined time when the YNR operation is selected. Circuit. 3. The digital switching circuit according to claim 2, wherein in the second switching means, when the Y-com operation is selected, the signal output from the first switching means is selected, and when the YNR operation is selected, the feedback signal is selected. . 3. The correlation detection method according to claim 2, wherein the correlation detection is performed by inputting an absolute value of a current signal input P output from the first switching means and a signal input M before 1H output from the second switching means. If the input P is larger than the signal input M before 1H, the MP value is determined as the K factor value.If the current signal input P is less than or equal to the signal input M before 1H, A digital noise reduction circuit characterized by determining a value of (PM) as a K factor value. The digital noise reduction circuit according to claim 2, wherein the TSC signal of the second noise reduction means is generated only when a high frequency microsignal exists within the core level in the core ring.