JPH0720207B2 - Adaptive noise suppressor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise suppressing device for suppressing noise of a video signal in a television receiver.

[Conventional technology]

FIG. 11 is a block circuit diagram of a conventional noise suppressor,
(1) is an input terminal to which the digital video signal (101) is input, (2) is a frame memory for delaying the input video signal by one frame, (3) and (5) are subtraction circuits,
(4) is a fixed memory circuit that converts the input signal with a non-linear characteristic and outputs the converted signal, and (12) is an output terminal that outputs a video signal in which noise is suppressed by the noise suppression device.

Next, the operation will be described. The video signal (101) input from the input terminal (1) is input to the subtraction circuits (3) and (5). The subtraction circuit (3) also receives a video signal (102) in which noise described later is suppressed and delayed by one frame, and a difference signal (103) obtained by subtracting the video signal (102) from the input video signal (101). Is output. The fixed storage circuit (4) stores the input difference signal (103), for example, in the 12th
A noise suppression signal (10
4) is output. The subtraction circuit (5) receives the input video signal (10
The noise suppression signal (104) is subtracted from 1), and the noise-suppressed video signal (105) is output to the output terminal (12). The frame memory (2) outputs a video signal (102) obtained by delaying the noise-suppressed output video signal (105) by one frame to the negative terminal of the subtractor (3). As a result, noise of a low level mixed in the input video signal (101) is suppressed.

[Problems to be Solved by the Invention]

Since the conventional noise suppressor is configured as described above, when an image is scene-changed, the edge of the object image with a small level difference between frames appears on the screen as an afterimage. .

The present invention has been made to solve the above problems, and provides an adaptive noise suppressor capable of reducing the appearance of an edge of an image of an object having a small level difference between frames as an afterimage on the screen. The purpose is to

[Means for Solving the Problems]

An adaptive noise suppressor according to the present invention comprises means for creating a first video signal that has been subjected to noise suppression by utilizing frame correlation between an input video signal and an output video signal, and a horizontal and vertical direction of the input signal. The second method that uses correlation to suppress noise according to the level of horizontal correlation and vertical correlation
Means for producing the video signal, means for detecting an edge of the output video signal, and means for producing an edge detection signal which is further expanded in the horizontal and vertical directions, and a second means for outputting the edge detection signal. And a selection means for outputting the video signal and outputting the first video signal when the video signal is not output.

[Action]

In the adaptive noise suppressor according to the present invention, the edge detection signal generating means detects the edge of the video signal which causes a level difference in the horizontal direction and the vertical direction, and outputs the edge detection signal. At this time, the output selection means outputs the second video signal.

Therefore, the periphery of the edge of the object image that causes a small level difference between frames is not the first video signal whose noise is suppressed by using the frame correlation, but the first video signal whose noise is suppressed by using the horizontal and vertical correlations. Since the second video signal is selected, it is possible to reduce the appearance of edges of the object image on the screen.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, the same components as those of FIG. 11 are designated by the same reference numerals and the description thereof will be omitted. (6) is a delay circuit for adjusting the delay amount of the output video signal of the subtraction circuit (5), (7) is the output video signal (206) of the delay circuit (6) and the output video signal of the delay circuit (11) ( 210) switch circuit,
(8) An edge detection circuit for detecting the horizontal and vertical edges of the output video signal (202) of the frame memory (2), and (9) an edge detection signal (208) output from the edge detection circuit (8). Edge detection signal expansion circuit that expands the horizontal and vertical directions, (10) is the input signal (101)
Horizontal / vertical noise suppression circuit that detects the horizontal and vertical correlations of the, and suppresses noise by using the filter in the highly correlated direction. (11) is output from the horizontal / vertical noise suppression circuit (10) It is a delay circuit for adjusting the delay amount of the video signal (210) to be reproduced to the delay amount of the output video signal (206) of the delay circuit (6).

Next, the operation will be described. The video signal (101) input from the input terminal (1) is input to the subtraction circuit (3), the subtraction circuit (5) and the horizontal / vertical noise suppression circuit. In the subtraction circuit (3), the output video signal (211) is delayed by one frame from the frame memory (2) (20
2) is also entered. The subtraction circuit (3) receives the input video signal (10
The video signal (202) input from the frame memory (2) is subtracted from 1) and the difference signal (203) is output. The fixed storage circuit (4) receives the differential signal (203) as input, converts the differential signal with the input / output characteristics shown in FIG. 12 as in the conventional example, and outputs the noise suppression signal (204). Subtraction circuit (5)
Subtracts the noise suppression signal (204) output from the fixed storage circuit (4) from the input video signal (101) and outputs the noise-suppressed video signal (205). Delay circuit (6)
Outputs the video signal (206), which is time-compensated by delaying the video signal (205) input from the subtraction circuit (5) by a predetermined amount, to the switch circuit (7).

On the other hand, the edge detection circuit (8) detects horizontal and vertical edges from the video signal (202) input from the frame memory (2). FIG. 2 is a block circuit diagram showing an example of the configuration of the edge detecting circuit (8). First, the edge detecting operation in the vertical direction of this circuit will be described.

Video signal (202) input from frame memory (2)
(FIG. 5A) is input to the 1-line delay circuit (801) and the addition circuit (803). The 1-line delay circuit (801) delays the video signal (202) by 1 line and outputs the video signal (301) shown in FIG. 5 (b). The 1-line delay circuit (802) delays the video signal (301) input from the 1-line delay circuit (801) by 1 line, and the delay circuit is shown in FIG.
The video signal (302) shown in is output. Adder circuit (803)
Adds the video signal (202) and the video signal (302),
The video signal (303) shown in FIG. 3D is output. The 1/2 circuit (804) multiplies the video signal (303) by 1/2 and outputs the video signal (304) shown in FIG. 5 (e). The subtraction circuit (805)
Video signal (30) input from 1-line delay circuit (801)
The video signal (304) is subtracted from 1) and the vertical edge signal (305) shown in FIG. 5 (f) is output. The 1-sample delay circuit (806) is a delay circuit for aligning with a horizontal edge signal (311) described later, and delays the edge signal (305) input from the subtraction circuit (805) for 1 sample period. The edge signal (306) is output.

Next, the edge detection operation in the horizontal direction will be described. The 1-sample delay circuit (807) delays the video signal (301) input from the 1-line delay circuit (801) for 1 sample period and outputs a video signal (307) shown in FIG. 6 (b). The 1-sample delay circuit (808) delays the video signal (307) input from the 1-sample delay circuit (807) for 1 sample period, and outputs the video signal (308) shown in FIG. 6 (c).
The addition circuit (809) includes a video signal (301) input from the 1-line delay circuit (801) and a 1-sample delay circuit (808).
The input video signal (308) is added and the video signal (309) shown in FIG. 6 (d) is output. The 1/2 circuit (810) multiplies the video signal (309) input from the adder circuit (809) by a factor of two to generate the video signal (31) shown in FIG.
0) is output. The subtraction circuit (811) subtracts the video signal (310) input from the 1/2 time circuit (810) from the video signal (307) input from the 1-sample delay circuit (807),
A horizontal edge signal (311) shown in FIG. 6 (f) is output. The fixed memory circuit (812) receives an edge signal (306) such as that shown in FIG. 7 (a) from the one-sample delay circuit (806) and, for example, FIG. 7 (a) inputted from the subtraction circuit (811). Regarding the edge signal (311) as shown in FIG. 7C, the presence or absence of the edge detection signal in the horizontal direction and the vertical direction is determined by the threshold values shown in FIGS. 7A and 7C, and FIG. Edge detection signals in the horizontal direction and the vertical direction as shown in (d) are taken out, and the logical sum of these signals is taken and output as an edge detection signal (207).

Next, the edge detection signal expansion circuit (9) expands the edge detection signal (207) input from the edge detection circuit (8) in the horizontal and vertical directions, and the edge detection signal (208) is input to the switch circuit (2). Output as. FIG. 3 is a block circuit diagram showing an example of the configuration of the edge detection signal expansion circuit (9), and the operation of this circuit will be described below.

The edge detection signal (207) input from the edge detection circuit (8) is supplied to the 1-line delay circuit (901) and the OR circuit (90).
Entered in 3). The 1-line delay circuit (901) delays the edge detection signal (207) by 1 line, and detects the edge detection signal (4).
01) is output. The 1-line delay circuit (902) receives the edge detection signal (40
An edge detection signal (402) obtained by further delaying 1) by one line is output. An OR circuit (903) calculates the logical sum of the input edge detection signal (207), edge detection signal (401) and edge detection signal (402) and outputs the edge detection signal (403). By the above operation, the edge detection signal (403) extended in the vertical direction is obtained.

Next, the edge detection signal (4
03) is a 1-sample delay circuit (904) and OR circuit (90
Entered in 6). The one-sample delay circuit (904) outputs an edge detection signal (404) obtained by delaying the input edge detection signal (403) by one sample period. The one-sample delay circuit (905) outputs an edge detection signal (405) obtained by further delaying the edge detection signal (404) input from the one-sample delay circuit (904) by one sample period. OR circuit (90
6) takes the logical sum of the input edge detection signal (403), edge detection signal (404) and edge detection signal (405), and outputs the edge detection signal (208). By the above operation, the edge detection signal (208) expanded in the vertical direction and the horizontal direction can be obtained. This edge detection signal (208) is
It is input to the switch circuit (7).

Next, the horizontal / vertical direction noise suppression circuit (10) detects the correlation in the horizontal and vertical directions from the input video signal (101), and uses the filter in the highly correlated direction to input video signal (10
Perform noise suppression in 1). FIG. 4 is a block circuit diagram showing an example of the configuration of this circuit. The operation of this circuit will be described below. The input video signal (101) is a 1-line delay circuit (100
1) and addition circuit (1003). The 1-line delay circuit (1001) delays the video signal (101) by 1 line,
The video signal (501) shown in FIG. 8 (b) is output. The 1-line delay circuit (1002) delays the video signal output from the 1-line delay circuit (1001) by 1 line and outputs a video signal (502) shown in FIG. 8 (c). The addition circuit (1003) adds the video signal (101) and the video signal (502), and FIG. 8 (d)
The video signal (503) shown in is output. 1/2 times circuit (1004)
Is the video signal (503) input from the adder circuit (1003)
Is halved, and the video signal (504) shown in FIG. 8 (e) is output. 1 sample delay circuit (1005), 1/2 time circuit (100
4) The video signal (505) obtained by delaying the video signal input by 1) for one sample period is output. Next, the 1-sample delay circuit (1009) delays the video signal (501) input from the 1-line delay circuit (1001) for 1 sample period and outputs the video signal (506) shown in FIG. 9 (b). . The one-sample delay circuit (1010) delays the video signal (506) input from the one-sample delay circuit (1009) by one sample period and outputs a video signal (507) shown in FIG. 9 (c). The addition circuit (1011) adds the video signal (501) input from the 1-line delay circuit (1001) and the video signal (507) input from the 1-sample delay circuit (1010), and FIG. 9 (d) The video signal (508) shown in is output. 1/2 circuit (1012)
Is the video signal (508) input from the adder circuit (1011)
Is multiplied by 1/2 to output the video signal (509) shown in FIG. 9 (e). The subtraction circuit (1006) is a 1-sample delay circuit (100
The video signal (505) input from the 1-sample delay circuit (1005) is subtracted from the video signal (506) input from 9), and the video signal (510) shown in FIG. 8 (f) is output.
The adder circuit (1007) receives the video signal (506) input from the 1-sample delay circuit (1009) and the 1-sample delay circuit (1
The video signal (505) input from 005) is added and the video signal (511) shown in FIG. 8 (g) is output. The 1/2 circuit (1008) multiplies the video signal (511) input from the adder circuit (1007) by 1/2 to generate the video signal (51) shown in FIG.
2) is output. The subtraction circuit (1013) is a half of the video signal (506) input from the 1-sample delay circuit (1009).
The video signal (509) input from the multiplication circuit (1012) is subtracted, and the video signal (513) shown in FIG. 9 (f) is output.
The adder circuit (1014) adds the video signal (506) input from the 1-sample delay circuit (1009) and the video signal (509) input from the 1/2 times circuit (1012), and FIG. The video signal (514) shown in g) is output. The 1/2 circuit (1015) halves the video signal (514) input from the adder circuit (1014).
Then, the video signal (515) shown in FIG. 9 (h) is output.

Next, the fixed storage circuit (1016) is inputted with the video signal (510) which is a vertical high frequency signal and the video signal (513) which is a horizontal high frequency signal, as shown in FIG. Then, the correlation between the horizontal and vertical directions is determined from the levels of the high-frequency signals in the horizontal and vertical directions, and the control signal (516) is output to the switch circuit (1
017). The switch circuit (1017) uses the control signal (516) to output a video signal (512) that has passed through the vertical low-pass filter, a video signal (515) that has passed through the horizontal low-pass filter, and the input video signal (101). And a video signal (506) delayed in the horizontal and vertical directions are switched to output a video signal (209) in which noise is suppressed in the horizontal and vertical directions.

By the above operation, the horizontal / vertical noise suppression circuit (10)
When the horizontal correlation is high, that is, when the horizontal high frequency signal level is low, the horizontal low-pass filter is passed to output the noise-suppressed video signal (515), and the vertical correlation is high. When it is high, that is, when the vertical high-frequency signal level is low, a video signal (512) that suppresses noise is output by passing through the low-pass filter in the vertical direction, and when both the horizontal and vertical correlations are low, The input video signal (101) is output as it is.

Next, the delay circuit (11) delays the video signal (209) input from the horizontal / vertical noise suppression circuit (10) and outputs the time-compensated video signal (210) to the switch circuit (7). . The switch circuit (7) is controlled by the edge detection signal (208) input from the edge detection signal expansion circuit (9), and when the edge detection signal (208) is input, the delay circuit (11). The frame signal input from the delay circuit (6) is selected and output from the input video signal (210) in which noise is suppressed by the horizontal and vertical correlations input, and when the edge detection signal (208) is not input. A video signal (206) whose noise is suppressed by the correlation between them is selected and is output to the output terminal (12) as a video signal (211). This video signal (211) is input to the frame memory (2). By the above operation, when an image is scene-changed, the edge of an object having a small level difference between frames is less likely to appear as an afterimage on the screen.

〔The invention's effect〕

As described above, according to the present invention, the edge of the video signal one frame before is detected, and the noise suppression around the edge of the video signal one frame before is performed horizontally without using the noise suppression by using the correlation between the frames. Since the noise is suppressed by utilizing the correlation in the vertical or vertical direction, it is effective in reducing the appearance of an edge of an object having a small level difference between frames as an afterimage on the screen.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a block circuit diagram of a configuration example of an edge detection circuit of this embodiment, and FIG. 3 is a configuration of a detection signal expansion circuit of this embodiment. An example block circuit diagram, FIG. 4 is a block circuit diagram of a configuration example of the horizontal / vertical direction noise suppressing circuit of this example, and FIG.
FIG. 7 is a signal waveform diagram of each part for detecting an edge in the vertical direction in the edge detection circuit of FIG. 2, and FIG. 6 is a signal waveform diagram of each part for detecting an edge in the horizontal direction in the edge detection circuit of FIG. FIG. 8 is a diagram showing how the edge detection signal in the horizontal and vertical directions in the edge detection circuit of FIG. 2 is converted into a binary edge detection signal, and FIG. 8 is a vertical direction in the horizontal / vertical noise suppression circuit of FIG. FIG. 9 is a signal waveform diagram of each part for performing the video signal processing of FIG. 9, FIG. 9 is a signal waveform diagram of each part for performing the horizontal video signal processing in the horizontal / vertical noise suppression circuit of FIG. 3, and FIG. FIG. 11 is a block diagram of the correlation of the fixed memory circuit in the horizontal / vertical noise suppression circuit, FIG. 11 is a block circuit diagram of a conventional noise suppression device, and FIG. 12 is an input / output characteristic diagram of the fixed memory circuit of this conventional example. (2) ... Frame memory, (3), (5) ... Subtraction circuit, (4) ... Fixed storage circuit, (6), (11) ... Delay circuit, (7) ... Switch circuit, ( 8) ... edge detection circuit, (9) ... edge detection signal expansion circuit, (10) ...
Horizontal and vertical noise suppression circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A means for creating a first video signal in which noise is suppressed by utilizing a frame correlation between an input video signal and an output video signal of the noise suppression device, and horizontal and vertical correlations of the input video signal. Detects and outputs a video signal with noise components suppressed through a vertical low-pass filter when the vertical correlation is high, and outputs a video signal with noise suppressed through a horizontal low-pass filter when the horizontal correlation is high. Is output, and when the correlation is low in the horizontal and vertical directions, the second video signal generating means for suppressing the noise for outputting the input video signal, and the edge of the output video signal are detected to detect the horizontal and vertical directions. Means for creating an expanded edge detection signal, and selecting the second video signal when the edge detection signal is being output, and outputting the edge detection signal. Adaptive noise suppression apparatus provided with a selection means for selecting and outputting said first video signal to Itoki.