KR0155506B1 - Metal oxide semiconductor transistor - Google Patents
Metal oxide semiconductor transistorInfo
- Publication number
- KR0155506B1 KR0155506B1 KR1019940036344A KR19940036344A KR0155506B1 KR 0155506 B1 KR0155506 B1 KR 0155506B1 KR 1019940036344 A KR1019940036344 A KR 1019940036344A KR 19940036344 A KR19940036344 A KR 19940036344A KR 0155506 B1 KR0155506 B1 KR 0155506B1
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- gate
- drain
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- oxide
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- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- 239000002184 metal Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000008859 change Effects 0.000 abstract description 2
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
MOS 트랜지스터의 게이트(3)와 인접한 소스/드레인(9)의 가장자리에 홈을 형성하여 소스/드레인 부근에서 채널형태를 바꾸면, 드레인 부근에서 형성되는 전기장이 채널영역으로 침투하는 것을 방지하여 짧은 채널효과를 억제할 수 있으며, 문턱전압의 조절이 용이하며, 소스/드레인 가장자리에 형성된 홈에 의하여 소스/드레인 영역의 접합깊이를 보다 깊게 할 수 있으므로 소스/드레인 저항을 줄일 뿐아니라, 금속배선에 의한 접합파괴나 일렉트로마이그레이션에 의한 신뢰성 저하를 억제할 수 있다.If grooves are formed at the edges of the source / drain 9 adjacent to the gate 3 of the MOS transistor to change the channel shape in the vicinity of the source / drain, a short channel effect is prevented by the electric field formed near the drain from penetrating into the channel region. , The threshold voltage can be easily controlled, and the depth of the junction of the source / drain region can be deepened by the groove formed at the edge of the source / drain, thereby reducing the source / drain resistance and joining by metal wiring. Deterioration in reliability due to breakdown or electromigration can be suppressed.
Description
제1도는 종래의 매몰 채널 MOS 트랜지스터.1 is a conventional buried channel MOS transistor.
제2도는 본 발명의 바람직한 실시예에 따른 혼합형 채널 MOS 트랜지스터.2 is a mixed channel MOS transistor according to a preferred embodiment of the present invention.
제3도의 (a) 내지(d)는 본 발명의 바람직한 실시예의 제조방법을 공정순서대로 나타낸 단면도.(A)-(d) of FIG. 3 are sectional drawing which showed the manufacturing method of the preferable Example of this invention in process order.
제4도는 본 발명의 다른 실시예에 따른 혼합형 채널 MOS 트랜지스터.4 is a mixed channel MOS transistor according to another embodiment of the present invention.
본 발명은 금속-산화물-반도체(metal oxide semiconductor;MOS) 전계효과 트랜지스터에 관한 것으로, 특히 짧은 채널(sub-㎛영역)을 가지는 pMOSFET에 나타나는 짧은 채널효과(short channel effect)와 소스/드레인(source/drain) 저항 증가를 방지하고, 금속배선에 의한 접합파괴(junction spike) 및 일렉트로 마이그레이션(electromigration:EM)으로 인한 신뢰성 저하를 억제할 수 있는 혼합형 채널 MOS 트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal oxide semiconductor (MOS) field effect transistors, in particular short channel effects and sources / drains present in pMOSFETs having a short channel (sub-μm region). The present invention relates to a mixed channel MOS transistor capable of preventing an increase in resistance and suppressing a decrease in reliability due to junction spike and electromigration (EM) caused by metallization.
제1도는 종래의 매몰채널(buried channel) MOS 트랜지스터를 나타낸 것이다.1 shows a conventional buried channel MOS transistor.
제1도에서 나타낸 MOS 소자의 단점은 집적도가 높아짐에 따라 MOS 소자의 채널길이가 짧아지면, 비례축소법칙(scaling rule)에 따라 소스/드레인 영역의 접합깊이도 얕아질 때 신뢰성이 떨어지는 것이다. 상세하게 설명하면, p형 불순물인 붕소(boron)이온은 규소기판(1)내에서의 이동도가 커서 비례축소법칙에 따른 접합깊이를 만족시킬 수 없다. 따라서, 접합깊이가 자연적으로 깊어져 누설전류가 크게 증가한다. 표면채널(surface channel) MOS 트랜지스터를 채택하여 접합깊이를 얕게 하더라도 소스/드레인 저항이 증가하게 되고, 금속배선에 의해 접합파괴가 일어나고 그리고 EM에 의하여 신뢰성이 저하된다.The disadvantage of the MOS device shown in FIG. 1 is that when the channel length of the MOS device is shortened as the degree of integration increases, the reliability of the MOS device becomes poor when the junction depth of the source / drain regions becomes shallow according to a scaling rule. In detail, boron ions, which are p-type impurities, have a high mobility in the silicon substrate 1 and cannot satisfy the junction depth according to the proportional reduction law. Therefore, the junction depth naturally deepens and the leakage current greatly increases. Even if the depth of the junction is shallow by adopting the surface channel MOS transistor, the source / drain resistance increases, the junction breakage occurs due to the metal wiring, and the reliability is degraded by the EM.
본 발명의 목적은 짧은 채널을 가지는 pMOSFET에 나타나는 짧은 채널효과와 소스/드레인 저항 증가를 방지하고, 금속배선에 의한 접합파괴 및 EM으로 인한 신뢰성 저하를 억제할 수 있는 혼합형 채널 P형 MOS 트랜지스터 및 그 제조방법을 제공하는 것이다.Summary of the Invention An object of the present invention is to provide a mixed channel P-type MOS transistor capable of preventing short channel effects and increase in source / drain resistance in a pMOSFET having a short channel, and suppressing junction breakdown caused by metallization and reliability deterioration due to EM. It is to provide a manufacturing method.
이하, 첨부된 도면들을 참조하면서 본 발명의 실시예들에 대해 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[실시예 1]Example 1
제2도에는 본 발명의 바람직한 일 실시예에 따른 혼합형 채널 MOS 트랜지스터가 도시되어 있다. 본 실시예에 따라, 제2도에 도시된 바와 같이, 게이트(3)와 인접한 소스/드레인(9)의 가장자리에 홈을 형성하여 소스/드레인 부근에서 채널형태를 바꾸면, 드레인 부근에서 형성되는 전기장이 채널영역으로 침투하는 것을 방지하여 짧은 채널효과를 억제할 수 있으며, 문턱전압의 조절이 용이하며, 소스/드레인 가장자리에 형성된 홈에 의하여 소스/드레인 영역의 접합깊이를 보다 깊게 할 수 있으므로 소스/드레인 저항을 줄일 뿐아니라, 금속배선에 의한 접합파괴나 EM에 의한 신뢰성 저하를 억제할 수 있다.2 shows a mixed channel MOS transistor according to one preferred embodiment of the present invention. According to this embodiment, as shown in FIG. 2, when a groove is formed at the edge of the source / drain 9 adjacent to the gate 3 to change the channel shape in the vicinity of the source / drain, an electric field is formed near the drain. By preventing penetration into the channel region, short channel effect can be suppressed, threshold voltage can be easily controlled, and the depth of junction of the source / drain region can be deepened by the groove formed at the source / drain edge. In addition to reducing the drain resistance, it is possible to suppress junction breakdown due to metal wiring and reliability deterioration due to EM.
제3도의 (a) 내지 (d)는 본 실시예에 따른 혼합형 채널 PMOS 트랜지스터의 제조방법을 공정순서대로 나타낸 것이다. 다음에는 이들 도면에 의거하여 혼합형 채널 MOS 트랜지스터의 제조방법에 대해 상세히 설명한다.3A to 3D show a method of manufacturing a mixed channel PMOS transistor according to the present embodiment in the order of a process. Next, a method of manufacturing a mixed channel MOS transistor will be described in detail with reference to these drawings.
먼저, 제3도의 (a)에 도시된 바와 같이, 웰(well) 형성 및 활성영역 공정이 완료된 n형 기판(1)의 표면에 카운터(Counter) 도핑을 위한 p형의 실리콘층(15, 제2도에 도시됨)을 형성하여 카운터 도핑영역을 형성한 후, 그 위에 게이트 절연막(2)으로서 규소산화막을 성장(혹은 증착)시킨 후, 다결정 규소막을 증착하고 게이트 형상(3)을 정의한다.First, as shown in FIG. 3A, the p-type silicon layer 15 for counter doping is formed on the surface of the n-type substrate 1 on which the well formation and active region processes are completed. After forming a counter doped region (shown in FIG. 2), a silicon oxide film is grown (or deposited) as a gate insulating film 2 thereon, and then a polycrystalline silicon film is deposited to define a gate shape 3.
이어, 다결정규소로 이루어지는 게이트(3)의 표면을 열산화시키거나 게이트(3)의 표면에 화학적 기상증착법(CVD)에 의하여 산화막을 증착시켜 게이트(3)의 주변에 얇은 산화막(4)을 형성한다. 규소질화막을 증착하고 비등방적 반응성 이온식각(RIE)으로 게이트(3)의 양측면 위에 측벽(5)을 형성한다. 소스/드레인이 형성될 영역과 게이트(3)의 표면 위에 고온로를 사용하여 열산화막(6)을 형성한다.Subsequently, a thin oxide film 4 is formed around the gate 3 by thermally oxidizing the surface of the gate 3 made of polycrystalline silicon or by depositing an oxide film on the surface of the gate 3 by chemical vapor deposition (CVD). do. A silicon nitride film is deposited and sidewalls 5 are formed on both sides of the gate 3 by anisotropic reactive ion etching (RIE). The thermal oxide film 6 is formed using a high temperature furnace on the region where the source / drain is to be formed and the surface of the gate 3.
제3도의 (c)를 참조하여, 게이트(3)의 측벽(5)을 건식식각법 혹은 습식식각법을 사용하여 제거한 후, 표면이 노출된 산화막(2)을 건식식각법으로 제거한다.Referring to FIG. 3C, after the sidewall 5 of the gate 3 is removed using a dry etching method or a wet etching method, the oxide film 2 having a surface exposed is removed by a dry etching method.
소스/드레인 가장자리에 표면이 노출된 기판(1)을 건식식각법 혹은 습식식각법을 사용하여 일정깊이(30nm에서 300nm)만큼 제거하여 홈을 형성한다. 이때, p+형의 소스/드레인 영역(7)은 산화막(6)에 의해 보호된다.The substrate 1 having the surface exposed at the source / drain edges is removed by a predetermined depth (30 nm to 300 nm) using dry etching or wet etching to form grooves. At this time, the source / drain region 7 of p + type is protected by the oxide film 6.
다음, 제3도의 (d)를 참조하여, 홈의 내부 표면 위에 게이트 절연막으로 사용될 규소산화막(7)을 고온로에서 열성장시키고 다결정 규소막을 증착한 다음 반응성 이온식각법으로 다결정 규소막을 식각하여 게이트(3)의 양측면에 측벽(8)을 형성한다. 이후의 공정은 종래의 pMOSFET 제조과정과 동일하다. 다만, 게이트전극을 형성할 때 다결정규소로 이루어지는 측벽(8)에도 전압이 인가되도록 접촉홀(contact)을 형성한다.Next, referring to (d) of FIG. 3, the silicon oxide film 7 to be used as the gate insulating film on the inner surface of the groove is thermally grown in a high temperature furnace, a polycrystalline silicon film is deposited, and the polycrystalline silicon film is etched by reactive ion etching. Side walls 8 are formed on both sides of (3). The subsequent process is the same as the conventional pMOSFET fabrication. However, when forming the gate electrode, a contact hole is formed so that a voltage is applied to the sidewall 8 made of polycrystalline silicon.
이상에서 설명된 바와 같이 제조된 혼합형 채널 MOS 트랜지스터는 제2도와 동일하다. 제2도를 참조하여, 혼합형 채널 MOS 트랜지스터의 채널영역 A는 매몰채널로, 채널영역 B는 표면채널로 구성되어 있다. 따라서 불순물의 농도분포로 채널영역 A의 불순물형은 웰과 반대되는 p형을, 소스/드레인(9)의 가장자리에 있는 채널영역 B의 불순물형은 웰과 동일하다. 물론 소스/드레인 영역의 불순물형을 p형이다.The mixed channel MOS transistor fabricated as described above is the same as in FIG. Referring to FIG. 2, the channel region A of the mixed channel MOS transistor is composed of a buried channel, and the channel region B is composed of a surface channel. Therefore, the impurity concentration of the channel region A is the p type opposite to the well, and the impurity type of the channel region B at the edge of the source / drain 9 is the same as the well. Of course, the impurity type of the source / drain region is p-type.
[실시예 2]Example 2
제4도는 본 발명의 바람직한 다른 실시예를 나타낸 것이다. 이 실시예에서, 채널영역 A는 웰과 동일한 n형으로 형성되고, 채널영역 B는 웰과 반대되는 형인 p형으로 형성된다.4 shows another preferred embodiment of the present invention. In this embodiment, the channel region A is formed in the same n-type as the well, and the channel region B is formed in the p-type, which is the type opposite to the well.
이상의 실시예들에서, 게이트에 인접한 소스/드레인의 가장자리에 형성되는 홈은 사각형이외에도 다각형 또는 둥근형으로 형성될 수 있다.In the above embodiments, the grooves formed at the edges of the source / drain adjacent to the gate may be formed in a polygon or round shape in addition to the quadrangle.
본 발명에 의한 혼합형 채널 MOS 트랜지스터는 소자구조상 종래의 표면채널형이나 매몰채널형 혼합형 채널 MOS 트랜지스터에 비하여 다음과 같은 여러 가지 장점들을 지닌다. 게이트와 인접한 소스/드레인 가장자리의 홈에 의하여 확산층이 모스소자의 채널로 침투하는 것을 억제할 수 있으므로 동일한 마스크를 사용하여 제조된 종래의 모스소자보다 유효채널길이가 늘어나며, 드레인 부근에서 형성되는 전기장이 채널영역으로 침투하는 것을 방지하여 짧은 채널효과를 억제할 수 있으며, 문턱전압의 제어가 용이하며, 펀치쓰루(punchthrough)누설, DIBL(Drain Induced Barrier Lowering)등에 의한 누설전류를 억제할 수 있다.The mixed channel MOS transistor according to the present invention has several advantages as compared to the conventional surface channel type or buried channel type mixed channel MOS transistor in terms of device structure. Since the diffusion layer can be prevented from penetrating into the channel of the MOS device by the groove of the source / drain edge adjacent to the gate, the effective channel length is longer than that of the conventional MOS device manufactured using the same mask, and the electric field formed near the drain By preventing penetration into the channel region, short channel effects can be suppressed, threshold voltage can be easily controlled, and leakage currents due to punchthrough leakage and drain induced barrier lowering (DIBL) can be suppressed.
또한, 소스/드레인 가장자리에 형성된 홈에 의하여 소스/드레인 영역의 접합깊이를 보다 깊게 할 수 있으므로 소스/드레인 저항을 줄일 뿐 아니라, 금속배선에 의한 접합파괴나 EM에 의한 신뢰성저하를 억제할 수 있다.In addition, the depth of the junction of the source / drain regions can be deepened by the grooves formed at the source / drain edges, thereby reducing the source / drain resistance, as well as suppressing the junction breakdown caused by metal wiring and the reliability deterioration due to EM. .
Claims (5)
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| KR1019940036344A KR0155506B1 (en) | 1994-12-23 | 1994-12-23 | Metal oxide semiconductor transistor |
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| KR1019940036344A KR0155506B1 (en) | 1994-12-23 | 1994-12-23 | Metal oxide semiconductor transistor |
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