KR0154013B1 - Mute circuit for a video signal - Google Patents

Abstract

The present invention relates to a mute circuit of a video signal capable of eliminating interference between a blue background signal generated by an OSD IC and a video signal generated by a video IC. According to the present invention, a pseudo-vertical synchronizing signal having a high level signal waveform of a predetermined period when a specific function is set, such as a channel switching, or a general function mode, is combined with a low level mute signal or a high level signal generated from an OSD IC. The logical sum and the muting control unit selectively provide the operating power of the power stage to the muting unit, thereby widening the muting or synchronizing signal interval of the video signal. Therefore, interference between the blue background signal generated in the OSD IC circuit and the output video signal of the video processing IC can be eliminated.

Description

Mute Circuit of Video Signal

1 is a mute circuit diagram of a video signal according to the prior art.

2 is a mute circuit diagram of a video signal according to the present invention.

3 is a waveform diagram for explaining signals generated in respective parts of FIG.

* Explanation of symbols for main parts of the drawings

10: first input terminal 11: second input terminal

12: input signal switch stage 13: video processing IC

14: OSD IC 15: Output signal switch stage

16,17: RF, line output stage 18: switching unit

19: video processing unit 20: command authorization unit

22: microcomputer 24: logic sum circuit

26: muting control unit 28: muting unit

The present invention relates to a mute circuit of a video signal, and more particularly, to eliminate interference between an OSD screen forming a blue background and a video signal input or reproduced from the outside when a reservation and channel switching or a general function are set. It relates to a mute circuit of a video signal.

1 is a mute circuit diagram of a video signal according to the prior art, wherein reference numeral 10 is a first input terminal for inputting a received television signal, and 11 is a second input terminal for inputting a signal input and reproduced from an external video device. to be.

Reference numeral 12 denotes an input signal switch for selecting one of the first and second input terminals 10-11, and 13 denotes a video signal that is selectively input by the input signal switch 12. It is a video processing IC.

Reference numeral 14 denotes an OSD IC for signal processing such that a background screen, text insertion, and menus are displayed on a monitor of an image device, and 15 denotes an operation mode that is identical to an operation mode initially inputted by the OSD IC 15. Output signal switch stage for output.

Reference numerals 16 and 17 denote RF line output stages for outputting RF or line output video signals signaled by the video processing IC 13 and the OSD IC 14, respectively.

Reference numeral 18 denotes a video signal processed by the video processing IC 13 to form a back blue screen provided by the OSD IC 14 when certain functions such as reservation / channel switching or general functions are set. A switching unit including a switching element Q1 for bypassing a voltage level signal to the transistor Q1.

In the mute circuit of the conventional video signal configured as described above, the video signal of the voltage level output from the video processing IC 13 is muted only by the transistor Q1, which is a switching element. Interference between the generated blue background signals is generated. As a result, streaks occur on the screen due to interference of video signals and background screens and characters caused by the OSD IC.

Accordingly, the present invention has been made to solve the shortcomings of the prior art, in order to eliminate the interference between the background image and the video signal being input or reproduced when setting a specific function, such as a reservation / channel switching or a general function setting It is an object of the present invention to provide a mute circuit of a video signal which completely mutes the input or reproduced video signal.

According to the present invention for achieving the above object, the mute circuit for muting the video signal output from the video signal processing circuit provides a specific function mode setting control command or a general function mode setting control command such as reservation or channel switching. Instruction granting unit for performing; A pseudo vertical synchronizing signal having a waveform of a high level signal having a predetermined period larger than a section of the vertical synchronizing signal of the video signal, and storing the pseudo vertical synchronizing signal in response to the specific function mode setting control command or the general function mode setting control command A microcomputer that reads and outputs a signal and outputs an OSD driving control signal, and generates a blue background signal in response to the OSD driving control signal, outputs a high level waveform signal in a specific function mode, and generates a low level signal in a normal function mode. An OSD IC for outputting a blue mute signal; A logic sum circuit stage for logic-suming and outputting a pseudo-synchronous signal output from the microcomputer and a predetermined level signal output from the OSD IC; A muting controller for selectively bypassing the operating power of the power stage to ground according to the OR signal provided by the OR circuit stage, wherein the muting control unit is connected to a base and a power terminal Vcc connected to an output of the OR circuit stage. A first switching element Q2 having an associated collector and an emitter connected to ground; A muting unit configured to provide a voltage level corresponding to the video signal to the OSD IC according to an output of the muting control unit, wherein the muting unit is a base to which the video signal is applied, a base connected between a collector and a power terminal of the muting control unit; And a second switching element Q3 having an emitter connected to an input of the OSD IC.

Hereinafter, the present invention will be described in detail with reference to the illustrated drawings.

FIG. 2 is a video signal and mute circuit diagram according to the present invention, and FIG. 3 is a waveform diagram for explaining FIG.

In FIG. 2, the command applier 20 may provide the microcomputer 22, which will be described later, by the user to control commands for setting a specific function mode such as a reservation or channel switching, and a general function mode such as on / off. It is configured to be.

The microcomputer 22 responds to the setting control command of the specific function mode or the general function mode by the command application unit 20, and the like-vertical synchronizing signal of the pulse waveform stored in an unshown storage means of the microcomputer 22 (first (A) is read out and output to one input terminal of the logic sum circuit stage 24 to be described later, and the OSD operation control signal is set so that the blue back screen can be set by the OSD IC 14. Is authorized. According to the present invention, the high level section of the pseudo vertical sync signal shown in FIG. 3A is approximately 1.5 times the section of the vertical sync signal 30 in the video signal illustrated in FIG.

The OSD IC 14 is configured to provide a signal of a predetermined level, such as FIG. 3 (b) and (c), to the other input terminal of the logical sum circuit stage 24 described later in conjunction with the blue background screen.

The OR circuit stage 24 is configured to logically process the pseudo vertical sync signal output from the microcomputer 22 and the signal of a predetermined level output from the OSD IC 14.

The muting control section 26, the video processing section 19, and the muting section 28 are detailed configuration diagrams of the video processing ICs constructed in accordance with the present invention, and the muting control section 26 according to the signal output from the OR circuit 24. A switching element Q2 for switching control of a video signal output from the video signal processing unit 19 and provided to the OSD IC 14, a protective resistor R1 and a bias storage for protecting the switching element Q2 ( R2-R3).

The muting unit 28 is composed of a transistor Q3, a bias resistor R4-R5, a protective resistor R6, and a capacitor C1, and has a video of a voltage level according to the video signal output from the video signal IC 13. The signal is output to the OSD IC 14. The video signal processed by the video signal processor 19 is applied to the base of the transistor Q3 of the muting unit 28, and its collector is a collector and a power supply terminal Vcc of the switching transistor Q2 of the muting control unit 26. And its emitter is connected to the input of the OSD IC 14.

The present invention configured as described above is described in detail as follows.

First, when the general function mode is to be set, the user provides the general function mode setting signal to the microcomputer 22 through the command application unit 20. The microcomputer 20 reads a pseudo-vertical synchronous signal as shown in FIG. 3 (a) stored in the storage means and provides the same to the diode D1 connected to one input terminal of the logic sum circuit stage 24, and simultaneously displays an OSD driving control signal. To the OSD IC 14.

In response to the OSD driving control signal, the OSD IC 14 generates a blue background signal and simultaneously transmits a high level signal as shown in FIG. 3B through the other input terminal of the OR circuit 24. To provide.

The AND circuit stage 24 mutes the signal of the OR waveform by ORing the forced synchronization signal (FIG. 3A) provided from the microcomputer 22 with the high level signal output from the OSD IC 13. Is provided to the switching element Q1. At this time, the OR signal by the OR circuit stage 24 is generated as the same waveform as the signal provided from the microcomputer 22.

In the muting control section 26, the switching element Q2 is turned on during the high level signal section of the logical sum waveform signal provided from the OSD IC 14 to maintain the conduction state and to turn off during the low level signal section. . Therefore, while the switching element Q2 of the muting control unit 26 maintains the conduction state, the operating power of the power supply terminal Vcc is bypassed to the ground terminal of the switching element Q2 of the muting control unit 26, and muting While the switching element Q2 of the control unit 26 maintains the off state, the operating power of the power supply terminal Vcc is applied to the collector of the switching element Q3 of the muting unit 28.

The switching element Q3 in the muting unit 28 is turned on and off in accordance with the video signal (Fig. 3 (d)) output from the video processing unit 19, so that the voltage level of the waveform as shown in Fig. 3 (e) is reduced. Generate a signal. In FIG. 3 (f), it can be seen that the period of the vertical synchronization signal is widened for a period corresponding to the high level period of the output of the OR circuit 24. The output of the mute unit 28 is provided to the input terminal of the OSD IC 14 to remove the streaks caused by the interference with the video processing IC.

On the contrary, when performing channel switching or reservation setting, the user provides the microcomputer 22 with a specific function mode setting signal through the command application unit 20. The microcomputer 20 reads a pseudo-vertical synchronous signal as shown in FIG. 3 (a) stored in the storage means and provides the same to the diode D1 connected to the input terminal of one side of the logic sum circuit 14, and at the same time, the OSD drive control signal. To the OSD IC 14.

The OSD IC 14 generates a blue background signal and simultaneously provides a low level OSD blue mute signal as shown in FIG. 3C to the diode D2 through the other input terminal of the logic sum circuit 24.

The OR circuit stage 24 mutes the signal of the OR waveform by ORing the pseudo synchronizing signal provided from the microcomputer 22 (FIG. 3A) and the low level OSD blue mute signal output from the OSD IC 13. The switching element Q1 of the control unit 28 is provided. At this time, the OR signal at the OR circuit stage 24 is generated as a low level signal.

Therefore, during the whole period of the low-level OR signal from the OR circuit stage 24, the switching element Q2 of the duty controller 26 is kept turned off. Therefore, while the switching element Q2 of the muting control unit 26 maintains the turn-off state, the operating power of the power supply terminal Vcc is bypassed to the ground terminal of the switching element Q1 of the muting control unit 26. At this time, since the collector stage of the switching element Q2 of the muting unit 28 connected to the collector stage of the switching element Q2 in the muting control unit 26 maintains the low level state, the third processing unit is performed. Even when a video signal as shown in FIG. D is provided, a low level output voltage as shown in FIG. 3 is generated through the switching element Q3 of the muting unit 28. Therefore, the output of the video processing unit 19 is completely muted inside the video processing IC. The low level output voltage (FIG. 3f) generated by the muting unit 28 is input to the OSD IC 14, and the OSD The IC 14 is mixed with the blue background signal and output to the outside through the switch 15.

Therefore, the blue background screen generated by the OSD IC 13 can be displayed as a signal from which interference of the voltage level input from the video processing IC is completely removed.

As described above, the present invention can eliminate streaks caused by interference between the video signal provided from the video IC and the blue back signal generated by the OSD IC when the reservation and channel switching or the general function are set.

Claims (1)

A mute circuit for muting a video signal output from a video signal processing circuit, comprising: a command applying unit for providing a specific function mode setting control command or a general function mode setting control command such as a reservation or channel switching; A pseudo vertical synchronizing signal having a waveform of a high level signal having a predetermined period larger than a section of the vertical synchronizing signal of the video signal, and storing the pseudo vertical synchronizing signal in response to the specific function mode setting control command or the general function mode setting control command A microcomputer that reads and outputs a signal and outputs an OSD driving control signal; An OSD IC generating a blue background signal in response to the OSD driving control signal, outputting a high level waveform signal in a specific function mode, and outputting a low level blue mute signal in a normal function mode; A logic sum circuit stage for logic-suming and outputting a pseudo-synchronous signal output from the microcomputer and a signal having a predetermined level output from the OSD IC; A muting controller for selectively bypassing the operating power of the power stage to ground according to the OR signal provided by the OR circuit stage, wherein the muting control unit is connected to a base and a power terminal Vcc connected to an output of the OR circuit stage. A first switching element Q2 having an associated collector and an emitter connected to ground; A muting unit configured to provide a voltage level corresponding to the video signal to the OSD IC according to an output of the muting control unit, wherein the muting unit is a base to which the video signal is applied, a base connected between a collector and a power terminal of the muting control unit; And a second switching element (Q3) having an emitter connected to an input of said OSD IC.