KR0153493B1 - Insulation method of semiconducor device - Google Patents

Insulation method of semiconducor device Download PDF

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KR0153493B1
KR0153493B1 KR1019950036330A KR19950036330A KR0153493B1 KR 0153493 B1 KR0153493 B1 KR 0153493B1 KR 1019950036330 A KR1019950036330 A KR 1019950036330A KR 19950036330 A KR19950036330 A KR 19950036330A KR 0153493 B1 KR0153493 B1 KR 0153493B1
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film
polysilicon
insulating film
interlayer insulating
semiconductor device
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KR1019950036330A
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Korean (ko)
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KR970023833A (en
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석종욱
박진호
김태룡
김태욱
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김광호
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 제조방법에 관한 것으로서, 특히 폴리실리콘과 금속막 사이의 절연 특성을 개선시키는 반도체 장치의 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an insulating film of a semiconductor device for improving the insulating property between polysilicon and a metal film.

발명은 등방성식각 특성을 이용하여 절연 특성을 개선하는 제조방법으로서 얇은 절연막을 이용하여 절연막 아래의 폴리실리콘 막질을 언터컷 단면으로 만드는 플라즈마 식각공정과, 플라즈마 식각 설비에서 SF6, CF, NF3, O2GAS를 혼합하여 폴리실리콘을 등방성 식각하는 공정과, 플라즈마 식각설비에서 등방성식각 특성을 이용하여 반도체 웨이퍼의 임계영역을 제어하는 공정을 포함한다.The invention is a manufacturing method to improve the insulating properties by using the isotropic etching characteristics, the plasma etching process to make the polysilicon film under the insulating film to the undercut cross-section using a thin insulating film, SF 6 , CF, NF 3 , Isotropic etching of polysilicon by mixing O 2 GAS, and the process of controlling the critical region of the semiconductor wafer using the isotropic etching characteristics in the plasma etching equipment.

Description

반도체소자의 절연방법Insulation Method of Semiconductor Devices

제1a도 내지 제1d도는 본 발명에 따른 반도체 장치의 절연막 형성방법을 공정순서대로 나타낸 단면도.1A to 1D are cross-sectional views showing an insulating film forming method of a semiconductor device according to the present invention in the order of process.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 폴리실리콘막 2 : 제1층간절연막1: polysilicon film 2: first interlayer insulating film

3 : 포토레시스트 4 : WSi3: photoresist 4: WSi

5 : BPSG 6 : 제2층간절연막5: BPSG 6: Second interlayer insulating film

7 : 금속막7: metal film

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 폴리실리콘과 금속막 사이의 절연 특성을 개선시키는 반도체 소자의 절연 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for insulating a semiconductor device for improving the insulating properties between polysilicon and a metal film.

종래의 반도체 소자의 절연막을 형성할 때, 폴리실리콘과 금속막 사이의 충분한 절연 마진의 확보를 위해, 층간절연막의 도포 두께를 증가시켜야 한다. 이런 경우 컨택의 종횡비가 증가하므로 컨택에 금속막을 채우는 것이 어렵게 된다.When forming the insulating film of the conventional semiconductor element, in order to ensure sufficient insulation margin between the polysilicon and the metal film, it is necessary to increase the coating thickness of the interlayer insulating film. In this case, it is difficult to fill the metal film in the contact because the aspect ratio of the contact increases.

또한 셀과 그 주변 지역간의 토폴로지(topology)차이로 인하여, 층간절연막의 도포 시에 경계면과 평탄화된 부분의 도포 두께 차이가 발생되며, 셀과 주변지역의 경계에서 토폴리지 차이에 의하여, 층간절연막의 두께가 얇아지므로 절연 특성이 취약하게 된다.In addition, due to the difference in topology between the cell and its surrounding area, a difference in coating thickness between the interface and the flattened part occurs when the interlayer insulating film is applied, and due to the topology difference at the boundary between the cell and the surrounding area, As the thickness becomes thinner, the insulation properties become weak.

한편, 도전성을 띄는 폴리실리콘 식각후, 절연 특성을 개선하기 위해, 폴리실리콘 산화과정을 진행하는 경우, 폴리실리콘 식각시 발생된 폴리실리콘 하단의 층간절연막인 BPSG막의 손실로 인하여, 층간절연막의 하부 막질인 WSi막이 산화됨으로써 반도체 소자의 결함이 발생되는 경우가 많아진다.On the other hand, in order to improve the insulating properties after the conductive polysilicon etching, when the polysilicon oxidation process is performed, the lower film quality of the interlayer insulating film due to the loss of the BPSG film, which is an interlayer insulating film under the polysilicon generated during polysilicon etching The WSi film is oxidized, so that defects in the semiconductor element are often generated.

이와 같이 반도체 소자가 고직접화됨에 따라, 절연물질의 도포 두께를 낮추면서도 절연 특성을 개선시키는 조건이 요구된다.As the semiconductor device becomes high in this manner, a condition for improving the insulating properties while reducing the coating thickness of the insulating material is required.

본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위한 것으로써, 절연물질의 도포 두께를 얇게 하면서 절연 특성을 개선시키는 데 그 목적이 있다.The present invention is to solve the problems of the prior art as described above, the object is to improve the insulating properties while reducing the coating thickness of the insulating material.

상기 목적을 달성하기 위해 본 발명은 폴리실리콘 도포 직후 폴리실리콘산화막 또는 고온산화막과 같은 층간절연막을 얇게 형성하고, 포토레시스트 패턴작업을 한다. 층간절연막을 식각한 후, 폴리실리콘 단면이 산화막 또는 층간절연막에 비해 안으로 들어 가게 등방성식각을 하여 언더컷을 형성한다.In order to achieve the above object, the present invention forms a thin interlayer insulating film such as a polysilicon oxide film or a high temperature oxide film immediately after polysilicon coating, and performs photoresist patterning. After the interlayer insulating film is etched, an undercut is formed by isotropic etching of polysilicon cross-section into the oxide or interlayer insulating film.

이하, 본 발명의 실시예를 첨부 도면에 의거하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체 소자의 절연막형성 방법이다.1A to 1D are a method of forming an insulating film of a semiconductor device according to an embodiment of the present invention.

제1a도를 참조하여, 폴리실리콘막(1) 위에 제1층간절연막(2)을 얇게 입히고, 포토레시스트(3) 패턴 작업을 한 후, 상기 제1층간절연막(2)을 식각한다.Referring to FIG. 1A, the first interlayer insulating film 2 is thinly coated on the polysilicon film 1, the photoresist 3 is patterned, and the first interlayer insulating film 2 is etched.

제1b도와 같이, 언더컷을 형성하기 폴리실리콘막(1)의 측면이 폴리실리콘막(1) 상부의 제1층간절연막(2)보다 안쪽에 있도록 폴리실리콘막(1)을 등방성 플라즈마 식각을 한다. 상기한 등방성 프라즈마식각은 NF3, CF6, O2, 가스를 혼합 사용함으로써 가능하게 된다.As shown in FIG. 1B, the polysilicon film 1 isotropically etched so that the side surface of the polysilicon film 1 is inside the first interlayer insulating film 2 above the polysilicon film 1 to form the undercut. The isotropic plasma etching can be performed by using a mixture of NF 3 , CF 6 , O 2 , and gas.

제1c도와 같이, 포토레시스트막(3)을 제거한 후 제2층간절연막(6)을 기판 전편에 도포하고, 제1d도와 같이 제2층간절연막(6) 위에 금속막(7)을 형성한다.After the photoresist film 3 is removed as shown in FIG. 1C, the second interlayer insulating film 6 is applied to the entire substrate, and the metal film 7 is formed on the second interlayer insulating film 6 as shown in FIG. 1D.

상기한 바와 같은 본 발명에 따르면, 폴리실리콘산화막 및 얇은 층간절연막을 이용하여 절연 특성을 개선함으로서 종횡비를 줄이게 되고, 콘택에 금속막질을 체우는 것이 용이하게 된다.According to the present invention as described above, it is possible to reduce the aspect ratio by improving the insulating properties by using a polysilicon oxide film and a thin interlayer insulating film, it is easy to put a metal film in the contact.

또한 폴리실리콘막을 등방성 플라즈마식각을 함으로써, 폴리실리콘막의 측면이 언더컷으로 형성되므로 종래의 반도체 소자에서 발생된 절연 문제를 해결할 수 있게 된다.In addition, by isotropic plasma etching the polysilicon film, the side surface of the polysilicon film is formed as an undercut, thereby solving the insulation problem generated in the conventional semiconductor device.

Claims (2)

반도체기판 상에 폴리실리콘막을 도포 후 폴리실리콘산화막 또는 고온 산화막과 같은 제1층간절연막을 얇게 형성하는 공정과, 제1층간절연막을 포토레시스트 패턴 작업 후 식각하는 공정과, 언더컷을 형성하기 위해 폴리실리콘막을 등방성 플라즈마식각하는 공정과, 포토레시스트막을 제거한 후 제2층간절연막을 기판 전면에 도포하고 제2층간절연막 상부에 금속막을 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a first interlayer insulating film such as a polysilicon oxide film or a high temperature oxide film after applying a polysilicon film on a semiconductor substrate, etching the first interlayer insulating film after a photoresist pattern operation, and forming a poly to form an undercut. Isotropic plasma etching the silicon film, and after removing the photoresist film, a second interlayer insulating film is applied to the entire surface of the substrate, and a metal film is formed over the second interlayer insulating film. 제1항에있어서, 상기 폴리실리콘막의 등방성 식각공정은 SF6, CF, NF3, O2혼합 GAS를 이용하여 수행되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the isotropic etching of the polysilicon film is performed using SF 6 , CF, NF 3 , and O 2 mixed GAS.
KR1019950036330A 1995-10-20 1995-10-20 Insulation method of semiconducor device KR0153493B1 (en)

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