JPH07147323A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the remaining material of an interconnection layer from forming a short circuit by a method wherein the interconnection layer on a substratum insulating layer is patterned, an interconnection in a desired pattern is formed and the material of the interconnection layer remaining outside an interconnection region is oxidized and transformed into an electric insulator. CONSTITUTION:An interconnection layer is formed of polysilicon on a field SiO2 oxide film 18 and a gate SiO2 oxide film 19 as substratum insulating layers, and interconnections 22, 24 in desired patterns are formed by an RIE method. In this case, the etching condition of the RIE method is adapted to the thickness T' of the interconnection layer. That is to say, the RIE method is executed under the etching condition where the cross section of an interconnection after an etching operation does not shape an overhang. Consequently, even after the RIE method has been executed, the polysilicon remains in a stringer shape outside the region of the interconnection region. In succession, the remaining polysilicon is oxidized and transform into SiO2, so that an electric insulator D is formed. Thereby, it is possible to prevent an electric short circuit from being formed between interconnections.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of forming a wiring having a desired pattern on an underlying insulating layer, and more specifically, a wiring layer material remaining on the underlying insulating layer after patterning. The present invention relates to a method for manufacturing a semiconductor device including a step of preventing a short circuit between wiring layers caused by the above.

[0002]

2. Description of the Related Art A wiring layer is not always formed only on a flat and planar ground insulating layer, and the ground insulating layer on which the wiring layer is formed often has uneven steps. . For example, a case where a gate material formed on a field oxide film (LOCOS oxide film), for example, a polysilicon film, is subjected to wiring processing by the RIE technique, which is performed in manufacturing a MOS type field effect transistor, will be described as an example. As shown in FIG. 2A, S is formed on the silicon substrate 12.
The iO ₂ oxide film 14 is formed by a thermal oxidation process (steam oxidation) or the like. Next, as shown in (b), SiO ₂
A silicon nitride film (Si ₃ N ₄ ) 16 is formed on the oxide film 14 by C
The silicon nitride film 16 is formed by the VD method or the like, and the silicon nitride film 16 is further etched by the photoresist method so as to expose the SiO ₂ oxide film 14 in the desired field region as shown in (c).

Next, as shown in (d), a thick field oxide film 18 is formed by the LOCOS method using the silicon nitride film 16 as a mask. Further, the silicon nitride film 16 is removed by etching, and then the wiring layer 20 is formed of polysilicon as shown in (e). Further, patterning is performed by reactive ion etching (RIE) to form a wiring having a desired pattern. Process (e)
3, the SiO ₂ oxide film 18 becomes thicker in the field region and the gate SiO ₂ oxide film 19 becomes thinner in the active region, as shown in FIG. A so-called bird's peak is formed and a step is formed on the surface.

[0004]

However, as described above, the base insulating layer 18 having a step by forming a bird's peak is formed.
When the wiring layer 20 is formed thereon, as shown in FIG. 3, the base insulating layer 18 forms a bird's peak to increase the layer thickness (the oxide film in the field region and the oxide film in the gate region). The thickness T of the wiring layer at the boundary portion is larger than the thickness T'of the wiring layer in the field region region where the underlying insulating layer is flat and the thickness T'of the wiring layer 20 on the gate region. It is speculated that this is probably due to the downward flow of the polysilicon deposit.

Therefore, when the wiring layer 20 is etched by the RIE method to form the wirings 22 and 24 having a desired pattern under the etching condition adapted to the thin wiring layer thickness T ', as shown in FIG. The wiring layer material, i.e., polysilicon A, remains in a long and slender stringer shape. Therefore, for example, an electrical short circuit is formed between the wiring 22 and the wiring 24, and the product semiconductor device becomes a defective product. On the other hand, if the etching time is extended or the isotropic etching is performed under the etching conditions adapted to the thick wiring layer thickness T, that is, under the condition that the stringer-like residual polysilicon is not generated, As shown by an arrow B in FIG. 4 or as shown in an enlarged view of FIG. 5A, the side surfaces of the wirings 22 and 24 in the flat portion are etched so that the cross-sectional shape of the wiring becomes an overhang-shaped reverse tapered shape. Become.

Once the lower layer wiring is formed in an overhang shape, the interlayer insulating layer 26 formed on the lower wiring is also formed in FIG.
As shown in (a), it is formed in an overhang shape.
Then, an upper wiring layer is formed thereon, and the wiring 2
When the wiring layer formed to form layers 8 and 29 is etched, as shown in FIG. 5B, the overhang portion of the interlayer insulating layer 26 hinders the etching, and polysilicon is more likely to remain in a stringer shape. Nari (Figure 5 (b) C
(See) and the wirings 28 and 29 are short-circuited. That is, R
The margin of the IE condition becomes poor. This tendency becomes stronger accordingly when a semiconductor device having a multilayer wiring structure is manufactured, and when etching the upper wiring layer,
The RIE condition becomes more and more severe. Therefore, when forming the wiring, it is required to prevent the wiring layer material from remaining on the underlying insulating layer when the wiring layer is etched. However, as described above, it is very difficult to solve this problem. Difficult

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device including a wiring forming step in which the remaining wiring layer material does not form a short circuit.

[0008]

[Means for Solving the Problems] The present inventor, after research,
It is practically very difficult to etch the wiring layer so that the wiring layer material does not remain on the underlying insulating layer, and it is conceived to solve the problem by converting the remaining wiring material into an electrical insulator.

In order to achieve the above object, based on such an idea, the present invention provides a wiring formed on a base insulating layer in a method of manufacturing a semiconductor device, which has a step of forming a wiring having a desired pattern on the base insulating layer. The method is characterized by including a step of patterning the layer to form a wiring having a desired pattern, and then oxidizing the wiring layer material remaining other than the formed wiring region to convert it into an electric insulator.

The method of the present invention can be applied to the manufacture of any semiconductor device as long as it uses a wiring layer material which is converted into an electrical insulator when oxidized. As the wiring layer material,
A typical example is polysilicon. The oxidizing method is not particularly limited, and examples thereof include a wet oxidizing method and a dry oxidizing method. The oxidation conditions are empirically or experimentally determined according to the thickness of the remaining wiring layer material. It is not necessary to oxidize all the remaining wiring layer material, and it is sufficient to oxidize the remaining wiring layer material to such an extent that a short circuit between wirings can be prevented. For example, in the case where the wiring layer material remains in a stringer shape as described above, the electrical short circuit disappears if the portion forming the intermediate portion of the stringer is oxidized, which is sufficient.

[0011]

In the present invention, the wiring layer material remaining in areas other than the wiring area of the desired pattern is oxidized and converted into an electrical insulator, so that a short circuit between wiring layers due to the remaining wiring layer material can be prevented.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One of the embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a schematic perspective view showing a state after carrying out the method of the present invention. In carrying out the method of the present invention, the steps up to the step shown in FIG. 2E are the same as the conventional steps, and polysilicon is formed on the field SiO ₂ oxide film 18 and the gate SiO ₂ oxide film 19 which are underlying insulating layers. Then, a wiring layer is formed, and then wirings 22 and 24 having a desired pattern are formed by the RIE method as shown in FIG. In this case, the etching conditions of the RIE method are adjusted to the wiring layer thickness T'shown in FIG. That is, the RIE method is performed under the etching conditions such that the wiring cross section after etching does not have an overhang shape. Therefore, even after applying the RIE method,
Polysilicon remains in a stringer shape other than the wiring region (see A in FIG. 4). Subsequently, the remaining polysilicon is oxidized and converted into SiO ₂ to be an electric insulator (indicated by D in FIG. 1).

Experimental Example The method of the present invention was carried out by using a sample in which the polysilicon remained in a stringer shape with a thickness of about 1000 Å, and was used as an experimental example. In the experimental example, oxidation was performed by the steam oxidation method. The temperature is about 1000 ° C and the ratio of H ₂ and O ₂ is H ₂ : O.
_Under the oxidation condition of ₂ = 1: 1, the remaining polysilicon could be changed to SiO ₂ in the oxidation time of about 15 minutes. In the short-circuit test performed thereafter, it was confirmed that there was no electrical short circuit between the wiring 22 and the wiring 24.

[0014]

According to the present invention, the wiring layer formed on the underlying insulating layer is patterned to form a wiring having a desired pattern, and then the wiring layer material remaining outside the formed wiring region is oxidized to electrically insulate. Convert to the body. This can reliably prevent the formation of an electrical short circuit between the wirings. Therefore, by applying the present invention, it is possible to prevent the occurrence of a semiconductor device having a poor insulation, improve the product yield, and provide a semiconductor device having high electrical insulation between wirings. Further, when the method of the present invention is applied, the wiring cross section in the flat portion can be processed into a forward tapered shape, so that the wiring processing margin in the upper layer becomes large and the work in the subsequent process becomes easier accordingly. Further, if the present invention is applied to the upper layers one after another, a more complete semiconductor device can be provided.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing a state in which stringer-like remaining polysilicon is converted into an electrical insulator.

FIG. 2A to FIG. 2E are diagrams showing a process of forming a wiring of a desired pattern on an insulating layer.

FIG. 3 is a cross-sectional view showing a difference in thickness of a wiring layer at a bird's peak portion.

FIG. 4 is a schematic perspective view showing a state in which the wiring layer material remains in a stringer shape in the step portion.

5 (a) is an explanatory view showing a wiring cross section etched in an overhang shape, and FIG. 5 (b) shows etching conditions when an upper layer wiring is formed on the wiring etched in an overhang shape. It is a perspective view explaining that a margin is insufficient.

[Explanation of symbols]

12 silicon substrate 14 SiO ₂ oxide film 16 silicon nitride film 18 field oxide film 19 gate oxide film 20 wiring layer 22, 24, 28, 29 wiring 26 interlayer insulating layer

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a step of forming a wiring having a desired pattern on a base insulating layer, wherein the wiring layer formed on the base insulating layer is patterned to form a wiring having a desired pattern, A method of manufacturing a semiconductor device, comprising the step of oxidizing a wiring layer material remaining in a region other than the formed wiring region to convert it into an electric insulator.