KR0150789B1 - Nonvolatile semiconductor memory device - Google Patents

Abstract

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Description

Nonvolatile Semiconductor Memory

1 is an explanatory diagram schematically showing a cross section and a circuit connection state of a memory cell of an EEPROM according to an embodiment of the present invention.

2 is a plan view of a semiconductor substrate showing a memory cell array of EEPROM.

3 is an explanatory diagram showing a circuit connection state when emitting electrons from a floating gate.

4 is an explanatory diagram showing a rotation connection state when electrons are injected into the floating gate.

5 to 7 show circuit diagrams and operating voltages for explaining the principles of the present invention.

8 shows energy bands in the present invention and conventional example.

9 is an internal block diagram of a nonvolatile semiconductor memory device of another embodiment.

10 is a plan view of 4 bits of a FAST type memory cell used in another embodiment.

FIG. 11 is a cross-sectional view of the A-A 'line of FIG. 10 (for 2 bits).

FIG. 12 is a cross-sectional view of the A-A 'line of FIG. 10 (for 2 bits).

13 is a circuit configuration diagram of an erase voltage application circuit ED of another embodiment.

14 is a circuit diagram of a negative voltage applying circuit NEG of an embodiment in which a negative voltage is applied to a control gate in an erase operation.

Fig. 15 is a characteristic diagram showing the effect of improving program disturb resistance in another embodiment.

16 is a circuit diagram of an XDCRN with another negative voltage application call.

FIG. 17 is a configuration diagram of a word line reset circuit that resets a negative voltage applied by XDCRN of FIG.

FIG. 18 is a sectional view of a multiple well structure for realizing the XDCRN of FIG.

FIG. 19 is a cross-sectional view (two lines A-A 'in FIG. 10) of a FAST type memory cell used in another embodiment.

20 is an internal block diagram of a nonvolatile semiconductor memory device of another embodiment.

21 is a circuit diagram of a negative voltage application circuit NEG of the embodiment of FIG.

FIG. 22 is a circuit diagram of the address buffer circuit ADB of the embodiment of FIG. 20; FIG.

23 is an internal block diagram of a nonvolatile semiconductor memory device of another embodiment.

24 is a circuit diagram of the negative voltage application circuit NEG of the embodiment of FIG.

FIG. 25 is a cross-sectional view (two lines A-A 'in FIG. 10) of a FAST memory cell used in the embodiment of FIG.

26 and 27 are block diagrams of a semiconductor memory device for explaining the principle of the present invention.

28 is a cross sectional view of a semiconductor element constituting a memory cell;

FIG. 29 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

30, 32 to 35, 38, 39, 41, and 42 are partial circuit diagrams of the semiconductor memory device of the embodiment of the present invention.

FIG. 31 is an explanatory diagram showing a relationship between an operation mode and an external signal of the apparatus of the embodiment of the present invention; FIG.

36 is an operation timing diagram of the semiconductor memory device of the embodiment of the present invention.

43 is a graph showing the relationship between the number of memory elements in a memory block and the instability of the threshold value after erasing in the semiconductor memory device of the embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a technology effective by applying to an electrically erasable nonvolatile memory (hereinafter, referred to as EEPROM).

As nonvolatile semiconductor memory devices, erasable and programmable read only memories (EPROMs) and electrically erasable EEPROMs have been conventionally used for program and data storage.

The EEPROM has a problem that the memory cell area is suitable for ego-capacity, but requires a package having a window for erasing by ultraviolet irradiation, and needs to be removed from the system at the time of writing to execute writing by a program. There is.

On the other hand, the EEPROM can be electrically rewritten in the system, but the memory cell area is about 1.5 to 2 times larger than the EEPROM, which is not suitable for large capacity.

As for such EEPROM, for example, the daily publication of Industrial Newspaper Co., Ltd., Electronic Technology, June 1988, pp. 122-127, the structure of a floating-gate tunnel oxide (FLOTOX) type EEPROM cell, the mechanism of injection of electrons into the floating gate, and the emission of electrons from the floating gate are described in detail.

The FLOTOX type EEPROM cell is a memory cell of a two-layered gate structure in which a floating gate for retaining electrons is provided in the lower layer of the jezer gate, and a region of a very thin insulating film (tunnel region) formed in a part of the insulating film between the floating gate and the drain region. A tunnel current, called a FN (Fowlor-Nordheim) current, is made to flow therethrough to inject electrons into the floating gate or discharge electrons from the floating gate.

In the memory cell of the FLOTOX type EEPROM, the electrons held in the floating gate are discharged by, for example, applying a GND voltage (Ov) to the control gate and applying a high voltage of 15V to 20V to the drain electrode. It was.

Recently, as an intermediate storage device between the EPROM and the EEPROM, an electric batch erasing (flash) EEPROM has been developed. This flash EEPROM is a nonvolatile semiconductor memory device having a function of electrically erasing a batch of chips or a batch of memory cells collectively, and the memory cell area can realize a value of about EPRON.

As the above-described flasher EEPROM, for example, the memory device disclosed in Japanese Patent Laid-Open No. 62-276878 is representative.

Hereinafter, the memory cell of the flash EEPROM is referred to as Floating Gate Asynmetric Source and Drain Tunnel Oxide (FAST) type.

The FAST type memory cell has a floating gate type deployment effect transistor structure similar to that of the EPROM FAMOS type, and is excellent in high integration since one bit (one memory cell) can be composed of one element.

As with FAMOS, writing is performed by injecting hot electrons generated near the drain junction into the floating gate electrode. By the write, the threshold voltage seen from the control gate electrode of the memory cell becomes high.

On the other hand, erasing generates a high electric field between the floating gate electrode and the source by grounding the control gate electrode and applying a positive high voltage to the source, and electrons accumulated in the floating gate electrode using a tunnel phenomenon passing through the thin gate oxide film. By extracting it to the source. The erasing lowers the threshold voltage seen by the control gate electrode. At this time, since the memory cell does not have the selection transistor, the negative threshold voltage (and the erase state) becomes a fatal failure.

In addition, the read applies a low voltage of about 1V to the drain, and a voltage of about SV to the control gate electrode, and executes using the magnitude of the channel current flowing at this time corresponding to 0 and 1 of the information. The low drain voltage is used to prevent parasitic weak write operation.

In the above FAST type memory cell, since the write is performed on the drain side and the erase side on the source side, it is desirable to individually optimize the voltage profile for each operation. In the prior art, a source-drain asymmetric structure is used. In the drain junction, an electric field concentrated profile for increasing the light efficiency is used, and in the source junction, an electric field relaxed profile in which a high voltage is applied is used.

Further, in a memory cell in which electrons are extracted from a floating gate electrode in a tunnel and erased, how to reduce the positive capacitance coupling between the region to which the erase voltage is applied (here, the source region) and the floating gate electrode is miniaturized and erased. This is an important point for achieving low voltage reduction. In the FAST type memory cell, the value is reduced by forming the overlapping region of the floating gate electrode and the source, which determines the capacitive coupling, by self-alignment by diffusion of the source.

In addition, the following are examples of the pro-collective erase memory other than the above-described prior art.

First, VN Kynett et al. Presented the paper at the 1989 International Solid-State Circuit Conference hosted by IEEE. In 140-141, a 1 Mb flash EEPROM of a chip batch erase type using a memory cell having the same principle as the above FAST type is disclosed. The memory cell area is 15. 2 mu m ² (design rule 1.0 mu m), the operating voltage for writing and erasing is 12 V, and low-voltage operation in a fine cell is realized. In this device, however, the rewrite requires an external power supply of Vcc (5V) and Vpp (12V). This is because the on-chip step-up power supply cannot be used because the current consumption during rewrite operation is large as described below.

In addition, S. D Arrigo et al. Similarly, 132-133 discloses a chip-uninstalled 256K bit Flash EEPROM. This device uses a so-called FLOTOX type memory cell to realize a 5V single power supply operation by an on-chip boost power supply. Namely, (1) the tunnel phenomenon of the battery is also used for light in addition to erasing, and (2) the thin region of the gate oxide film used in the tunnel is limited on the drain high concentration diffusion layer, thereby reducing the current consumption of the rewrite operation. Reduction is possible. Another feature of this memory is that a negative voltage is applied to the control gate in an erase operation. As a result, the voltage applied to the drain diffusion layer is reduced to about 5V to increase the margin for the junction breakdown voltage. In this device, however, the tunnel region is not self-aligned, and a selection transistor called a pass gate is included in the cell, which is inferior to the FAST type in terms of cell fineness and low voltage operation.

The present inventors have found that the above-mentioned problems occur in the electron emission of the memory cell of the FLOTOX type EEPROM.

That is, a high voltage is applied to an n ⁺ diffusion layer or an n ⁺ / P junction portion forming a drain region in order to apply a high voltage to the drain electrode when electrons are emitted from the floating gate, resulting in a decrease in the memory cell of the EEPROM.

For this reason, conventionally, the memory cell of the EEPROM has a high breakdown voltage structure, but the structure of the high breakdown voltage of the memory cell of the EEPROM prevents the miniaturization and increases the area of the semiconductor chip.

As described above, the FAST type memory cell is a promising device having various advantages, but has a problem as described below.

The first problem is that parasitic leakage current flows from the source to the semiconductor substrate when performing the erase operation. This is a leak current peculiar to the FAST type memory cell due to the thinning of the gate oxide film over the entire floating gate electrode. That is, when a high electric field (about 10 MV / cm) necessary for the erase operation is applied to the gate oxide film, electron and hole pairs due to the interband tunnel are generated on the source region surface below it. Since this hole cannot be prevented from flowing out to the substrate side, a large leak current flows. Further, in the FLOTOX type memory cell, since the gate oxide film is thickened at the end of the high concentration diffusion layer, holes do not flow out to the substrate side, and no leak current is generated.

The presence of the leak current requires an external power source for erasing action in addition to the Vcc power source (normally SV power supply) for read operation supplied outside the chip in order to increase the current consumption of the chip collective consumption operation.

The second problem is that repeated rewriting significantly lowers the resistance to the program disk, making it difficult to secure the reliability of the array operation. The program display is a phenomenon in which the threshold voltage of the memory cell is changed in the word line half-selected state in which the write high voltage is applied only to the zener gate electrode of the memory cell.

G, Vema et al., IEEE State, 1988 Int. Reliability Physics Symposium, pp. 158-166 report a decrease in the resistance of the program disturb. According to this, a positive trap charge is formed in the gate oxide film by the erasing operation, which causes the tunnel injection of electrons that causes the program disturb. Positive trap charge formation is considered to be due to the fact that the holes generated in the interband tunnel during the erasing operation are energized in the high electric field between the substrates of the source to become enthusiastic holes, which are very small but are injected and trapped in the gate oxide film.

The degradation of the program disturb resistance is a more severe constraint when the memory array is divided into several blocks in a direction orthogonal to the word lines, and the rewrite operation is performed for each block. When the block division is not taken into consideration, the time when the memory cells are exposed to the program disturb may be a total time for writing to the memory cells other than the same word line once. On the other hand, in consideration of the above-mentioned block division, this time is lengthened by approximately the number of times of rewrite when rewriting of another block is repeated after writing to a block.

The third problem is that in principle, it is impossible to perform the erase operation in units of bit lines. Since the FAST type memory cell is a single predetermined memory cell having no switch MOS, when a high voltage of erasing is applied to the source line, all of the memory cells connected to the source line are erased at the same time. Even if the source line is uncoded, block erasing in units of the source line can be performed.

20 is a schematic diagram of the cross-sectional structure of the FAST memory cell. As described above, this memory element has a structure of 1 element / bit floating gate type field effect transistor similar to the EPROM FAMOS type memory element, and is excellent in high integration.

As described above, the writing is performed by injecting the heat carrier generated near the drain 1 into the floating gate 2 as in the EPROM. By the write, the threshold seen from the control gate 4 of the memory cell becomes high. On the other hand, erasing is a tunnel phenomenon in which the high voltage is generated between the floating gate 2 and the source 3 by passing the thin oxide film 5 by grounding the control gate 4 and applying a high voltage to the source 3. Is carried out by extracting the electrons accumulated in the floating gate 2 into the source 3 using. By the erase, the threshold seen by the control gate 4 becomes low. The lead applies a low voltage of about 1V to the drain 1 so that a weak light rarely occurs, and applies a voltage of about 5V to the control gate 4 so that the magnitude of the channel current flowing corresponds to 0 and 1 of the information. In the figure, (6) is a p-type silicon substrate, (7) is an n-type diffusion layer, (8) is a low concentration n-type diffusion layer, and (9) is a p-type diffusion layer.

In addition, as described above, in the memory element which performs the erase operation by the electron tunnel, how to suppress the capacitance coupling between the region to which the scavenging voltage is applied (here, the source region) and the floating gate electrode can be miniaturized and erased. It becomes a point to make the voltage reduction of a compatible. In the FAST type memory device, the gate oxide film of the floating gate electrode mill is thinned entirely (as a tunnel oxide film), and the self-alignment is formed by spreading and surrounding the overlapping portion of the floating gate electrode and the source region with the back region. As a result, the tunnel area of the electrons can be refined to a limit, thereby reducing the capacitive coupling.

In the flash EEPROM using the conventional FAST type memory device, securing controllability of the one-state threshold voltage (threshold voltage low level) realized by the electrical batch erase operation is an important problem. This is because even if the threshold voltage is too high or too low after erasing, it becomes defective in subsequent read operations.

If the threshold voltage is too high after erasing, the current required for one read is insufficient, so that the lower limit of the read power supply voltage or the read speed occurs. That is to say, it should be obvious that the erase operation should not be insufficient.

On the other hand, when the threshold voltage becomes low after erasing, the current flows to the memory element in which the word line is not selected at the time of read, so that the read in the zero state where the current does not flow is impossible. Since the FAST type memory device does not have a selection transistor, it is impossible to perform excessive erase.

As a result, in a flash EEPROM using a FAST type memory device, in order to simultaneously erase a plurality of memory devices by applying an erase voltage to a common source line, there is nothing unstable in the erase characteristics of each memory device, or at least the instability is not. Small suppression is an important precondition.

However, the reality is that when the batch erase operation is performed at the LSI level due to various factors such as the instability of the device structure or the instability of the tunnel oxide film characteristics, there is a great instability between the erase characteristics. It is.

It is a first object of the present invention to provide a highly reliable nonvolatile semiconductor memory device.

It is a second object of the present invention to provide a small nonvolatile semiconductor memory device.

It is a third object of the present invention to provide a nonvolatile semiconductor memory device using the FAST type memory cell that does not require a dedicated external power supply for an erase operation.

A fourth object of the present invention is to provide a nonvolatile semiconductor memory device using the FAST type memory cell, which is hardly affected by program disturb and which is easy to realize electrical erase in block units. .

A fifth object of the present invention is to provide a nonvolatile semiconductor memory device using the FAST type memory, which can perform an erase operation in units of bits.

A sixth object of the present invention is to provide a nonvolatile semiconductor memory device using the FAST type memory cell that can also perform an erase operation with a single power supply (for example, a 5V power supply) used for read operation and write operation.

A seventh object of the present invention is a nonvolatile semiconductor memory device using the FAST type memory element, which is capable of suppressing the instability of the threshold voltage after scavenging sufficiently small even if there is a large instability between the erase characteristics of the memory element that performs the batch erase operation. A nonvolatile semiconductor memory device is provided.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Brief descriptions of representative ones of the inventions disclosed in the present application are as follows.

That is, a negative voltage is generated for applying a negative voltage to the control gate of the MOSFET in a nonvolatile semiconductor memory device having an electrically erasable nonvolatile memory cell constituted by a MOSFET having a two-layer gate structure including floating gate and control gate. A low voltage generation circuit is provided for applying a low voltage to the circuit and the drain electrode of the MOSFET. This makes it possible to achieve the first and second objects described above. In other words, the potential of the voltage applied to the control gate when the electrons are emitted from the floating gate is lowered than the conventional GND potential. Therefore, even if the potential of the voltage applied to the drain electrode is lowered as much as the potential of the voltage applied to the control gate is lowered than before, the potential difference necessary for electron emission can be secured between the floating gate and the drain electrode. That is, since the voltage applied to the drain electrode at the time of electron emission from the floating gate can be stepped down, the degradation of the memory cell of the EEPROM can be prevented.

In addition, since the voltage applied to the drain electrode is lowered than before, the memory cell of the EEPROM does not need to have a high withstand voltage structure, and thus the memory cell can be made smaller and the nonvolatile semiconductor memory device can be miniaturized.

In addition, in order to achieve the above-mentioned third and sixth objects, the voltage applied to the source region (or drain region) of each memory cell when the batch erasing operation is performed in the nonvolatile semiconductor memory device using the FAST type memory cell is performed. It is supplied from the Vcc power supply of the memory device (usually supplied from outside the chip, which is usually used for read operation, hereinafter same), and at the same time, an erase voltage having a polarity opposite to that of the Vcc power supply is applied to the control gate electrode of each memory cell. And the erase voltage is supplied by a voltage conversion circuit (step-up circuit) in the nonvolatile semiconductor memory device. The value of the erase voltage of the opposite polarity is a value determined by the structural constant and characteristics of the memory cell, but is, for example, about Vcc to 2Vcc.

The fourth object is then realized by using a means for achieving the third and sixth objects and simultaneously performing block division in the word line direction so that memory cells connected to the same word line belong to the same block.

The fifth object is then decoded from the source line (or data line) and the word line to which the erase voltage is applied in the means for achieving the third and sixth objects, and the selected pair of source line (or data line) and the word line. It is executed by causing the erase operation to be executed only in the memory cells at the intersections.

Next, a circuit diagram of an example of the operation of the memory array corresponding to the means for achieving the third to sixth objects and the operating voltages of the respective parts are shown in FIGS.

In this example, the memory array M-ARRAY is formed of FAST type memory cells (n-channels) M1 to M9 arranged in three rows and three columns, and is operated through word lines W1 to W3, data lines D1 to D3, and a common source line CS. Run

First, FIG. 5 shows a case where the erase operation is collectively executed as a whole of the memory array M-ARRAY.

In this case, a negative erase voltage of -7V is applied to all word lines W1 to W3, and a positive erase voltage of ⁺ 5V is applied to the common source line CS. ⁺ 5V of the common source line CS is supplied from the Vcc power supply outside the device, and -7V of the word line is supplied from the voltage conversion circuit inside the device. At this time, the substrate and the data line are at the ground potential. In addition, the write and read operations are performed by decoding the data lines and word lines by selecting the memory cells at the intersection points as in the conventional two power supply type chip erase type flash EEPROM.

Next, FIG. 6 shows a case where the erase operation is performed by treating the memory cell groups MB1, MB2, and MB3 connected to the same word line as a batch of memory blocks, as shown by dotted lines in the figure. In other words, the group of memory cells connected to the same word line is selectively erased.

In this case, the memory block to be erased is selected by decoding the word line to which the negative erase voltage of -7V is applied. Other than that is the same as that of FIG.

Next, Fig. 7 shows a case where an erase operation is performed by selecting any one bit in the memory array M-ARRAY.

In this case, the word line applying the negative erase voltage of -7V is decoded and the positive erase voltage of 5V is applied from the data line, and the erase operation is selectively performed in the memory cell at the intersection of the selected word line and the data line by decoding the word line. Is executed. At this time, the substrate and the common source line are the ground potential.

Also, the write is executed by applying a write voltage to the common source line and the select word line and grounding the select data line. Hot electron injection takes place from the source region side in the memory cell at the intersection, so that the write operation is realized. At this time, the unselected data lines are separated from each other in an open state, and the unselected word lines are set to the ground potential. The read operation is performed by decoding the data lines and word lines by selecting the memory cells at the crossing points, similarly to the conventional two-power chip erasure type flash EEPROM.

By the means described above, the desired purpose is realized.

First, a Vcc power source is applied to a source region or a train region of each memory cell, and an erase voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. It is configured to supply and the operation is as follows.

That is, when performing a batch erase operation in a nonvolatile semiconductor memory device using a FAST type memory cell, a source region through which a large leak current (for example, 1 M bits to several 10 mA) flows is directly driven by a Vcc power supply. At this time, in order to prevent the decrease of the erase speed, it is necessary to apply the erase voltage of the opposite polarity to the Vcc voltage to the control gate electrode, but to the same electrode, a minute tunnel current (for example, about 10 mA at 1 Mb) that directly contributes to the erase. ), It can be driven by a voltage conversion circuit (step-up circuit) provided in the nonvolatile semiconductor memory device. In this way, the chip batch erase operation by the Vcc single power supply can be realized without sacrificing the erase speed.

Next, in addition to the above configuration, memory cells connected to the same word line are configured to execute block division in the word line direction so as to belong to the same block.

That is, since the erase voltage applied to the source region of the memory cell is reduced from the conventional Vpp voltage (for example, about 12V) to the Vcc voltage (for example, about 5V), the inter-band tunnel as shown in FIG. The hole generated in the hole becomes an electric passion hole between the source and the substrate, and the phenomenon of being injected and trapped in the gate oxide film can be significantly suppressed. In addition, since the memory cells connected to the same word line are always rewritten, the program disturb time experienced by each cell should be considered in consideration of the time required for writing the other memory cells on the same word line. Depending on the number of times, the increase in the disturb time is solved. In this manner, a nonvolatile semiconductor memory device excellent in program disturb resistance and capable of electric erasing on a block-by-block basis is realized.

Next, when the source line or data line to which the erase voltage is applied and the word line are decoded, and the erase operation is performed only in the memory cell where the selected pair of source or data lines are at the intersections of the word lines, the erase voltages having different polarities are different. By erasing the applied source line or data line and word line respectively, the erase operation can be selectively performed in the memory cells at the intersections. At this time, since the tunneling phenomenon of electrons which dominates the era strongly depends on the development strength of the oxide film, the erasure can be substantially prevented in the half-selected memory cell in which only one of the data line and the word line is selected.

The seventh object is realized by individually controlling the actual end point of the batch erase operation for each memory element or for a combination of several memory elements in accordance with the erase speed of each memory element. Specifically, as shown in FIG. 26, it is realized by combining the following means.

First, the memory array M-ARRAY is divided into the above blocks (MB1 to MB4 in FIG. 26), and each block is at least one memory element, and means for independently performing electric erasing for each block (ED1 to FIG. ED4).

Second, prior to the electrical erasing, each block is provided with means for determining whether the threshold voltage of all the memory elements in the block is low so that it is not necessary to erase or if there is any element having a high threshold voltage (lead device SA in the drawing). do.

Third, when the threshold voltages of all the memory elements in the block are low and need not be erased, a means for preventing the application of the erase voltage is provided so as not to perform the erase operation of the batch erase. That is, a function of determining whether or not the erase voltage is applied to the MD1 to the MD4 is applied.

Finally, the batch erasing ends when the necessary erase operation is performed for all the memory elements targeted. This may be determined inside the apparatus or may be determined by an external control apparatus.

FIG. 26 illustrates a case where one read device SA is included in a memory array (M-ARRAY). However, in general, the memory array and the read device SA total 8 sets so that reads and writes can be performed in units of 8 bits or 16 bits. Or 16 sets. In the case of Article 8, it is set as the structure shown in FIG.

Incidentally, in Fig. 26, the erasing of the entire memory array M-ARRAY is simulated, but a partial collection of only a part of them may be removed. That is, when the blocks MB1 and MB2 are erased at the same time, the blocks MB1 and MB2 constitute the blocks.

As a result, the batch erase operation as a chip is continued until the end of the last erased among all the memory elements to be processed is completed. However, if each erased block is noticed, the actual erase operation is further performed for the memory elements that have been erased to the required level. There is nothing to be done. As a result, even if there is an unstable relationship between the erase characteristics of the memory elements to be subjected to the batch erase, the threshold voltage after the end of erase can be adjusted to the desired value with precision.

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated with an Example.

1 is an explanatory view showing a cross section and a circuit connection state of a memory cell of an EEPROM according to an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor substrate showing a memory cell array of this EEPROM, and FIG. 3 is a floating gate. 4 is an explanatory view showing a circuit connection state when electrons are injected into the floating gate.

The nonvolatile semiconductor memory device of this embodiment is a FLOTOX type EEPROM.

Hereinafter, the planar configuration of the memory cell array of the EEPROM of the present embodiment will be described with reference to FIG. In addition, in FIG. 2, illustration of insulating films other than a field insulating film is abbreviate | omitted in order to simplify description.

For example, a semiconductor substrate (hereinafter referred to as a substrate) 1, which is a p-type silicon (Si) single crystal, has a source region 2 and a drain region 3, for example, an n ⁺ type diffusion layer. It is arrange | positioned facing every cell Qm.

The train region 3 is disadvantaged for each memory cell Qm of the EEP ROM via an island-like field insulating film 4 made of SiO ₂ or the like.

Between the source region 2 and the drain region 3 of the memory cell Qm of each EEPROM, a floating gate 5 and a control gate 6 are formed in descending order, and these two gates and the source region 2 are formed. And the drain region 3 constitute a MOSFET having a two-layer gate structure.

The floating gate 5 is a gate for holding electrons, and is formed in each of the memory cells Qm serving as a polysilicon (polycrystalline Si) layer, for example.

The control gate 6 is a control gate that emits electrons from the floating gate 5 or injects electrons into the floating gate 5, for example, a polysilicon layer similar to the floating gate 5. Is shared by the memory cells Qm arranged in the left and right directions of the word lines WL. And all of the memory cells Qm connected to one word line WL have their source region 2 shared.

In the upper layer of the control gate 6 which also serves as the word line WL, a data line DL extending in a direction perpendicular to the direction in which the word line WL extends is formed. The data line DL is, for example, an aluminum (Al) layer and is electrically connected to the respective drain regions 3 via the connection hole 7. The two memory cells Qm lined side by side along the direction in which the data line DL extends are arranged such that their drain regions 3 are shared and are mirrored with respect to the drain region 3.

FIG. 1 is an explanatory diagram schematically showing a cross-sectional view of the memory cell along the line I-I of FIG. 2 and a connection state between each circuit formed in the substrate and each electrode of the memory cell.

On the substrate 1, a gate insulating film 8 made of SiO ₂ or the like is formed. In the gate insulating film 8, a thin tunnel region Sa is formed at each portion of the gate insulating film 8 that is different in thickness from the insulating film.

The floating gate 5 described above is formed on the upper surface of the gate insulating film 8. The emission of electrons from the floating gate 5 and the injection of electrons into the floating gate 5 are performed through the tunnel region 8a of the gate insulating film 8.

An insulating film 9 made of SiO ₂ or the like is formed on the upper surface of the floating gate 5, and the control gate 6 described above is formed on the upper surface.

Meanwhile, in the present embodiment, the negative voltage generating circuit 10, the high voltage generating circuit 11, the low voltage generating circuit 12, and the GND power supply voltage circuit are formed in the element formation region except for the region where the memory cell array is formed on the substrate 1. 13) and switching circuit 114 are formed.

The negative voltage generating circuit 10 is a circuit for applying a negative voltage to the control gate 6 when emitting the electrons from the floating gate 5.

The high voltage generation circuit 11 is a circuit for applying a high voltage to the control gate 6 when injecting electrons into the floating gate 5.

The low voltage generation circuit 12 is a circuit for applying a low voltage to the drain electrode 3a when electrons are emitted from the floating gate 5.

In addition, the high voltage generating circuit 11 and the low voltage generating circuit 12 may be configured as one circuit so that the low voltage and the high voltage can be output properly.

The GND power supply voltage circuit 13 is a circuit for applying the GND voltage to the drain electrode 3a when supplying the GND potential (ground potential of the circuit) to each electrode and injecting electrons into the floating gate 5.

The switching circuit 14 is a circuit for switching the connection state between each of the circuits 10 to 13, the drain electrode 3a, and the control gate 6 in accordance with the injection and release of electrons.

Next, the data erasing method and the writing method in the EEPROM will be described with reference to FIG. 3 and FIG.

In the present embodiment, for example, the emission of electrons from the floating gate is erased of data, and the injection of electrons into the floating gate is written of data.

First, in order to erase data (emitting electrons from the floating gate), as shown in FIG. 3, the output terminal of the negative voltage generating circuit 10 is electrically connected to the control gate 6 via the switching circuit 14. The output terminal of the low voltage generation circuit 12 is electrically connected to the train electrode 3A via the switching circuit 14.

For example, if a potential difference of about 15V is required between the control gate 6 and the drain electrode 3A for data erasing, the negative voltage generating circuit 10 may control the control gate 6 by, for example, about -8V. A negative voltage is applied, and a positive low voltage of, for example, about 7V is applied to the drain electrode 3a in the low voltage generation circuit 12.

In this case, since the potential difference (| -8 | + 7 = 15V) necessary for emitting electrons from the floating gate 5 is secured between the control gate 6 and the drain electrode 3a, the floating gate 5 is maintained. Existing electrons are released to the drain region 3 via the tunnel region 8a, and data is erased.

That is, in the EEPROM of the present embodiment, a voltage applied to the drain electrode 3A by applying a negative voltage to the control gate 6 when erasing data (emission of electrons from the floating gate 5) is more than conventional. For example, 8 to 13 volts can be lowered.

In addition, in order to write data (injecting electrons), as shown in FIG. 4, the output terminal of the high voltage generating circuit 11 is electrically connected to the control gate 6 via the switching circuit 14, and further, GND. The output terminal of the power supply voltage circuit 13 is electrically connected to the drain electrode 3a via the switching circuit 14. In the high voltage generating circuit 11, a high voltage of 15 to 20 V is applied to the control gate 6, and a GND voltage (0 V) is applied to the drain electrode 3a in the GND power supply voltage circuit 13. Electrons are injected from the drain region 3 through the tunnel region 8a to the floating gate 5 to write data.

As described above, according to the present exemplary embodiment, when the negative voltage generation circuit 10 is formed in the element formation region other than the region where the memory cell Qm is formed in the substrate 1, data is erased (emission of electrons from the floating gate 5). By applying the negative voltage generated by the negative voltage generating circuit 10 to the control gate 6, the potential of the voltage applied to the control gate 6 at this time is lower than that of the conventional one, and thus the voltage applied to the drain electrode 3a. Even if the potential of is lowered than before, the potential difference required for the emission of electrons between the floating gate 5 and the drain electrode 3a can be ensured.

Therefore, the voltage applied to the n ⁺ diffusion layer or the n ⁺ / p junction portion forming the drain region 3 during data erasing (emission of electrons from the floating gate 5) can be lowered than before, so that the reliability of the EEPROM can be reduced. It will be possible to improve.

In addition, since the voltage applied to the drain region 3 can be lowered than before, the memory cell Qm does not need to have a high breakdown voltage structure. As a result, the memory cell Qm can be miniaturized and the EEPROM can be miniaturized.

In the above embodiment, the case where a high voltage is applied to the control gate when electrons are injected into the floating gate has been described, but the present invention is not limited thereto. For example, the negative voltage is drained by the negative voltage generation circuit when electrons are injected into the floating gate. The low voltage may be applied to the control gate in the low voltage generation circuit. In this case, no high voltage generation circuit is required.

Another embodiment of the present invention will be described using FIGS. 9 to 10.

FIG. 9 is an internal block diagram of the nonvolatile semiconductor memory device according to the present embodiment, FIG. 10 is a plan view showing four bits of the FAST type memory cell used in this embodiment, and FIG. 11 is a sectional view taken along the line AA ′ of the plan view of FIG. (2 bits), FIG. 12 is a sectional view (2 bits) of the BB 'portion of the plan view of FIG. 10, FIG. 13 is a circuit configuration diagram of an erase voltage application circuit ED, and FIG. Circuit diagram of the negative voltage application circuit NEG, FIG. 15 is a characteristic diagram showing the effect of improving program disturb resistance in the present embodiment, FIG. 16 is a circuit configuration diagram of another negative voltage application circuit XDCRN, and FIG. Fig. 18 is a cross sectional view of a multi-well structure for realizing the XDCRN, in which the word line reset circuit resets the negative voltage applied by the XDCRN.

The circuit element of this embodiment is not particularly limited, but is formed on a semiconductor substrate such as one single crystal silicon by a known manufacturing technique of a CMOS (complementary MOS) integrated circuit. In addition, although not particularly limited, an integrated circuit is formed on a semiconductor substrate made of single crystal p-type silicon.

The n-channel MOSFET is a gate electrode such as polysilicon formed through a gate insulating film such as polysilicon formed through a thin gate insulating film on a source region, a drain region and a channel between the source region and the drain region formed on the surface of the semiconductor substrate as described above. It consists of.

The p-channel MOSFET is formed in an n-type well region formed on the surface of the wing semiconductor substrate. As a result, the semiconductor substrate constitutes a common substrate gate of several n-channel MOSFETs formed thereon, and the ground potential of the circuit is supplied. The common substrate gate of the P-channel MOSFET, that is, the n-type well region, is connected to the power supply voltage Vcc.

The integrated circuit may be formed on a semiconductor substrate made of single crystal n-type silicon. In this case, the n-channel MOSFET is formed in the p-type well region.

The memory cell of this embodiment is not particularly limited but is formed on the p-type semiconductor substrate. Fig. 10 shows the planar structure for 4 bits, Fig. 11 shows the cross-sectional structure of the A-A 'portion, and Fig. 12 shows the cross-sectional structure of the B-B' portion.

In Figs. 10 to 12, reference numeral 21 denotes a p-type semiconductor substrate, 22 denotes a thin gate oxide film (tunnel oxide film) formed on the main surface side of the p-type semiconductor substrate, 23 denotes a floating gate electrode, and 24 denotes a The first interlayer oxide film, 25 is a control gate electrode, 26 is an n ⁺ type semiconductor region (drain region), 27 is a P ⁺ type semiconductor region (drain shield layer), and 28 is an n ⁺ type The semiconductor region (part of the source region), 29 is an n-type semiconductor region (part of the source region), 30 is a second interlayer insulating film, 31 is a connection hole, 32 is an aluminum data line, Denoted at 33 is a field oxide film for device isolation by the LOCOS method, 34 is a channel stopper for preventing parasitic channels from forming a p ⁺ type semiconductor region, and 35 is a boundary line between the device isolation region and the active region by the LOCOS method. .

The gate oxide film 22 is a silicon oxide film formed by thermally oxidizing the surface of the semiconductor substrate 21, and the film thickness thereof is about 10 nm.

The first interlayer insulating film 24 is a silicon oxide film formed by thermally oxidizing the surface of the floating gate electrode 23 to be a polycrystalline silicon film, and the film thickness thereof is about 20 nm.

The control gate electrode 25 becomes a polycrystalline silicon film similarly to the floating gate electrode 23, and is deposited on the surface of the first interlayer oxide film to control the potential of the floating gate electrode 23 by means of a positive capacitance coupling. . The end portions of the control gate electrode 25 and the floating gate electrode 23 in the channel direction are simultaneously processed in one patterning process, and the gate length thereof is 0.7 µm. The control gate electrode 25 is integrated with the word line WL and extends over the element isolation region 33.

The drain region composed of the n ⁺ type semiconductor region 26 is connected to a data line 32 made of aluminum via a connection hole 31. The junction length of the n ⁺ type semiconductor region 26 is about 0.01 μm except for the portion directly below the connection hole 31, and the junction depth below the connection hole 31 is deeper than other portions, and 2 μm or so.

In addition, a p ⁺ type semiconductor region (drain shield region) 27 is formed to surround the drain region, and the threshold voltage is set in the thermal equilibrium state, the channel hot electron injection efficiency is improved in the write operation, and the erase operation is performed. Punch through prevention is achieved. The impurity concentration of the p ⁺ -type semiconductor region 27 is about 5 x 10 ⁷ / cm 3 at the junction surface with the n ⁺ -type semiconductor region 26, and the depth is about 0.25 μm at the surface of the semiconductor substrate 21. to be.

The source region is an n ⁺ type semiconductor region 28 containing arsenic (As) as an impurity and an n type semiconductor region 29 containing phosphorus (P) as an impurity, and extends in a direction in which the word line WL extends. The source line SL is formed. The junction depth of this n ⁺ type semiconductor region 28 is about 0.2 μm. In addition, the n-type semiconductor region 29 is formed so as to be interposed between the n ⁺ -type semiconductor region 28 and the p-type semiconductor substrate 21, and the junction breakdown between the source and the semiconductor substrate is controlled by the gentle inclination profile. The height is working. The impurity concentration of the n-type semiconductor region 29 is about 1 × 10 ¹⁹ / cm 3 at the interface with n ⁺ semiconductor region 28, and the junction depth is about 0.35 μm, and the junction breakdown voltage of this band exceeds 15V. .

The second interlayer oxide film 30 is made of a phosphate silica (PSG) film and covers the main surface of the p-type semiconductor substrate 21. The connection hole 31 is formed by partially removing the second interlayer oxide film 30 and the gate oxide film 22 on the drain region.

11 and 12, a protective film made of a PSG film formed by the CVD method and a silicon nitride film thereon is provided on the data line 32 of aluminum.

Next, an internal block and operation of the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIG. 9 as a memory array and peripheral circuits in which the FAST memory cells are arranged in a matrix.

The memory array M-ARRAY is, for example, a FAST type memory cell arranged in four rows and four columns, and is composed of memory cells M1 to M16, word lines W1 to W4, and data lines D1 to D4. In this embodiment, one memory block is constituted as a whole.

In the memory array, the control gates of the memory cells are connected to the corresponding word lines, and the drains of the memory cells arranged in the same column are connected to the corresponding data lines, respectively. The sources of the memory cells are collectively coupled to the common source line CS.

In addition, although not particularly limited, the memory array is configured to provide eight or ten sets in total in order to perform write and read operations in units of 8 bits or 16 bits.

Each data line D1 to D4 constituting the memory array is connected to a common data line CD via an address decoder YDCR. The output terminal of the write data input circuit DIB, which receives the write signal input from the external input / output terminal I / O, is connected to the common data line CD via the MOSFET Q5 which is turned ON at the time of writing.

The sense amplifier SA is connected to this common data line CD. The output terminal of the sense amplifier SA is connected to the I / O terminal via the data output buffer DOB.

Similarly, for other memory arrays, an address decoder, a common data line, a sense amplifier, and a data input / output circuit are provided and connected to the I / O terminal.

Further, each word line W1 to W4 constituting the memory array is connected to an address decoder XDCR that selects a word line in read and write operations via the transistors Q1 to Q4 and applies a negative voltage at the time of erasing. It is connected to the circuit NEG.

The transistors Q1 to Q4 are deflation type p-type NOSFETs and serve to prevent the negative voltage applied to the word line from being erased to the address decoder circuit. At the same time, the read and write operations are made deflation type in order to prevent the voltage drop and the speed drop in the transistors.

The common source line CS is connected to the erase voltage application circuit ED. The erase voltage application circuit ED applies a positive voltage (Vcc, which is an external power supply voltage in this case) at the time of erasure, and connects the common source line CS to the ground potential 0V of the circuit during read and write operations.

First, in the read operation, the address decoder circuits XDCR and YDCR are activated to select one word line and one data line. The low voltage Vcc is supplied as the operating voltage to the address decoder circuits XDCR and YDCR. The memory cell has a high threshold value or a low threshold value for the selection level of the word line according to the pre-written data. When the threshold value of the memory cell selected by each of the address decoders XDCR and YDCR is high, the memory cell stops in the OFF state even though the word line is at the selection level. On the other hand, when the threshold value of the selected memory cell is low, the memory cell is turned ON by the word line selection level. The presence or absence of a current flowing in the common data line corresponding to the threshold value of the memory cell is detected at the sense amplifier SA connected via the switch MOSPET Q6, and is detected at the external terminal I / O through the data output buffer DOB activated in read mode. Is output.

In the write operation, the address decoder circuits XDCR and YDCR are activated in the same manner as the read operation, and one word line and one data line are selected.

The high voltage Vpp is supplied to the address decoder circuits XDCR and YDCR as its operating voltage, and the low voltage Vcc is supplied to the data input circuit DIB, respectively. MOSFET Q6 is then turned OFF, which disables the data output buffer DOB and sense amplifier SA. The selected word line has its voltage at the high voltage Vpp. Similarly, the selected data line is connected to the low voltage Vcc via MOSFETs Q5 and DIB. As a result, hot electrons are injected into the floating gate in the memory cell at the intersection thereof to perform writing. In the memory cell in the written state, electrons are accumulated in the floating gate, and the threshold voltage seen from the control gate becomes high. In the memory device of this embodiment, the hot electron injection efficiency is high due to the miniaturization of the gate length of the memory cell to 0.7 mu m and the introduction effect of the p ⁺ type semiconductor region (drain shield region) 27 shown in FIG. Therefore, the low voltage Vcc voltage can be used as the data line driving voltage. When the Vcc voltage is supplied from the Vcc power supply external to the storage device, and the Vpp voltage is generated at the Vcc voltage using the boost circuit in the device, the word line having a small current flowing through the Vcc single power supply can be written. It is possible.

In order to perform the above read and write operations normally, the memory cell should not be in the depressed state. If there is a cell in the depressed state, an undesired leakage current flows there, and thus the desired memory cell cannot be selected. This means that controllability is important in the erasing operation described later.

Next, an erase operation which is a feature of the present embodiment will be described.

In the erase operation of this embodiment, a negative voltage is applied to a control gate of a memory cell and a positive voltage (here, Vcc, which is an external power supply voltage) is applied to a control gate of a memory cell, and electrons held at the floating gate are caused by the potential difference between the positive and negative voltages. This is done by extracting to the source region by tunnel release. The erase voltage applying circuit ED and the negative voltage applying circuit NEG are supplied with a power supply voltage Vcc as its operating voltage.

를 입력으로 하는 인버터 회로로서 공통소스선 CS에는 상기 전원전압 Vcc가 인가된다.The erase voltage applying circuit ED has an erase pulse as shown in FIG.

The power supply voltage Vcc is applied to the common source line CS as an inverter circuit having the input as.

In addition, a negative erase voltage is applied to the word lines W1 and W4 by the negative voltage applying circuit NEG.

14 shows the circuit configuration of the negative voltage application circuit NEG. This circuit is a so-called ground pump circuit.

가 저레벨로 되면 지연회로 D3에서 결정된 시간이 경과한 후 신호

가 저레벨로 되고, 디코더 분리신호 SET가 고레벨로 된다. 이것에 의해 어드레스 디코더회로 XDCR은 워드선에서 전기적으로 분리된다. 다음에 발진기 OSC2가 발진을 개시하여 상보적 펄스 신호 PU1과 PU2가 발생하고, 이것을 이용해서 차지펌프의 원리에 의해서 부전압 Vppn을 발생시킨다. 이것을 또 PU1을 사용해서 마찬가지로 차지펌프에 따라서 워드선 W1∼W4에 인가한다. 소거신호

가 고레벨로 되면 펄스신호 PU1과 PU2는 정지하지만 신호

가 고레벨로 되기까지의 기간은 부적합 리세트 신호 PRST와 ERST가 부전위의 절점(joint)을 0V 또는 정의 전압으로 하여 소거를 정지한다.Cancel signal in FIG.

Becomes low level, the signal after the time determined by delay circuit D3 has elapsed.

Becomes low level, and decoder separate signal SET becomes high level. As a result, the address decoder circuit XDCR is electrically separated from the word line. The oscillator OSC2 starts oscillation, and the complementary pulse signals PU1 and PU2 are generated, and the negative voltage Vppn is generated using the charge pump principle using this. This is again applied to the word lines W1 to W4 in accordance with the charge pump using PU1. Cancel signal

Is high, pulse signals PU1 and PU2 stop but signal

In the period until the high level is reached, the reset signals PRST and ERST stop the erasure with the joint of the negative potential as 0 V or a positive voltage.

Since the current flowing through the word line during the erase operation is small, as described above, the negative voltage required for erasing by the negative voltage applying circuit NEG in the device is externally supplied to the external power supply voltage (power supply voltage supplied from the outside of the chip via the external terminal). Can be generated and supplied to the word line. On the other hand, an external power supply voltage Vcc is used for the low voltage Vcc applied to the common source line CS through which a large amount of leakage current flows. In this way, the electrical collective erase operation for collectively erasing the entire memory array can be performed with a single Vcc power supply (power supply voltage Vcc and ground potential Vss of the circuit).

The data lines D1 to D4 during the erasing operation may be lowered to the ground potential Vss (0 V) by the address decoder YDCR or may be in an open state. This is because the parasitic channel current flowing from the source to the drain of the memory cell does not need to be considered in the erasing method of the present invention in which the erasing is performed by applying a large negative voltage to the control gate. In addition, the parasitic effect caused by the channel current which is a problem in the conventional erasing method in which the control gate is grounded is described in Japanese Patent Application No. 62-141486.

Next, FIG. 15 is a characteristic diagram comparing the prior art and the present embodiment in a situation where the program disturb life is reduced by the rewrite cycle.

In the prior art in which erase is performed by applying high voltage Vpp to the source, the program disturb life after rewriting of 10 ⁴ is reduced to 3 to 4 digits compared to the initial characteristic before rewriting. On the other hand, in the present invention where the source voltage can be lowered to Vcc and erased, it can be seen that the decrease in life is about half a digit, so that the influence of rewrite can be suppressed to a level with almost no problem.

The program disturb life is defined as the time until the threshold voltage of the memory cell in the word line half-selected state rises by 0.1V.

, a1,

를 받아서 임의의 워드선 1개의 선택적으로 소거전압을 인가한다. 이 결과 소거동작은 각각의 워드선에 접속된 메모리셀 군을 메모리 블록으로서 워드선 단위로 실행된다.Next, in the above embodiment, the row decoder circuit XDCR and the negative voltage application circuit NEG are constituted by respective circuits, but the present invention is not limited thereto. For example, you may comprise using one circuit XCDRN, as shown in FIG. This circuit is provided between the row address buffer circuit and the word line like the row decoder circuit XDCR. In this case, at the time of erasing, the source of the n-type MOSFET of the inverter circuit INV1 of the last stage and the inverter circuit INV2 of the preceding stage is connected to the negative voltage power supply Vppn. In addition, the ground potential Vss is set at the time of lead and write. However, the reset at the end of erasing must be performed in the same manner as in the previous case. A reset circuit for this purpose is shown in FIG. The circuit XDCRN is integrated with the row decoder circuit, and the outputs a0,

, a1,

The erase voltage is selectively applied to one word line. As a result, the erasing operation is performed in units of word lines as a memory block with a group of memory cells connected to each word line.

Here, the FAST type memory cell is usually formed on the p type substrate, and the substrate potential becomes the ground potential. Therefore, in order to realize the circuit XDCRN, as shown in FIG. 18, the n-type MOSFET of the final inverter circuit INV1 and the inverter circuit INV2 at the front end thereof is formed in the p-type well provided in the n-type well to form this p-type well. This can be connected to the negative voltage power supply Vppn. Of course, in the case of using an n-type substrate, a p-type well may be formed in the same manner as a normal circuit, and the p-type well may be connected to the negative voltage power supply Vpp. In FIG. 18, reference numeral 101 denotes a p-type semiconductor substrate, 102 denotes an n-type well region, 103 denotes an n-type well region 102 and p is separated from the p-type semiconductor substrate 101. type well region, 104 is a p ⁺ type semiconductor region for connecting the p-type semiconductor substrate 101 to the ground potential Vss, 105 for connecting the n-type well region 102 to the ground potential Vss n ⁺ Type semiconductor region 106 is a p ⁺ type semiconductor region for connecting the p type well region 103 to the negative power supply voltage Vppn during the erase operation and to the ground potential Vss during the write and read operations. , 108 is an n ⁺ type semiconductor region constituting a source and a drain region of a MOS transistor formed in the p-type well region 103, 109 is a gate oxide film of the MOS transistor, and 110 is a gate of the MOS transistor Electrode.

An embodiment of the present invention will be described with reference to FIG.

FIG. 19 is a sectional view of two bits of the FAST type memory cell used in the nonvolatile semiconductor memory device of this embodiment (part A-A 'in FIG. 10), which corresponds to FIG.

The memory cell used here has the same structure as the memory cell of FIG. 11 of the above embodiment except that the n-type semiconductor region 29 containing p as an impurity is not present in the source region. By eliminating the n-type semiconductor region, the capacitance between the source region and the floating gate is reduced to approximately 60% during the erasing operation, thereby realizing low voltage and / or high speed of erasing. On the other hand, the junction breakdown voltage between the source and the substrate drops to about 12V, but there is no problem in this embodiment in which the voltage applied to the source is lowered to Vcc to be erased.

Except for the difference in the source structure of the memory cell described above, the memory device of this embodiment is the same as the embodiment of FIGS. 3 to 18, and operates similarly.

Another embodiment of the present invention will be described with reference to FIGS. 20 to 22.

20 is an internal block diagram of the nonvolatile semiconductor memory device according to this embodiment, which corresponds to FIG. 9 of the embodiment. As the memory cell, a FAST type memory cell similar to the third embodiment or the embodiment of FIG. 19 is used.

The operation of the nonvolatile semiconductor memory device according to the present embodiment is essentially the same as that of the embodiment of FIG. 3 or 19. However, the erase operation is a unit of a memory block in which the memory array M-ARRAY is divided in the word line direction. This is different. Here, the memory array is divided into two blocks of the memory block MB1 which is the memory cell groups M1 to M8 connected to the word lines W1 and W2 and the memory block MB2 which is the memory cell group M9 to M16 connected to the word lines W3 and W4.

21 shows the circuit configuration of the negative voltage application circuit NEG. This embodiment differs from the fourteenth embodiment in that a decode function for selecting a memory block is built in. That is, in the negative voltage applying circuit NEG of FIG. 21, the negative voltage Vppn is applied only to the word line corresponding to the memory block which performs the erase operation, and the ground voltage 0V is applied to the unselected word line.

모두 저레벨로 되고, A1 어드레스 입력에 의해서 결정되는 2개의 워드선 출력 WI1과 WI2 또는 WI3과 WI4가 고레벨로 된다. 이 WI1∼WI4는 부전압 인가회로 NEG에 공급된다. 그러나 트랜지스터 Q1∼Q4의 작용에 의해 소거시에는 디코더 회로의 출력이 워드선 W1∼W4에는 인가되지 않는다.The memory block is selected. In this embodiment, as shown in FIG. 22, A1, which is one of the row input external inputs of the address buffer circuit ADB, is used. The memory block is selected even when the A0 input and the row decoder XDCR in the address buffer circuit ADB are erased. That is, a0,

Both are at the low level, and the two word line outputs WI1 and WI2 or WI3 and WI4 determined by the A1 address input are at the high level. These WI1 to WI4 are supplied to the negative voltage application circuit NEG. However, due to the action of the transistors Q1 to Q4, the output of the decoder circuit is not applied to the word lines W1 to W4 during erasing.

In addition, the memory cells in the non-selected memory block enter an erase half-selected state in which a positive voltage (in this case, an external power supply voltage Vcc) is applied only to the source region via a common source line. However, the distress phenomenon accompanying this is applied to the selected word line. This can be solved by appropriate setting of the negative voltage Vppn and the gate / interlayer oxide film thickness.

Another embodiment of the present invention will be described with reference to FIGS. 23 to 25.

FIG. 23 is an internal block diagram of the nonvolatile semiconductor memory device according to the present embodiment, which corresponds to FIG. 9 of the embodiment or FIG. 20 of the embodiment. 24 is a circuit configuration diagram of the negative voltage applying circuit NEG, which corresponds to FIGS. 14 and 21 of the embodiment. FIG. 25 is a cross-sectional view (part A-A 'in FIG. 10) of a FAST type memory cell used in the nonvolatile semiconductor memory device of this embodiment, which corresponds to FIGS. 11 and 19 of the embodiment.

Although the present embodiment is not substantially different in operation from the embodiments of FIGS. 9 to 22, when the VCC voltage is applied to the data line instead of the source line, the data line and the negative erase voltage are applied at the same time. The word lines to be decoded are different. This selectively erases one bit of the memory cell at the intersection of the pair of selection data lines and the selection word line. Only differences from the embodiments of FIGS. 9 to 22 are described below.

가 고레벨에 있으므로 OFF 상태로 된다. 또 MOS 트랜지스터 Q52도 마찬가지로 OFF로 되고, 공통 소스선 CS는 개방상태로 된다. 소거동작은 제어 게이트의 부전압과 드레인의 상기 정전압과의 전위 차로 실행되고, 부유 게이트의 전자는 소스가 아니라 드레인 영역으로 추출된다. 상기 정전압을 인가하는 데이터선은 열 어드레스 디코더 YDCR에 의해서 선택된다. 한편 제24도에 도시한 바와 같이 부전압 인가회로 NEG는 행선택용 외부입력 신호 A0, A1로 형성된 신호 WI1∼WI4를 사용해서 임의의 워드선을 선택하는 디코드 기능을 내장하고 있다. 이렇게 해서 1쌍의 데이터선가 워드선이 선택되어 그 교차점에 있는 메모리셀이 선택적으로 소거된다.As shown in FIG. 23, in the present embodiment, when the erasing signal EP becomes high at the time of erasing, the MOS transistor Q7 is turned on, and through this Q7, the positive voltage (here, the external power supply voltage Vcc) has a common data line CD. Is applied to. At this time, the MOS transistor Q51 is a write signal.

Is OFF because it is at a high level. The MOS transistor Q52 is similarly turned off, and the common source line CS is turned open. The erase operation is performed at a potential difference between the negative voltage of the control gate and the constant voltage of the drain, and the electrons of the floating gate are extracted to the drain region rather than the source. The data line to which the constant voltage is applied is selected by the column address decoder YDCR. On the other hand, as shown in Fig. 24, the negative voltage application circuit NEG has a built-in decoding function for selecting an arbitrary word line using the signals WI1 to WI4 formed of the row selection external input signals A0 and A1. In this way, the word line is selected for the pair of data lines, and the memory cells at the intersection thereof are selectively erased.

가 저레벨로 되므로 외부 입력신호 I/O 에 따라서 MOS 트랜지스터 Q51, Q52가 ON, OFF된다. 외부 입력신호 I/O가 저레벨(0 상태)일 때 MOS 트랜지스터 Q51, Q52는 모두 ON 상태로 되어 공통 소스선 CS는 라이트 Vcc 전압에 접속되고, 공통 데이터선 CD는 접지전위 Vss에 접속된다. 이때 열 어드레스 디코더 YDCR에 의해서 선택 데이터선은 공통 데이터선 CD(접지전위)에 접속되는 한편, 비선택 데이터선은 개방상태로 된다. 또, 워드선에 관해서는 행 어드레스 디코더 XDCR에 의해서 선택 워드선에는 Vpp 전압이 인가되는 한편, 비선택 워드선은 접지전위로 유지된다. 어떻게 해서 선택 데이터선과 선택 워드선의 교차점에 있는 메모리셀에서 열전자 라이트가 실행된다.The write operation using hot electron injection is inversely performed on the source region side. As shown in FIG. 23, the write signal at the time of writing

Becomes low level, the MOS transistors Q51 and Q52 are turned on and off in accordance with the external input signal I / O. When the external input signal I / O is at a low level (0 state), both the MOS transistors Q51 and Q52 are turned on so that the common source line CS is connected to the write Vcc voltage, and the common data line CD is connected to the ground potential Vss. At this time, the selected data line is connected to the common data line CD (ground potential) by the column address decoder YDCR, while the unselected data line is left open. As for the word line, the Vpp voltage is applied to the selected word line by the row address decoder XDCR, while the unselected word line is held at ground potential. In this way, the thermoelectron write is executed in the memory cell at the intersection of the selection data line and the selection word line.

의 NOR 출력이 들어 있지만 어느 한쪽은 단지

의 반전 신호가 입력되는 구성이라도 좋다.In this embodiment, the gates of both of the switch MOS transistors Q51 and Q52 are connected to the external input signal I / O.

Contains the NOR output, but either side is just

The inverted signal may be input.

Next, Fig. 25 is a sectional view of two bits of the FAST type memory cell used in this embodiment. In the same figure, reference numeral 51 denotes a p-type semiconductor substrate, 52 denotes a thin gate oxide film (tunnel oxide film) formed on the main surface side of the p-type semiconductor substrate, 53 denotes a floating gate electrode 54, a first interlayer oxide film, Reference numeral 55 is a control gate electrode, 56 is an n ⁺ type semiconductor region (part of the drain region), 57 is an n type semiconductor region (part of the drain region), and 58 is an n ⁺ type semiconductor region (source Region), 59 are p ⁺ type semiconductor regions (source shield layers), 60 are second interlayer oxide films, 61 are connection holes, and 62 are aluminum data lines.

In this embodiment, since writing is performed on the source side and erasing on the drain side, the source junction is an expanded concentration type of n ⁺ / p ⁺ and the drain is an electric field relaxation type of n ⁺ / n / p. This is different from the case of the embodiment of FIG.

Another embodiment of the present invention will be described with reference to FIGS. 29-36. In this embodiment, it is assumed that the memory cell shown in Fig. 28 is shown. That is, the erasing is performed by grounding the gate and applying a high voltage to the source.

Each circuit element in the figure is not particularly limited, but is formed on a semiconductor substrate such as one single crystal silicon by a known technique for manufacturing a CMOS integrated circuit.

Although not particularly limited, an integrated circuit is formed on a semiconductor substrate made of single crystal p-type silicon. The n-channel MOSFET is composed of a source region, a drain region formed on the surface of the semiconductor substrate, and a gate electrode made of polysilicon formed through a thin gate insulating film on the semiconductor substrate between the source region and the drain region.

P-channel MOSFETs are formed in n-type well regions formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate constitutes a common substrate gate of several N-channel MOSFETs formed thereon, and the ground potential of the circuit is supplied. The common substrate gate of the P-channel MOSFET, that is, the n-type well region, is connected to the power supply voltage Vcc. Alternatively, in the case of a high voltage circuit, it is connected to the external high voltage Vpp, the internally generated high voltage, or the like. Alternatively, the integrated circuit may be formed on a semiconductor substrate made of single crystal n-type silicon. In this case, the n-channel MOSFET is formed in the p-type well region.

에 의해 활성화되고, 외부단자에서의 어드레스 신호 AX, AY를 입력하여 외부 단자에서 공급된 어드레스신호와 동일상의 내부 어드레스 신호와 역상의 어드레스 신호로 되는 상보 어드레스 신호를 형성한다.Although not particularly proposed, in the EEPROM of this embodiment, the complementary address signals formed by the address signal AX and the drawing via the QKESSM address buffer ADB are supplied to the address decoders XDCR and YDCR. Although not particularly limited, the address buffers XADB and YADB are internal chip select signals.

Is activated by inputting the address signals AX and AY from the external terminals to form a complementary address signal which becomes an internal address signal in the same phase as the address signal supplied from the external terminal and an address signal in the reverse phase.

The row address decoder XDCR is activated by the address decoder activation signal DE to form the selection signal of the word line W of the memory array M-ARRAY according to the complementary address signal of the address buffer XADB.

The column address decoder YDCR is activated by the address decoder activation signal DE to form selection signals of the data lines D1-D4 of the memory array M-ARRAY according to the complementary address signals of the address buffer ADB.

The memory array M-ARRAY is shown as an example of two memory blocks MB1 and MB2 as cannons. The memory block MB1 is formed by the memory elements M1 to M8, the word lines W1 to W4, and the data lines D1 and D2. The memory block MB2 is formed by the memory elements M9 to M16, the word lines W1 to W4 and the data lines D3 and D4. Each is composed.

In the memory block, the gates of the memory elements arranged in the same row are respectively connected to the corresponding word lines, and the drains of the memory elements arranged in the same column are each connected to the corresponding data lines. The source of the memory element is coupled to source lines CS1 and CS2. In this embodiment, erase control circuits ED1 and ED2 are provided in the source lines CS1 and CS2.

Although not particularly limited, as described above, the memory array is configured such that eight or sixteen sets of memory arrays are provided in order to execute write and read operations in units of eight or sixteen bits.

Each data line D1 to D4 constituting the one memory array M-ARRAY is connected to a common data line CD via column select switches MOSFETs Q1 to Q4 that receive a selection signal configured by the address decoder YDCR. The common data line CD is connected to the output terminal of the write data input buffer DIB, which receives the write signal input from the external terminal I / O, through the MOSFET Q5, which is turned ON at the time of writing. Similarly, the same column selection switch MOSFETs are provided for the other memory arrays, and the selection signal is formed by the address decoder corresponding thereto.

The common data line CD provided corresponding to the memory array M-ARRAY is coupled to the sense amplifier SA via the switch MOSFET Q6.

Although the circuit of the sense amplifier SA is shown in FIG. 30, the common data line CD is connected to the source of the n-channel MOSFET Q7 to which the source is connected via the MOSFET Q6 which is turned ON by the read control signal re. A p-channel load MOSFET Q8 is provided between the drain of the n-channel MOSFET Q7 and the power supply voltage terminal Vcc at which the ground potential of the circuit is applied to the gate thereof. The load MOSFET Q8 performs an operation of flowing a precharge current through the common data line CD for a read operation.

To increase the strength of the MOSFET Q7, the potential of the common data line CD is passed through the switch MOSFET Q6 to maintain the potential of the data line at a substantially constant low voltage to prevent weak writes in the reads. Is supplied to the gate of the drive MOSFET Q9 which is the input of the inverted amplifier circuit which becomes the load MOSFET Q10 of the type.

가 공듭된다.The output voltage of this inverting amplifier circuit is supplied to the gate of the MOSFET Q7. In addition, an n-channel MOSFET Q11 is provided between the gate of the MOSFET Q7 and the ground potential of the circuit to prevent reckless current consumption in the non-operation period of the sense amplifier. The operating timing signal of the sense amplifier is common to the MOSFET Q11 and the gate of the p-type MOSFET Q10.

Is knotted.

및 VPP에 공급되는 칩 이네이블 신호, 출력이네이블신호, 라이트 이네이블신호, 소거이내이블신호 및 라이트/소거용 고전압에 따라서 내부 제어신호

,

등의 타이밍 신호 및 어드레스 디코더 등에 선택적으로 공급하는 리드용 저전압 Vcc/라이트용 고전압 Vpp 등을 발생한다. 예를 들면, 제31도와 같은 각 모드와 외부신호의 관계를 가정하면, 이것을 실현하기 위한 타이밍제어회로 CNTR로서는 제32도에 도시한 것을 예로서 고려할 수 있다.The timing control circuit CNTR is not particularly limited, but the external complex

And an internal control signal according to a chip enable signal, an output enable signal, a write enable signal, an erase enable signal, and a write / erase high voltage supplied to the VPP.

,

And a low voltage Vcc for read and a high voltage Vpp for write, which are selectively supplied to a timing signal such as an address decoder and the like. For example, assuming a relationship between each mode as shown in FIG. 31 and an external signal, the timing control circuit CNTR for realizing this can be considered as an example shown in FIG.

는 저레벨, DE, re가 고레벨,

가 저레벨로 된다. 어드레스 디코더 회로 XDCR, YDCR이 활성화되어 1개의 워드선, 1개의 데이터선이 선택된다. 어드레스 디코더 회로 XDCR, YDCR, 데이터 입력회로 DIB에는 그 동작전압으로서 저전압 Vcc가 공급된다. MOSFET Q10은 ON상태로, MOSFET Q11은 OFF 상태로 된다.The lead signal has the internal signal

Is low level, DE, re is high level,

Becomes low level. The address decoder circuits XDCR and YDCR are activated to select one word line and one data line. The low voltage Vcc is supplied to the address decoder circuits XDCR, YDCR and the data input circuit DIB as its operating voltage. MOSFET Q10 is turned ON and MOSFET Q11 is turned OFF.

The memory cell has a high threshold value or a low threshold value for the selection level of the word line according to the pre-written data. When the threshold value of the memory cells selected by the respective address decoders XDCR and YDCR is high and the word line is at the selected level, the common data line CD is relatively turned off by the current supply from the MOSFETs Q8 and Q7 when the word line is in the OFF state. It becomes high high level. On the other hand, when the selected memory cell is turned ON by the word line selection level, the common data line CD is at a relatively low low level.

In this case, the common data line CDml high level is limited to a relatively low potential by supplying a relatively low low level output voltage formed by the inverting amplifier circuit which receives it to the gate of the MOSFET Q7. On the other hand, the low level of the common data line CD is limited to a relatively high potential by supplying a relatively high high level output voltage formed by the receiving inverting amplifier circuit to the gate of the MOSFET Q7.

에 의해 제어된다. D0가 리드모드, 라이트 후의 검증모드에서는 고레벨로 되고, 데이터출력버퍼 DOB를 활성화하여 I/O 단자로 데이터를 송출한다. 다른 메모리 블록에 대응한 공통 데이터선과 외부 단자 사이에도 상기와 마찬가지의 샌스앰프 및 데이터 출력 버퍼로 되는 리드 회로가 각각 마련된다.In addition, the MOSFET Q7 of the amplification yaw performs the amplification operation of the gate ground type source input and transfers the output signal to the CMOS inverter circuit INV1. This output signal is then waveform shaped at inverter IVN2. The signal SO goes high when the threshold of the memory is high, and goes low when it is low. Although not particularly limited by the corresponding data output buffer DOB, it is amplified and sent out from the external terminal I / O. This data output buffer DOB is a data output buffer control signal D0,

Controlled by D0 is at high level in the read mode and the verify mode after writing, and the data output buffer DOB is activated to send data to the I / O terminal. A read circuit serving as the above-described sand amplifier and data output buffer is also provided between the common data line corresponding to the other memory block and the external terminal.

는 저레벨 DE, wr,

는 고레벨로 되고, re, D0는 저레벨로 된다. 어드레스 디코더회로 XDCR, YDCR이 활성화되어 1개의 워드선, 1개의 데이터선에 선택된다. 어드레스 디코더회로 XDCR, YDCR, 데이터 입력회로 DIB에는 그 동작전압으로서 고전압 Vpp가 공급된다. MOSFET Q6은 OFF로 되고, 데이터 출력버퍼 DOB, 센스 앰프는 비활성화된다. 라이트가 실행되는 워드선은 그 전압이 상기 고전압 Vpp로 된다. 부유 게이트에 전자를 주입해야 할 기억소자가 접속된 데이터선은 MOSFET Q5, DIB를 거쳐서 고전압 Vpp에 접합된다. 이것에 의해 기억소자에 라이트가 실행된다. 타이트된 상태의 기억소자는 그 부유 게이트에 전자가 축적되고, 임계값 전압은 높게 되어 워드선을 선택해도 드레인 전류는 흐르지 않는다. 전자의 주입이 실행되지 않는 경우에 임계값 전압은 낮게 워드선을 선택하면 전류가 흐른다. 다른 메모리 블록에 대응한 공통 데이터선과 외부 단자 사이에도 상기와 마찬가지의 입력단 회로 및 데이터 입력버퍼로 되는 라이트 회로가 각각 마련된다.The internal signal in the write mode

Low-level DE, wr,

Becomes high level, and re and D0 become low level. The address decoder circuits XDCR and YDCR are activated and selected for one word line and one data line. The high voltage Vpp is supplied to the address decoder circuits XDCR, YDCR, and data input circuit DIB as its operating voltage. MOSFET Q6 is turned off, and the data output buffer DOB and sense amplifiers are disabled. The word line on which the write is executed has its voltage at the high voltage Vpp. The data line to which the memory element to inject electrons into the floating gate is connected to the high voltage Vpp via the MOSFETs Q5 and DIB. This writes to the memory device. In the memory device in the tight state, electrons are accumulated in the floating gate, and the threshold voltage becomes high so that the drain current does not flow even when the word line is selected. When the injection of electrons is not carried out, selecting a word line with a low threshold voltage causes current to flow. The same input terminal circuit and write circuit as the data input buffer are provided between the common data line and the external terminal corresponding to the other memory block, respectively.

In the verify mode after the write, the read mode is in the same state as the read mode except that the high voltage is applied to the Vpp terminal. The address decoder circuits XDCR, YDCR, data input circuit, and DIB are supplied by being switched from high voltage Vpp to Vcc as their operating voltages. The user performs a check to see if it has been written.

In the write / erase inverse mode, each decoder is active, but the high voltage for write / erase is not supplied to each decoder.

Execution is performed in accordance with FIGS. 33 to 36 in the erase mode. FIG. 33 shows the erase control circuit ECNTR shown in FIG. 29, FIG. 34 shows the erase voltage applying circuit ED in FIG. 29, FIG. 35 shows the address buffer circuit ADB and decoder circuits XDCR and YDCR, and FIG. Each timing diagram is shown. In the erase load, the control signals DE, wr, re, and D0 become the low level SC to the high level.

가 고레벨에서 저레벨로 변화하면 소거모드의 개시로 된다. 먼저 지연회로 D1에 의해 결정된 시간만 리세트 펄스 RST가 고레벨로 되어 소거전압 인가회로 ED를 미세트한다. 다음에 폴리플롭회로 FF가 세트되어 소거하고자 하는 블록의 리드를 실행한다. 이 사이 소거전 리드 모드신호 EV가 저레벨로 되고, 발진기 OSC1이 발전을 개시하여 내부 어드레스를 발생한다. 2진 카운터 C에 의해 순차로 분주된 신호 A0I, A1I, A2I가 어드레스 버퍼 ADB에 공급되고, 이것으로 EE1이 고레벨임으로 어드레스 버퍼 ADB는 A3을 제외하고 외부에서의 입력을 받지 않는다. 어드레스 신호 A3은 외부에서 부여되고, 내부 블록 MB1 또는 MB2의 선택에 사용된다.

Is changed from the high level to the low level, the erasing mode starts. First, only the time determined by the delay circuit D1 resets the reset pulse RST to a high level to finely erase the erase voltage application circuit ED. Next, the polyflop circuit FF is set to read the block to be erased. During this period, the read mode signal EV before erasing is at a low level, and the oscillator OSC1 starts generating power to generate an internal address. The signals A0I, A1I, and A2I sequentially divided by the binary counter C are supplied to the address buffer ADB. As a result, EE1 is at a high level so that the address buffer ADB does not receive external input except for A3. The address signal A3 is externally given and used for the selection of the internal block MB1 or MB2.

가 저레벨로 되어도 공통 소스선 CS1에는 고전압이 인가되지 않는다. 메모리블럭내의 모든 메모리셀에 대해서 리드가 완료하면 리드 완료신호 ER이 고레벨로 되고, 플립플롭 FF을 리세트하여 EV를 저레벨로 한다. 다음에 소거기간으로 되고, 지연회로 D2에서 결정된 기간의 시간이 경과한 후 소거펄스 EP가 저레벨로 되어 전워드선을 저레벨로 하고, 소거가 충분하지 않은 메모리의 소스에 고전압이 인가된다.When the read of the memory selected by the internal address is executed, the result is returned to the erase suppression application circuit ED. As shown in FIG. 34, for the memory block MB1, the output SO of the sense amplifier SA is at a high level when one of the column selection signals Y1 and Y2 is at a low level in the period of high level, that is, the threshold of the memory cell. If it is determined that the voltage is high, the flip-flop is set, and the erase pulse is erased in the erase period described next.

The high voltage is not applied to the common source line CS1 even when is set to the low level. When the read is completed for all the memory cells in the memory block, the read completion signal ER becomes high level, and the flip-flop FF is reset to make the EV low level. Next, the erase period is set, and after the time period determined by the delay circuit D2 has elapsed, the erase pulse EP becomes low level, and the entire word line is made low, and a high voltage is applied to the source of the memory which is not sufficiently erased.

In the case shown in FIG. 29, since there is only one erase voltage application circuit ED in the memory block, optimization is performed for each I / O (memory array) having 8 or 16 sets. Further, when the entire chip is erased, optimization is further performed for each of the memory blocks MB1 and MB2.

In the lead, a voltage Vev, for example, 3.5 V, which is lower than a normal read voltage (for example, 5 V) is supplied to the sense amplifier SA, the decoder circuits XDCR, and YDCR in order to secure an operating power supply voltage margin. This is preferably generated inside the memory, but may be provided externally.

The effect of the present invention is shown in FIG. The vertical axis represents the instability of the threshold voltage in the device after erasing, and the horizontal axis represents the number of memory elements in one memory block. In this example, eight sets of memory arrays M-ARRAY exist in the apparatus, and the write and read operations are performed in units of 8 bits. The smaller the memory element in the memory block, the greater the effect, but the more complicated the peripheral circuitry. The suppression effect of threshold voltage instability can also be determined by balancing the complexity of the peripheral circuitry to determine the size of the memory block.

Although only the present embodiment has described the case where the read before erasing is performed for all the memory elements in the memory block, the present invention is not limited to this. In the case of the eight sets of read / write units, the read may be stopped when the memory cell having a high threshold voltage is detected in all the read / write units, and the operation may be performed. This can shorten the read time before erasing.

In the present embodiment, the write / erase is performed using the high voltage Vpp from the outside, but the present invention is not limited thereto. If the current flowing during write / erase is small, the device may generate the high voltage desired by Vcc inside the device and use it for write / erase. Moreover, you may use this internal boosting power supply together with external high voltage Vpp.

In addition, of course, this invention is not limited to the said Example. The configuration of the circuit portion for controlling the normal write / read or the like or the circuit portion for controlling the erasure may be any of the above experiments.

Another embodiment of the present invention will be described with reference to FIGS. 37 to 39.

37 is an internal block diagram of the nonvolatile memory device according to the present embodiment, which corresponds to FIG. 29 of the embodiment. The memory cell is a memory of a method in which a negative voltage is applied to a gate during erasing and a positive positive voltage (in this case, an external power supply, Vcc) is applied to a source to extract electrons in the floating gate as a source by a high field between the gate and the source. I use it.

Except for this erasing operation, this embodiment describes only the difference from the above embodiment since there is no substantial difference in operation from the embodiment of FIG.

The transistors Q12 to Q15 are deflation type PMOSFETs and serve to prevent the negative voltage applied to the word line during erasing from being applied to the decoder circuit. At the same time, the read / write operation is made deflation type in order to prevent the voltage drop and the speed drop in the transistor.

The erase voltage application circuits ED1 and ED2 are the same as in FIG. 34 except for the final stage as shown in FIG. 38. In FIG. 34, Vpp is applied to the common source line CS1. In this case, Vcc is applied.

가 저레벨로 되면 지연회로 D3에서 결정된 시간이 경과한 후 신호

가 저레벨로 되고, 디코더분리신호 SET가 고레벨로 된다. 이것에 의해 행 디코더회로 XDCR은 워드선에서 전기적으로 분리된다. 다음에 발진기 OSC2가 발진을 개시하여 상보적 펄스신호 PU1가 Pu2가 발생하고, 이것에 의해 차지펌프의 원리에 따라 부전압 Vppn이 발생한다. 이것을 또 펄스 PU1을 사용해서 마찬가지로 차지펌프의 원리에 따라 워드선에 부전압을 인가한다. 소거신호

가 고레벨로 되면 펄스 PU1과 PU2는 정지되지만 신호

가 고레벨로 되기까지의 기간 부전압 리세트신호 PRST와 ERST가 부전위의 정점을 0V 내지 정의 전압으로 하여 소거를 정지한다.39 shows a circuit of the negative voltage application circuit NEG. So-called charge pump circuit. Cancel signal

Becomes low level, the signal after the time determined by delay circuit D3 has elapsed.

Becomes low level, and decoder separation signal SET becomes high level. As a result, the row decoder circuit XDCR is electrically separated from the word line. The oscillator OSC2 starts oscillation, and the complementary pulse signal PU1 generates Pu2, which generates a negative voltage Vppn according to the principle of the charge pump. Again, the pulse PU1 is used to apply a negative voltage to the word line in accordance with the principle of the charge pump. Cancel signal

Becomes high level, pulses PU1 and PU2 stop but signal

Period until the high level is reached The negative voltage reset signals PRST and ERST stop erasing by setting the peak of the negative potential to 0 V or a positive voltage.

The operation in the erase mode in this embodiment is executed as in the case of the embodiment of FIG. In the embodiment of FIG. 29, the high voltage is applied to the source to erase the Vcc and the negative voltage to the gate.

Another embodiment of the present invention will be described with reference to FIGS. 40 to 42.

40 is an internal block diagram of the nonvolatile memory device according to the present embodiment, which corresponds to FIGS. 29 and 37 of the embodiment. Here, as the memory cell of FIG. 37, the intrinsic 39 of FIG. 37, a negative voltage is applied to the gate during erasing, and a positive voltage (here, Vcc, which is an external power source) is applied to the source to float by a high electric field between the gate and the source. A memory is used to extract electrons in the gate as a source.

Although there is no substantial difference in operation from the embodiment of Figs. 37 to 39, the memory block is determined not only by the source but also by the source and the word line. Hereinafter, only the differences from the embodiment of FIG. 29 and the intrinsic FIG. 39 will be described.

FIG. 41 shows a circuit of the negative voltage application circuit NEG, which differs from FIG. 39 in that a decode function for selecting a memory block is incorporated.

모두 저레벨로 되고, A1 어드레스 입력에 따라 결정되는 2개의 위드 출력 W11과 W12, 또는 W13과 W14가 고레벨로 된다. 이 출력 W11∼W14는 부전압 인가회로 NEG에 공급된다. 그러나 트랜지스터 Q12∼Q!15의 작용에 의해 소거시에는 디코더 회로의 출력에 워드선 W1∼W4에는 인가되지 않는다.The address buffer circuit differs in that it is used for selecting blocks of the external inputs A1 and A3 as shown in FIG. In addition, in order to perform the selection of the memory block in the word direction, that is, the selection of the memory blocks MB1 and MB3, MB2 and MB4, the A0 input unit and the row decoder XDCR in the address buffer ADB are selected to perform the memory block even when the erase voltage is applied. have. That is, a0,

Both are at the low level, and the two withdrawal outputs W11 and W12 or W13 and W14 determined according to the A1 address input are at the high level. These outputs W11 to W14 are supplied to the negative voltage application circuit NEG. However, due to the action of the transistors Q12 to Q! 15, it is not applied to the word lines W1 to W4 to the output of the decoder circuit during erasing.

The operation in the erase mode in this embodiment is executed as in the case of the embodiment of Figs. However, for the embodiment of FIG. 37, the binary counter BC in FIG. 33 is not necessary once.

Representative inventions disclosed herein are listed below.

(1) A nonvolatile semiconductor memory device comprising an electrically erasable nonvolatile memory cell composed of a MOSFET having a two-layer gate structure including a floating gate and a control gate, wherein a negative voltage is applied to apply a negative voltage to a control gate of the MOSFET. A nonvolatile semiconductor memory device comprising a generation circuit and a low voltage generation circuit for applying a low voltage to the drain electrode of the MOSFET.

(2) a gate insulating film having a substantially constant film thickness provided on the surface of the semiconductor substrate, a floating gate electrode provided on the gate insulating film, a control gate electrode formed on the floating gate electrode via an interlayer insulating film, and provided separately from each other in the semiconductor substrate, The memory cell includes one element of a MOSFET having a source region and a drain region having an overlapping portion with the floating gate electrode, and a channel region between the source region and the drain region with the gate insulating layer interposed therebetween. A nonvolatile semiconductor memory device having a memory array arranged in a matrix form, the nonvolatile semiconductor memory device comprising: at least a source region of a memory cell to be subjected to at least one erase operation when an electrical erase operation for removing charges held in the floating gate electrode to the outside is performed; Either one of the drain regions Means for applying a first voltage having a polarity reversely biasing the semiconductor substrate, a means for applying a second voltage having a polarity different from the first voltage to the control gate electrode of the memory cell, and the second A nonvolatile semiconductor memory device characterized by providing a voltage conversion circuit for supplying a voltage of.

(3) a gate insulating film having a substantially constant film thickness provided on the surface of the semiconductor substrate, a floating gate electrode provided on the gate insulating film, a control gate electrode formed on the floating gate electrode via an interlayer insulating film, and provided separately from each other in the semiconductor substrate, The memory cell includes one element of a MISFET having a source region, a lane region, and a channel region between the source region and the drain region having the overlapping portion of the floating gate electrode with the gate insulating layer interposed therebetween. A nonvolatile semiconductor memory device having a memory array arranged in a form, wherein at least a source region or a drain region of a memory cell to be subjected to the erase operation when an electrical erase operation for removing charges held in the floating gate electrode to the outside is performed. Either of these areas Means for applying a first voltage having a reverse polarity with respect to the semiconductor substrate and a second voltage having a polarity different from that of the first voltage to a control gate electrode of the memory cell; A memory cell in which the control gate electrodes in the array are electrically connected in common is a nonvolatile semiconductor memory device characterized in that it performs an electrical erase operation at the same time.

(4) In the above (3), when the electrical erase operation is executed, the memory array is divided, and in each division unit, the control gate electrode of the memory cell group is shared to apply the second voltage thereto. A nonvolatile semiconductor memory device comprising means.

(5) a gate insulating film having a substantially constant film thickness provided on the surface of the semiconductor substrate, a floating gate electrode provided on the gate insulating film, a control gate electrode formed on the floating gate electrode via an interlayer insulating film, and provided separately from each other in the semiconductor substrate, and The memory cell includes one element of a MISFET having a source region and a drain region having an overlapping portion with the floating gate electrode interposed therebetween with the gate insulating film interposed therebetween, and a channel region therebetween. A nonvolatile semiconductor memory device having a memory array disposed thereon, wherein at least one of a source region or a drain region of a memory cell which is an object of the erase operation when performing an electrical erase operation for externally removing charges held in the floating gate electrode. The semiconductor on either side Means for applying a first voltage of reverse polarity to the plate and a second voltage having a polarity different from the first voltage to the control gate electrode of the memory cell; At least one data line each from among a data line group electrically commoning one of a source region or a drain region of a memory cell group arranged in the same column of the array and a word line group electrically commoning a control gate electrode of the memory cell group arranged in the same row And means for selecting a word line and applying the first voltage and the second voltage to them.

(6) The nonvolatile semiconductor memory device according to (3), (4) or (5), wherein a voltage conversion circuit for supplying the second voltage is provided.

(7) In the above (2), (3), (4), (5) or (6), the junction breakdown voltage between the semiconductor substrate and the region to which the first voltage is applied is applied among the source region and the drain region. A nonvolatile semiconductor memory device characterized by being higher than the breakdown voltage between another region and a semiconductor substrate.

(8) The said (2), (3), (4), (5) or (6) WHEREIN: The area | region where the said 1st voltage is applied is formed by the diffusion layer which becomes one kind of impurity, It is characterized by the above-mentioned. It is a nonvolatile semiconductor memory device.

(9) The nonvolatile semiconductor memory device according to (8), wherein the one kind of impurity is arsenic.

(10) A memory array formed by arranging memory blocks having memory cells of at least one electrically erasable nonvolatile memory device in a matrix, means for performing electrical erasure for each memory block, and externally According to the instruction of the erase operation, before the simultaneous erase operation of one or more memory blocks is executed, the read operation of the memory cells in the corresponding memory blocks is executed, and the erase operation of the memory block is continued or stopped according to the read information. A nonvolatile semiconductor memory device characterized by providing an erase control circuit for executing control.

(11) The memory cell according to (10), wherein the memory cell is a MOSFET having a two-layer gate structure of floating gate and control gate, and extracts information charge accumulated in the floating gate into a source, a drain, or a well using a tunnel phenomenon. Nonvolatile semiconductor storage device, characterized in that electrical erasing is performed.

(12) The memory cell according to (10), wherein the memory cell has a two-layer gate structure of floating gate and control gate, and a source or a drain is common in this memory block, and the gate is made a ground potential. A nonvolatile semiconductor memory device characterized in that electrical erasing is performed by applying a voltage to a common source or drain and extracting information charge accumulated in the floating gate into a source, a drain, or a well using a tunnel phenomenon.

(13) In (10), the memory cell is a MOSFET having a double-layer gate structure of floating gate and control gate, in which a source or a drain is common, and a negative voltage is applied to the gate. A nonvolatile semiconductor memory device characterized in that electrical erasing is performed by applying a voltage to a common source or drain and extracting information charges accumulated in the floating gate into a source, a drain, or a well using a tunnel phenomenon.

(14) The memory cell according to (10), wherein the memory cell is a MOSFET having a two-layer gate structure of floating gate and control gate, in which a source or a drain is common and a memory cell belonging to this memory block. Means for applying a negative voltage only to a word line connected to a gate of the gate, applying a negative voltage to the word line, applying a voltage to a common source and drain, and using the tunnel phenomenon to store information charges accumulated in the floating gate. A nonvolatile semiconductor memory device characterized in that electrical erasing is performed by extraction into a source, a drain, or a well.

(15) The nonvolatile semiconductor memory according to (10), (11), (12), (13) or (14), wherein the erase control circuit includes an address generating circuit for selecting a memory cell. Device.

(16) The above-mentioned (10) to (14) or (15), wherein the read operation of the memory cell for controlling the continuation and stop of the erase is performed by selecting the word line selection potential and the power supply voltage of the sense amplifier transmitted to the control gate. A nonvolatile semiconductor memory device characterized by being set at a relatively low potential.

The effect obtained by the representative of the invention disclosed in this application is briefly described as follows.

That is, a semiconductor integrated circuit device for providing a memory cell constituted by a MOSFET having a two-layer gate structure, which is a floating gate and a control gate, on a semiconductor substrate. Forming a negative voltage generating circuit for applying a voltage, and forming a low voltage generating circuit for applying a low voltage to the drain electrode of the MOSFET at the time of discharge of charge at the floating gate. The potential of the voltage applied to the control gate is lower than the conventional GND potential. Therefore, even when the potential of the voltage applied to the control gate is lowered than before, the potential difference required for the emission of electrons can be ensured between the floating gate and the drain electrode. That is, since the voltage applied to the drain electrode when the electrons are emitted from the floating gate can be lowered than before, the reliability of the semiconductor integrated circuit device can be improved.

In addition, since the voltage applied to the drain electrode can be lowered than before, the memory cell does not need to have a high withstand voltage structure. As a result, the memory cell can be miniaturized and the semiconductor integrated circuit device can be miniaturized.

In addition, an effect can be obtained that a nonvolatile semiconductor memory device capable of electrical erasing by a Vcc unit power supply and having excellent rewrite reliability and integration degree can be realized.

And. It is possible to realize a nonvolatile memory cell which has a small current consumption during the erasing operation, excellent reliability, and which can be electrically rewritten.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example, Of course, a various change is possible in the range which does not deviate from the summary.

Claims (15)

And a plurality of memory cells for storing information as values of threshold voltages, each of the plurality of memory cells each having a first semiconductor region and a second semiconductor region, the first semiconductor region, and the first semiconductor region formed in a semiconductor substrate. A first insulating film covering at least a channel forming region between the two semiconductor regions, a floating gate formed on the first insulating film and extending onto the first semiconductor region and the second semiconductor region, and a second formed on the floating gate electrode And a control gate formed on the insulating film and the second insulating film and coupled to one of a plurality of word lines, each of the plurality of memory cells having a threshold voltage in response to the application of a negative voltage to the control gate. A nonvolatile memory device which changes from a first value to a second value. The nonvolatile memory device according to claim 1, further comprising a negative voltage generating circuit for generating the negative voltage. The threshold voltage of each of the plurality of memory cells is reduced by electrons in the floating gate being emitted from the floating gate by a tunnel effect passing through the first insulating layer in response to the application of the negative voltage. Nonvolatile memory changed. The nonvolatile memory device of claim 3, wherein the negative voltage generation circuit generates the negative voltage at an external supply voltage of a constant voltage. The nonvolatile memory device according to claim 4, wherein the second value of the memory cell is not in a depression state. The nonvolatile memory device of claim 1, wherein the plurality of memory cells are divided into a plurality of blocks, and each block further includes at least one word line and a plurality of data lines. The threshold voltage of each of the plurality of memory cells is reduced by electrons in the floating gate being emitted from the floating gate by a tunnel effect passing through the first insulating layer in response to the application of the negative voltage. Nonvolatile memory changed. 8. The nonvolatile memory device according to claim 7, wherein the negative voltage generation circuit generates the negative voltage at an external supply voltage of a constant voltage. 10. The nonvolatile memory as in claim 8, wherein the second value is not in a deflation state. And a plurality of blocks including a plurality of memory cells for storing information as a value of a threshold voltage, the plurality of blocks, an access unit for accessing the memory cells in the plurality of memory blocks, a voltage applying circuit and a verification unit. Each of the plurality of memory blocks further includes at least one word line and several data lines, each of the plurality of memory cells being coupled to one of the plurality of data lines and a first semiconductor region formed in a semiconductor substrate. A first insulating film covering at least a channel forming region between the second semiconductor region, the first semiconductor region and the second semiconductor region, formed on the first insulating film and extending over the first semiconductor region and the second semiconductor region The floating gate, the second insulating film formed on the floating gate, and the second insulating film; At least one control gate is coupled to one word line, and each of the plurality of memory cells has its threshold voltage changed from a first value to a second value by a threshold voltage change operation of applying a predetermined voltage to the control gate. And the access unit includes a selector for selecting at least one block of the plurality of blocks and a group including the at least one word line of at least one block of the plurality of blocks and the plurality of data lines. And a counter for sequentially selecting at least one group of lines selected from the group, wherein the voltage application circuit is configured to set the threshold value of at least one memory cell in the at least one block in the threshold voltage change operation. At least one coupled to at least one word line in the at least one block selected by the selector to change After applying the predetermined voltage to the memory cell and executing the threshold voltage change operation on a plurality of memory cells included in the at least one block selected by the selecting unit, the verification unit is configured by the selecting unit. Confirm the threshold values of the plurality of memory cells after the threshold voltage change operation included in the selected at least one block, and after the threshold voltage change operation, the threshold values of at least one memory cell in the at least one block The voltage is included in the at least one block selected by the selection unit selectively in response to the verification result for the block when the voltage is higher than the allowable maximum value of the second value, as indicated by the verification result of the verification unit. The voltage application circuit is again used for the threshold voltage change operation for several memory cells. Applying a positive voltage to said at least the non-volatile memory device as the threshold voltage is higher than the allowable minimum value lower than the allowable maximum value of the second value, the value of the number of memory cells included in one block. 11. The method of claim 10, wherein in response to the threshold voltage change operation, electrons in the floating gate are discharged from the floating gate by a tunnel effect passing through a first insulating film, whereby each of the threshold voltages of the plurality of memory cells is increased. Nonvolatile memory changed. The nonvolatile memory device of claim 11, wherein the predetermined voltage has an absolute value greater than the external supply voltage. The nonvolatile memory device according to claim 12, wherein the voltage application circuit generates the predetermined voltage of negative polarity at a positive external supply voltage. The nonvolatile memory device according to claim 13, wherein each of the plurality of blocks includes one word line. 15. The nonvolatile memory as in claim 14, wherein the second value of the memory cell is not in a deflation state.

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