KR0149578B1 - Time delay circuit for semiconductor memory device - Google Patents

Abstract

1. The technical field to which the disclosed invention of the claims belongs: A time delay circuit of a semiconductor memory device capable of effectively adjusting time delay as another time constant according to an operating voltage.

2. The technical problem to be solved by the invention: when the operating voltage of the circuit which is a problem of the conventional RC delay circuit and the temperature compensation RC delay circuit is reduced, that is, when the operating voltage is lower than the reference voltage (Low Vcc) The present invention provides a time delay circuit that arbitrarily adjusts a time delay according to a high and low operating voltage compared to a reference voltage according to the present invention by reducing an increase in time constant and an unnecessary time delay and speed delay.

3. Summary of the Invention The present invention provides a time delay circuit for a semiconductor memory device. A time delay circuit of a semiconductor memory device operated by input of first and second power supply voltages, comprising: level detecting means for outputting a level detection signal by detecting that the first power supply voltage changes below a predetermined reference voltage; Delay means for outputting the input signal to a common node which is operated by the input of the first and second power supply voltages, and is switched by the input of the level detection signal to convert the first power supply voltage and the second power supply voltage. And a time delay circuit of the semiconductor memory device having a time delay compensation means for inputting an operating voltage and buffering the input signal to the common node.

4. Significant Uses of the Invention: Used in time delay circuit devices for controlling the operation by appropriately delaying the time in a semiconductor memory device, and particularly suitable for semiconductor memory devices.

Description

Time delay circuit of semiconductor memory device

1 is a general RC delay circuit diagram.

2 is an RC delay circuit diagram having a general temperature compensation function.

3 is a circuit diagram of a time delay circuit according to an embodiment of the present invention.

4 is an operation timing diagram according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a time delay circuit that arbitrarily adjusts a time delay by having a time constant adapted to a level change of an operating voltage.

In general, when a word line is selected and a charge sharing occurs between a memory cell and a bit line in an operation in a semiconductor memory device, particularly a large memory device, the time delay circuit is used to ensure sufficient charge sharing thereof. do. At this time, the charge until the charge becomes the equipotential between the parasitic capacitor and the capacitor connected to the drain of the MOS transistor is called the charge sharing time (Charge Sharging Time). The time delay circuit is very important because it is used to adjust a signal race between signals in the chip. As such a time delay circuit, a delay circuit for delaying a signal by simply combining a gate and an RC delay circuit using a time constant of a resistor and a capacitor are frequently used. In particular, the RC delay circuit is the most commonly used time delay circuit because it is easy to adjust the degree of time delay with a metal layer option and a fuse option.

FIG. 1 is an RC delay circuit that is generally used in a conventional semiconductor memory device.

Referring to FIG. 1, at least one inverter 17, 37, 57 is connected in series between the input terminal 1 and the output terminal 70 in the RC delay circuit.

The inverters 17, 37, and 57 are provided with a first power supply voltage 2 and a second power supply for inputting a first power supply voltage 2, for example, an internal power supply voltage Vcc capable of operating a semiconductor memory device. The voltage 4 is connected between the second power supply voltage 4 for inputting the ground voltage Vss of the semiconductor memory device, for example. Resistors 8, 13 and 33 are connected between one side of the inverters 17, 37 and 57 and the first power supply voltage 2 terminal, respectively, and the other side of the inverters 17, 37 and 57. Resistors 11, 14, and 99 are connected between the terminals of the second power supply voltage 4, respectively. In addition, a connection node 21 for connecting the inverter 17 and the inverter 37, a connection node 28 for connecting the inverter 37 and the inverter 57, and the second power voltage 4. Capacitors 6, 12, and 18 are connected between each of the terminals. A capacitor 18 is connected between the connecting node 31 on the output line of the inverter 57 and the terminal of the second power supply voltage 4. In addition, the inverters 17, 37, and 57 are constituted by drain connections of the PMOS transistor and the NMOS transistor. The first power supply voltage 2 is applied to one side of the resistors 8, 13, and 33 and the sources of the PMOS transistors of the inverters 17, 37, and 57, and the second power supply voltage is respectively applied to the resistors ( 11, 14, 99 and one of the sources of the EnMOS transistor of the inverters 17, 37, 57. Thus, the RC delay circuit of FIG. 1 is ready for operation. That is, it is set up.

The operation of the RC delay circuit according to FIG. 1 now begins.

First, a low input signal is input to the input terminal 1 and the input signal is input to the gates of the PMOS and NMOS transistors of the inverter 17 set up. Accordingly, the first power supply voltage 2 applied to the source of the PMOS transistor of the inverter 17 is connected to the connection node through the source-drain channel of the PMOS transistor formed by the low signal input to the gate. 21 is supplied. Thus, the PMOS transistor is turned on. Meanwhile, in the NMOS transistor of the inverter 17, the gate does not form a source-drain channel due to the input signal of the row input to the gate of the NMOS transistor. Therefore, even if the second power supply voltage 4 is supplied to the source of the enMOS transistor, the enMOS transistor is turned off. The capacitor 6 is supplied with the first power supply voltage 2 so that the positive charge of the first power supply voltage 2 is charged to the first power supply voltage 2 level. The time constant RC represents a time delay caused by the positive charge supplied by the first power supply voltage 2 passing through the resistor 8 and being charged to the capacitor 6 through the source-drain channel of the PMOS transistor. It can be represented as. That is, the time delay until the positive charge supplied from the first power supply voltage 2 passes through the resistor 8 to start charging from the connection node 21 to the capacitor 6 is a time constant. Therefore, the time that the input signal input to the gate of the PMOS transistor is transferred to the connection node 21 through the channel of the PMOS transistor operated by the first power supply voltage 2 is the time constant. Delay. The connection node 21 has a signal having a high voltage level. Accordingly, the inverted high signal of the input signal is output to the connection node 21.

On the other hand, after the above operation, the input signal different from the above-described input signal is sequentially input to the input terminal 1, and the input signal of the PMOS and NMOS transistors of the inverters 17 set up. Each is input to a gate.

Accordingly, the second power supply voltage 4 applied to the source of the NMOS transistor of the inverter 17 forms a channel between the source and drain of the NMOS transistor which is formed by the high signal input to the gate. It is supplied to the connection node 21 through. Thus, the NMOS transistor is turned on. At this time, the positive charge charged in the capacitor 6 is bypassed to the second power supply voltage 2 terminal through the drain-source channel of the enMOS transistor of the inverters 17. Meanwhile, the PMOS transistor of the inverters 17 does not form a channel between the source and the drain due to the high input signal input to the gate of the PMOS transistor. For this reason, the PMOS transistor is turned off even when the first power supply voltage 2 is supplied to the source of the PMOS transistor. In the capacitor 6, the positive charge is continuously bypassed to the second power supply voltage 4 Vss terminal and discharged to the second power supply voltage 4 level. The time delay caused by the positive power being discharged from the capacitor 6 and passing through the resistor 8 through the second power supply voltage 4 terminal is referred to as the time constant RC. That is, the positive charge charged in the capacitor 6 is discharged to the second power supply voltage 4 Vss terminal, passes through the drain-source channel of the NMOS transistor, and passes through the resistor 8 to the second terminal. The time delay is the time delay from the time when the bypass is started to the power supply voltage (4) Vss terminal to the discharge of the second power supply voltage (4) Vss terminal. Accordingly, the time constant of the input signal input to the gate of the NMOS transistor is transferred to the connection node 21 through the channel of the PMOS transistor operated by the second power supply voltage 4. Delayed by. The positive charge of the capacitor 6 begins to bypass the second power supply voltage 4 terminal to be discharged to the second power supply voltage level 4 so that the connection node 21 is connected to the second power supply voltage 4. Level). That is, the connection node 21 has a signal having a low voltage level. Accordingly, the inverted low signal of the input signal is output to the connection node 21.

Thus, the RC delay circuits in the case where the input signal is low and high are described. When the input signal is low and high, each subsequent operation is performed when the input signal is low and high.

That is, the inverters 37., 57, resistors 13, 14, 33, 99, and capacitors constituting the next RC delay circuit following the RC delay circuits in the case where the input signal is low and high in this case. 12 and 18 are sequentially operated to sequentially output the inverted and time-delayed output signals from the connection node 28 and the output terminal 70 with respect to the input signals.

However, the RC delay circuit shown in FIG. 1 changes the time delay degree according to the threshold voltage and the operating voltage of the PMOS and ENMOS transistors constituting the insides of the inverters 17, 37, and 57. There is a problem.

Since the charge sharing time at the input operating voltage is a high voltage in a region where the first power supply voltage, which is the operating voltage, becomes higher than the reference voltage Vref level (hereinafter, High Vcc), the charge sharing time is shortened and is the operating voltage. In the area where the one power supply voltage falls below the reference voltage Vref level (hereinafter, Low Vcc), the charge sharing time becomes long because the voltage is relatively low. This is a problem of causing a column failure due to the lack of the charge sharing time in the Hign Vcc region and a speed delay due to the increase of the charge sharing time in the Low Vcc region. In addition, even when a time delay is not required as the operating voltage becomes the low Vcc, there is a problem in that an overall speed delay occurs as a signal delay occurs according to the operating voltage.

2 is a temperature compensation circuit to compensate for a time delay difference with respect to a change in threshold voltages of the PMOS and ENMOS transistors. FIG. 2 is described in detail on pages 1991-31 of 1991 SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS, issued May 30, 1991.

In the circuit shown in FIG. 2, as described in the technical paper, as the temperature increases, the threshold voltage of the MOS transistors decreases, and the on-resistance of these MOS transistors increases inversely with the temperature, resulting in a decrease in temperature. Accordingly, the threshold voltages of the MOS transistors are lowered, thereby reducing the temperature dependence rate by compensating time (hereinafter, referred to as time constant) as the turn-on resistance of the PMOS transistor as an input thereof is lowered. However, even in such a case, when the operating voltage decreases, there is a problem in that the time constant cannot be increased.

The problem that occurs in the conventional circuit as described above, that is, the problem that the delay time constant changes as the power supply voltage is changed causes an excessive speed delay in the semiconductor memory device, in particular, the DRAM.

Accordingly, an object of the present invention is to provide a time delay having a different time constant by adapting to the level change even if the level of the operating voltage for operating the semiconductor memory device changes.

According to the present invention for achieving the above object, in the time delay circuit of a semiconductor memory device, the level detection for outputting a level detection signal by detecting that the operating voltage of the first power supply level is changed below a predetermined reference voltage Means, delay means for delaying the input signal and being output by the input of the first and second power supply voltages to the common node, and switching by the output of the level detection signal, the first power supply voltage and the second power supply. And time delay compensating means for buffering an input signal to the common node using a voltage as an operating voltage.

Hereinafter, with reference to the accompanying Figure 3 a preferred embodiment of the present invention will be described in detail. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings.

Figure 3 illustrates the configuration of one embodiment for achieving the object of the present invention.

In addition to the conventional RC delay circuit, the time delay circuit shown in the above embodiment forms another path using the time delay compensation means 27 for the signal detected and output by the level detector 9 to reduce the time constant. Operate the circuit quickly.

Now, when the first power supply voltage 2 and the second power supply voltage 4 are input to the circuit configured as shown in FIG. 3, the first power supply voltage 2 is formed in the time delay compensation circuits 26 and 67. It is supplied to the source of the OS transistors 25 and 55. In addition, the first power supply voltage 2 is supplied to the sources of the PMOS transistors 5 and 35 in the CMOS inverters 17 and 57 through the resistors 8 and 13. The second power supply voltage 4 is supplied to the sources of the NMOS transistors 10 and 40 in the CMOS inverters 17 and 57 through the resistors 11 and 14. By the above operation, the time delay circuit of FIG. 3 is ready for operation. That is, it is set up.

On the other hand, the level detection signal (hereinafter referred to as? DET) detected by the level detector 9 compares the first power supply voltage 2 with a preset reference voltage Vref, and the first power supply voltage 2 is set in advance. If the voltage is higher than Vref, the? DET is output to logic low. If the first power supply voltage 2 is lower than the preset reference voltage Vref, the level detector 9 outputs the? DET of high. Referring to FIG. 4 according to FIG. 3, the øDET is represented by logic low and high as the first power supply voltage 2 Vcc is higher and lower than the reference voltage Vref.

When a low signal is input to the input terminal 1 while the? DET output from the level detector 9 is low because the first power supply voltage 2 is high, a gate is connected to the input terminal 1. The PMOS transistor 5 in the CMOS inverter 17 is turned on, and the NMOS transistor 10 is turned off. At this time, the PMOS transistor 25 in the time delay circuit 27 is not operated. This is because the inverter 80 inverts the? DET of the row output from the level detector 9 to block the source-drain channel of the PMOS transistor 25, thereby reducing the power supply voltage in the CMOS inverter 37. This is because the supply is cut off. Accordingly, the positive charge of the first power supply voltage 2 is charged to the capacitor 6 through the channel of the resistor 8 and the PMOS transistor 5. When the capacitor 6 is fully charged with the positive charge, the capacitor 6 is charged up to the first power voltage 2 level. The input signal has a delay time as much as the time constant by the time constant which is the time when the positive charge passes through the resistor 8 and the time delay until the capacitor 6 is charged.

Then, the voltage of the first power supply voltage (2) level is supplied to the connection node (21). As a result, the logic low state, which is the input signal, is inverted to a logic high state and output to the connection node 21. Referring to FIG. 4 with reference to FIG. 3, the time until the? DET changes from a low state to a high state becomes T1 in FIG. 4, and the input signal IN The delayed time of the output signal OUT when changing from the low state to the high state becomes TD1 in FIG. The delayed time is the same as in the conventional RC delay circuit of FIG.

When a high signal is inputted to the input terminal 1 while the? DET output from the level detector 9 is low, the CMOS inverter (using the logic high signal of the input terminal 1 as an input signal) is input. 17 is input to the gates of the PMOS transistor 5 and the NMOS transistor 10 in FIG. Thus, the NMOS transistor 10 to which the logic high as the input signal is input is turned on, and the PMOS transistor 5 is turned off. At this time, the enMOS transistor 30 in the time delay circuit 17 is not operated.

This is because the? DET of the row output from the level detector 9 blocks the source-drain channel of the enMOS transistor 3. The positive charge is supplied to the connection node 21 while the positive charge charged in the capacitor 6 is discharged. Accordingly, the positive charge passes through the drain-source channel of the NMOS transistor 10, passes through the resistor 11, and is grounded and discharged to the second power supply voltage 4 terminal. Thus, the connection node 21 is in a logic low state. The input signal has a delay time as much as the time constant by the time constant which is the time when the positive charge passes through the resistor 11 and the time delay until the capacitor 6 is discharged. Accordingly, the logic high signal of the input signal is inverted into a logic low signal and output to the connection node 21.

Subsequently, an input signal that is a voltage level of the second power supply voltage 4 of the connection node 21, that is, a logic low signal, is the PMOS transistor 35 and the NMOS transistor 40 in the CMOS inverter 57. Is input to the gate. The PMOS transistor 35 in the CMOS inverter 57 to which the gate is connected is turned on, and the NMOS transistor 40 is turned off. At this time, the PMOS transistor 55 in the time delay circuit 67 is not operated.

Because the inverter 80 inverts the? DET of the row output from the level detector 9 to block the source-drain channel of the PMOS transistor 55, thereby reducing the power supply voltage in the CMOS inverter 77. This is because the supply is cut off. Accordingly, the positive charge of the first power supply voltage 2 is charged to the capacitor 3 through the channel of the resistor 13 and the PMOS transistor 35. When the capacitor 3 is fully charged with the positive charge, the capacitor 3 is charged to the first power voltage 2 level. The input signal has a delay time as much as the time constant by the time constant that is the time when the positive charge passes through the resistor 13 and the time delay until the capacitor 3 is charged and discharged again. The capacitor 3 starts to be discharged and the voltage of the first power supply voltage 2 level is supplied to the connection node 44. Thus, the logic low state, which is the input signal, is inverted to a logic high state and output to the connection node 44.

Accordingly, the logic low signal of the input signal is inverted to a logic high signal and output to the output terminal 70.

The process of inputting the low signal and the high signal to the input terminal 1 while the? DET output from the level detector 9 described above is low is performed in the conventional RC delay circuit shown in FIG. Same as the time delay effect.

In a case different from the above case, if the low power signal is input to the input terminal 1 while the? DET output from the level detector 9 is high because the first power supply voltage 2 is low, the input is performed. The PMOS transistor 5 in the CMOS inverter 17 having a gate connected to the terminal 1 is turned on, and the NMOS transistor 10 is turned off. At this time, in the PMOS transistor 25 in the time delay circuit 27, a signal of the logic low in which the? DET output from the level detector 9 is inverted by the inverter 80 is input to the gate. Accordingly, the PMOS transistor 25 forms a channel between the source and the drain and is turned on. On the other hand, the CMOS inverter 37 is connected in parallel with the CMOS inverter 17, the gates are connected to the input terminal (1). At the same time, the PMOS transistor 15 in the CMOS inverter 37 is turned on by receiving the power supply voltage from the drain of the PMOS transistor 25. Accordingly, the positive charge of the first power supply voltage 2 is charged to the capacitor 6 through the channel of the resistor 8 and the PMOS transistor 5. At the same time, the positive charge of the first power supply voltage 2 is charged to the capacitor 6 through the channel of the PMOS transistor 25 and the channel of the PMOS transistor 15. Thus, when the capacitor 6 is fully charged with the positive charge, it is charged up to the first power voltage 2 level. At this time, the capacitor 6 is charged to the first power supply voltage 2 level faster than when the? DET in the conventional RC delay circuit is logic low and the input signal is logic low.

Because the resistance component of the PMOS transistor 25 in the time delay circuit 27 is much smaller than the resistance component of the resistor 8, the time delay circuit ( This is because the time to pass through the channel of the PMOS transistor 25 in 27 is much faster.

The input signal has a delay time as much as the time constant by the time constant which is the time when the positive charge passes through the resistor 8 and the time delay until the capacitor 6 is charged. For the same reason, the RC delay circuit having the time delay circuit 27 has the time constant smaller than that of the conventional RC delay circuit as shown in FIG. Therefore, unnecessary delay time can be reduced. Then, the capacitor 6 starts to be discharged and the voltage of the first power supply voltage 2 level is supplied to the connection node 21. As a result, the logic low state, which is the input signal, is inverted to a logic high state and output to the connection node 21. Referring to FIG. 4, the delayed time of the output signal OUT when the input signal IN is changed from the low state to the high state is TD2 in FIG. 4. do. The delayed time is shorter than the delay time of the conventional RC delay circuit of FIG. 1, which is more effective by reducing unnecessary signal delay.

In addition, the voltage level of the first power supply voltage 2 of the connection node 21, that is, the logic high signal, is the gate of the PMOS transistor 35 and the NMOS transistor 40 in the CMOS inverter 57. Is entered. Thus, the NMOS transistor 40 to which the logic high as the input signal is input is turned on, and the PMOS transistor 35 is turned off. At this time, the øDET output from the level detector 9 is inputted to the NMOS transistor 60 in the time delay circuit 67 by a logic high signal. Thus, the NMOS transistor 60 is turned on by forming a channel between the source and the drain. On the other hand, the CMOS inverter 77 is connected in parallel with the CMOS inverter 57 and the gates are connected to the connection node 21. At the same time, the NMOS transistor 50 in the CMOS inverter 77 is turned on by receiving the second power supply voltage 4 Vcc from the drain of the NMOS transistor 60. The positive charge is supplied to the connection node 44 while the positive charge charged in the capacitor 3 is discharged. Accordingly, the positive charge passes through the drain-source channel of the NMOS transistor 40, passes through the resistor 14, and is grounded and discharged to the second power supply voltage 4 Vss terminal. Thus, the connection node 44 is in a logic low state. The input signal has a delay time as much as the time constant by the time constant which is the time when the positive charge passes through the resistor 14 and the time delay until both the capacitor 3 is discharged. At the same time, the positive charge of the connection node 44 is discharged to the Vss terminal of the second power supply voltage 4 through the channel of the NMOS transistor 50 and the channel of the PMOS transistor 60. Thus, when the capacitor 3 discharges all of the positive charges, it is discharged to the second power supply voltage level 4. At this time, the positive charge of the capacitor 3 returns to the second power supply voltage 2 level sooner than when the? DET in the conventional RC delay circuit is logic low and the input signal generated in the connection node 21 is logic high. Discharged. Because the resistance component of the enmo transistor 60 in the time delay circuit 67 is much smaller than the resistance component of the resistor 14, the time delay is greater than the time that the positive charge passes through the resistor 14. This is because the time passing through the channel of the enMOS transistor 60 in the circuit 67 is much faster. For the same reason, the RC delay circuit having the time delay circuit 67 has the time constant smaller than that of the conventional RC delay circuit as shown in FIG. The delayed time is shorter than the delay time of the conventional RC delay circuit of FIG. 1, which is more effective by reducing unnecessary signal delay. Therefore, in the case of the present invention, unlike the conventional case, since the time delay circuit having a time delay (time constant) is implemented at a voltage lower than the reference voltage of the first power supply voltage, that is, the Vcc, the conventional problem is realized. Can be solved.

4 is a waveform diagram of an operation signal of FIG. 3 according to time.

Referring to FIG. 3, when the first power supply voltage 2, that is, Vcc (A) is a voltage region T1 higher than the reference voltage B, the level detection signal C is output low and an input signal is output. When the (D) transitions from low to high, the level detection signal (C) when the delay time (TD1) and Vcc (A) in the voltage region (T2) lower than the reference voltage (B) in the output signal (E) accordingly. Is output as high and when the input signal D transitions from low to high, the respective delay time TD2 is compared in the output signal E according to the high voltage region T1 when the low voltage region T2 is compared. The delay time is shorter than that of).

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Particularly, in the embodiment of the present invention, the case in which two are connected in series as a basic circuit is illustrated, but it is possible to connect several circuits in series. In addition, a time delay circuit can be configured by providing several operating temperature sensing functions in a chip. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims below, but also by the equivalents of the claims.

According to the present invention as described above, in the general delay circuit and temperature compensation circuit, if the operating voltage (Vcc) is lower than the reference voltage, even if time delay is not necessary, the overall speed delay occurs according to the operating power supply voltage. Especially in the case of low power supply voltage, time delay can be effectively reduced.

For example, the present invention is limited to the above-described drawings, but it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (6)

A time delay circuit of a semiconductor memory device, comprising: level detecting means for detecting a change in an operating voltage of a first power supply voltage level below a predetermined reference voltage and outputting a level detection signal; and input of first and second power supply voltages; A delay means for delaying the input signal to be output to the common node and a signal input by switching the level detection signal and the output and inputting the first power supply voltage and the second power supply voltage as operating voltages. And a time delay compensating means for buffering the node. The time delay circuit of a semiconductor memory device according to claim 1, wherein said level detecting means operates during the operation of said semiconductor memory device. 2. The time delay circuit of the semiconductor memory device according to claim 1, wherein the level detecting unit operates by receiving an input of an external signal informing the start of access. The semiconductor device according to claim 1, wherein the delay means comprises inverting means for inverting an input signal and outputting the signal to the common node, and a MOS capacitor connected between the common node and the second power supply voltage. Time delay circuit of the memory device. The method of claim 4, wherein the inverting means comprises: resistors having one side connected to each of the first power supply voltage terminal and the second power supply voltage terminal, each source being connected to the other side of the resistors, and a drain being connected to the common node. And a first CMOS inverter comprising a first PMOS transistor and a first NMOS transistor for inverting a signal connected to the gate and outputting the inverted signal to the common node. The method of claim 1, wherein the time delay compensating means includes a drain between the second CMOS inverter connected in parallel to the first CMOS inverter, the second power voltage terminal of the second CMOS inverter, and the second power voltage. A third NMOS transistor having a channel between the sources, and a third PMOS transistor having a channel between the source and the drain between the first power supply voltage and the first power supply voltage terminal of the second CMOS inverter; And each of the third NMOS transistor and the third PMOS transistor is switched in response to the level detection signal and an inversion signal thereof input to the gate.