KR0145853B1 - Image processing system with data bus for image private use and the method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an image processing system having at least two modules for transmitting image data to each other for processing unique image data, and a control method thereof.

2. Technical problem to be solved by the invention

An image processing system and a control method thereof capable of processing a large amount of image data at high speed are provided.

3. Summary of Solution to Invention

In addition to the system bus of the image processing system, image data is transmitted between modules through an image data bus for exclusively transmitting image data.

4. Important uses of the invention

It is used to process a large amount of image data at high speed in an image processing system.

Description

Image Processing System with Data Bus for Image and its Control Method

1 is a block diagram of a general image processing system

2 is a block diagram of an image processing system having an image data bus according to the present invention.

3 is a diagram illustrating an interface of an image data bus according to the present invention.

4 is an arbitration flowchart of an image data bus according to the present invention.

5 is a timing diagram of an arbitration operation of an image data bus according to the present invention.

6 is a circuit diagram of a bus arbitrator in FIG.

7 is a data transfer count circuit diagram of FIG.

8 is a control state detection circuit diagram of FIG.

9 is a circuit diagram of the bus master in FIG.

10 is an operation timing diagram of each part of FIG.

FIG. 11 is a circuit diagram showing a transmission request and a source confirmation signal in FIG.

12 is an operation timing diagram of each part of FIG.

FIG. 13 is a detailed circuit diagram of a transmission ready signal generating circuit in FIG.

14 is an operation timing diagram of each part of FIG.

FIG. 15 is a detailed circuit diagram of a transmission reserve processing circuit in FIG.

16 is a detailed circuit diagram of the control state decoding circuit in FIG.

FIG. 17 is a circuit diagram of a read signal generation circuit in FIG.

18 is an operation timing diagram of each part of FIG. 17.

19 is a detailed circuit diagram of the read control circuit in FIG.

20 is a detailed circuit diagram of the bus use detection circuit of FIG.

21 is an operation timing diagram of each part of FIG. 20

22 is a circuit diagram of a bus slave in FIG.

23 is an operation timing diagram of each part of FIG.

24 is a circuit for generating a destination confirmation signal in FIG.

FIG. 25 is an operation timing diagram of each part of FIG. 24

FIG. 26 is a detailed circuit diagram of the control state decoding circuit of FIG.

FIG. 27 is a write signal generation circuit diagram of FIG.

28 is an operation timing diagram of each part of FIG.

FIG. 29 is a detailed circuit diagram of the light control circuit in FIG. 27. FIG.

30 is a block diagram of an image processing system showing an example of applying an image data bus according to the present invention.

* Explanation of symbols for main parts of the drawings

200: image data bus 202: bus arbiter

204: system bus MST: bus master

SLV: Bus Slave

The present invention relates to an image processing system, and more particularly, to an image processing system having at least two modules for transmitting image data to each other for processing unique image data, and a control method thereof.

In general, an image processing system such as a facsimile, a multimedia computer system, or the like, includes a plurality of modules for performing different unique image data processing functions. The modules transmit image data to each other for image data processing. The image processing system connects the song modules for image processing to the system bus and relays the image data between the modules in a bus master such as a CPU (Central Proccessint Unit) or DMA (Direct Memory Access). Per pixel is transmitted for each block. The system bus is a conventional back plane bus. At this time, since the program execution bus cycle for operating the system also occurs through the same system bus, the program controlling the system should be stopped when data transfer is required. It also has a structure in which the CPU controls the data transfer to the program.

As an example of such an image processing system, a configuration of a conventional color facsimile is shown in FIG. The color facsimile of FIG. 1 uses the modules for image processing, that is, the color scanner 102, the color compensator 104, the page memory 106, the encoder 108, the decoder 112, and the color printer 114. It is connected to the system bus 118 to transfer the image data for each pixel or block between the modules under the relay of the CPU 100. At this time, since the program execution bus cycle for operating the system also occurs through the system bus 118, the program controlling the system should be stopped when data transmission is required. The CPU 100 also controls the data transfer. For example, in order to transfer the data input from the color scanner 102 to the page memory 106, it is transmitted to the page memory 106 by pixel or block or line by execution of a program or by use of a DMA. Done.

As described above, in the related art, a cycle for executing a system control program and a cycle for transferring data between components are all performed through one same bus. Accordingly, in order to improve the performance of the program, the data transmission in the pixel unit is not suitable for processing a large amount of data due to the decrease in the transmission efficiency. In addition, when the block data is transmitted using DMA or the like to increase the transmission efficiency, the program execution is stopped, which is not suitable for the task requiring real time processing. In addition, it is difficult to design hardware and software in consideration of the above problems, and there are complex problems.

Accordingly, an object of the present invention is to provide an image processing system and a control method thereof capable of processing a large amount of image data at high speed in an image processing system.

Another object of the present invention is to provide an image processing system and a method of controlling the same, which can improve data transmission speed by transmitting image data between separate modules of an image processing system through a separate dedicated passage.

The present invention for achieving the above object is characterized by transmitting the image data between the respective modules through the image data bus for transmitting only the image data separately from the system bus of the image processing system.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description, it should be noted that like elements in the drawings represent like reference numerals wherever possible. Also in the following description, numerous specific details such as specific circuit configurations, number of bits or bytes, frequency, logic state, operating timings, etc. are shown to provide a more general understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

First, as shown in FIG. 2, the present invention provides data transmission through an independent image data bus 200 and an image data bus 200 that process only image data in block units separately from the system bus 204 of the image processing system. The transmission speed is improved by transmitting image data between the modules M1 to Mn using the controlling bus arbiter 202. The modules M1 to Mn may be the same as the scanner 102, the color compensator 104, the page memory 106, the encoder 108, the decoder 112, the color printer 114, and the like shown in FIG. This module has a unique video data processing function. Control of data transmission on the image data bus 200 is performed by the bus arbiter 202. The source and destination in the image data bus 202 may be organized systematically according to the operation of the system. Since the number of cases is not large, the image data bus 200 may be a relatively simple logic circuit. Control becomes possible. The source refers to the source of the data, i.e. the module transmitting the data and the destination refers to the end of the data, i.e. the module receiving the data. It also simplifies the software by letting the CPU deviate from the execution of the program for its control.

The image data bus 200 basically has a multi-master bus structure. Accordingly, each of the modules M1 to Mn includes a bus master 206 and a bus slave 208. The bus arbiter 202 selects a destination module in response to a request of the bus master by the source module, and arbitrates transmission of image data through the image data bus 200 between the bus master of the source module and the bus slave of the destination module. . The bus arbiter 204 also processes the data transfer request according to the priority of the task currently being performed and allows it to perform a data transfer cycle if the required destination module can receive the data. The bus master 206 receives the image data of its module 210 through the image data bus 200 under the arbitration of the bus arbiter 202 in response to the transmission start signal from the module 210 being applied. Send to the appropriate destination module if possible. The bus slave 208 receives image data from the bus master of the source module, which has requested transmission start when its module 210 is selected as a module, and receives the image data through the image data bus 200 to its module 210. Is authorized.

As described above, the bus master (MST) and the purpose of the source module for transmitting the image data through the image data bus 200 is a detailed interface configuration between the slave (SLV) and the bus arbiter 202 of the module. Shown in The bus master MST corresponds to the bus master of the source module in the configuration shown in FIG. 2 and the bus slave SLV corresponds to the bus slave of the destination module in the configuration shown in FIG. Signals /XFR_REQ.SID for the presence or absence of data to be transmitted by the source module for the interface between the bus master (MST) of the source module and the slave (SLV) of the destination module and the bus arbiter 202 and the possibility of receiving data of the destination module. The signal DID for checking the back, the signals SAD, DAD, / AS to inform the determined bus master and bus slave, the data bus D [23: 0] for data transfer, and the signal / IN_USE to indicate that the bus is busy. And signals / RD, / WR for reading and writing block data, and bus status signals / STA [2: 0] for control. In addition, the address line is omitted using the characteristics of the block data.

The bus master MST is connected to the corresponding module through the data bus D [23: 0], applies the address SADDR [12: 0] to the corresponding module, and inputs a transmission start signal / XFR_SRT from the corresponding module. The bus master (MST) is also connected to the image data bus 200 via the data bus D [23: 0] and from the bus arbiter 202 via the image data bus 200 to the source address SAD [3: 0]. And control status signal / STA [2: 0] and reset signal / REST and click CLK and address strobe signal / AS and counter reset signal / CT_RS and transmission completion signal / UNDER_F and input image data bus 200. The write signal / WR is inputted from the bus slave (SLV) through the transmission request signal / XFR_REQ and the source confirmation signal / SID, and applied to the bus arbiter 202 through the image data bus 200. The RD, the source transfer end signal / SXFR_END and the write end signal WR_END are generated and applied to the bus slave SLV through the image data bus 200. The bus master MST also applies the source transfer termination signal / SXFR_END to the bus arbiter 202 via the video data bus 200 as a bus use status signal / IN_USE.

The bus slave SLV is connected to a corresponding module through the data bus D [23: 0], applies an address SADDR [12: 0] to the corresponding module, and inputs a transmission control signal / XFR_CONT from the corresponding module. The bus slave (SLV) is also connected to the video data bus 200 via the data bus D [23: 0], and the destination address DAD [3: 0 from the bus arbiter 202 via the video data bus 200. ] And the control status signal / STA [2: 0] and the reset signal / RESET and clock CLK address strobe signal / AS, and the read signal / RD and source from the bus master (MST) through the image data bus 200. Input transmission end signal / SXFR_END and write end signal WR_END, input read signal / RD and source transfer end signal / SXFR_END and write end signal WR_END from bus master (MST) through video data bus 200, and confirm the destination The signal / DID and are generated and applied to the bus arbiter 202 through the image data bus 200, and the write signal / WR is generated and applied to the bus master MST through the amount.

The bus arbiter 202 is connected to the video data bus 200 via data bus D [23: 0] and generates a source address SAD [3: 0], a counter reset signal / CT_RS, and a transmission completion signal / UNDER_F. To the bus master (MST) via the image data bus (200) to generate the destination address DAD [3: 0] and to the bus slave (SLV) through the image data bus (200), and control status signal / Generates STA [2: 0], reset signal / RESET, clock CLK, and address strobe signal / AS and applies it to bus master (MST) or bus slave (SLV) via video data bus 200, The transmission request signal / XFR_REQ and read signal / RD are input from the bus master MST through the 200. The bus arbiter 202 also inputs the source transfer termination signal / SXFR_END of the bus master MST as the bus use status signal / IN_USE through the video data bus 200.

Now, the signals described above will be described. Data bus D [23: 0] is a 24-bit color image data line of 8 bits each for R, G, and B. The data bus D [23: 0] is an example in which the system is a color image processing system. The 4-bit source address SAD [3: 0] is a signal for the bus arbiter 202 to determine the bus master to use the image data bus and inform the bus masters. The 4-bit destination address DAD [3: 0] is a signal for the bus arbiter 202 to determine the bus slave to use the video data bus and inform the bus slaves. The reset signal / RESET bus arbiter 202 is a signal for resetting modules connected to the image data bus 200. The clock CLK is provided from the bus arbiter 202 and is a system clock. The address strobe signal / AS is the source address SAD [3: 0] or the destination address DAD [3 determined to use the image data bus 200 from the bus arbiter 202 to the bus master (MST) or bus slave (SLV). Signal used to send: 0]. The write signal / WR is a signal used to write the image data stored in the line buffer on the bus master (MST) side to the line buffer on the bus slave (SLV) side. The read signal / RD is a signal for reading data of the corresponding module from the bus master (MST) side and storing it in its own line buffer. The counter reset signal CT_RS is generated as a pulse generated by the bus arbiter 202 after transmitting the number of bytes of data to be transmitted. The transmission completion signal UNDER_F is also generated as a signal generated by the bus arbiter 202 after transmitting the number of bytes of data to be transmitted. The transfer request signal / XFR_REQ is a signal for requesting the bus arbiter 202 to send data to the bus slave (SLV) after the bus master (MST) fills the data in the line buffer. The source acknowledgment signal / SID is a signal that the bus arbiter 202 responds to in a corresponding bus master (MST) after receiving the transmission request signal / XFR_REQ. The destination acknowledgment signal / DID responds to the corresponding bus slave (SLV) when the bus arbiter 202 inquires the destination inquiry signal / D_ASK to check the available bus slave (SLV) after receiving the transmission request signal / XFR_REQ. It is a signal. The source transfer end signal / SXFR_END and the write end signal WR_END are signals indicating that the pair of bus masters MST and bus slaves SLV are using the image data bus 200, and the bus arbiter 202 Inputs the source transfer termination signal / SXFR_END as the bus use status signal / IN_USE to check whether the image data bus 200 is used. The 13-bit address SADDR [12: 0] is an address designating the data storage area of the line buffer in the bus master MST or bus slave SLV, respectively. The transmission start signal / XFR_SRT is a signal that the module fills all the data in the line buffer and informs its bus master (MST) to start the transmission. The transmission control signal / XFR_CONT is a signal for notifying the bus slave (SLV) of the module that the line buffer is finished. The three-bit control state signal / STA [2: 0] is a signal representing the state of the video data bus 200 and represents six states as shown in Table 1 below.

Looking at the protocol (protocol) of the image data bus 200 according to the present invention. First, different IDs (IDs) and ID bits are allocated to the modules M1 to Mn through the data lines D [23: 0], for example, as shown in Table 2 below. The ID address and ID bits are assigned to identify each module.

Now, with reference to FIG. 4 showing the mediation flowchart of the image data bus 200 according to the present invention and FIG. 5 showing the timing diagram of the mediation operation for the image data bus 200, the image data bus arbitration and data transmission will be described. When any module in the system wants to transmit data, the bus master of that module applies a transmit request signal / XFR_REQ to the bus intermediary 202. Then, the bus arbiter 202 checks whether the transmission request signal / XFR_REQ is 0, and if it is 0, the source inquiry signal / S_ASK (SSTA [2: 0] ==) at steps (S1) to (S2). 1) to find out which bus masters requested data transfer. Next, in step S3, a destination inquiry signal / D_ASK (where / STA [2: 0] = 11) is generated to find out which bus slave can receive data. Subsequently, the bus masters MST and the bus slaves SLV are determined at the earliest locations by comparing the priority of the bus masters that have requested data transmission in steps S4 to S5. When this is done, the bus arbiter 202 loads the IDs of the selected bus master (MST) and bus slave (SLV) on the source address SAD [3: 0] and destination address DAD [3: 0] lines, giving the address strobe / AS signal. Send to each module with Each module then knows whether it is selected. After that, the bus arbiter 202, together with the source memory addressing signal SMA (in this case / STA [2: 0] = 10), starts the bus master MST and the destination memory addressing signal DMA in this case. With the traffic notification signal XFC (where / STA [2: 0] = 100) to specify the start address of the bus slave (SLV) with / STA [2: 0] = 110 and program the number of bytes of data to be transmitted. Export the transfer count. After all processes are determined through this process, the transmission start signal SRT (/ STA [2: 0] = 101) is generated to start transmission between the determined bus master (MST) and the bus slave (SLV) (step S8). As shown in FIG. 5, the read signal / RD and the write signal / WR signal are generated between the modules selected in FIG. 5 to perform data transmission. At this time, the bus master (MST) using the image data bus 200 sends a bus use status signal / IN_USE to the bus arbiter 202 to inform that the bus is busy.

The bus arbiter 202 as described above is used to interface the system bus 204 and the image data bus 200 with the CPU 212, the data transfer count circuit 214, and the multiplexer as shown in FIG. 216 and 218, a program RAM 220 and a data RAM 222. The CPU 212 downloads the arbitration program and the data table from the main program of the image processing system to the program RAM 220 and the data RAM 222 through the system bus 204, respectively. The CPU 212, which has downloaded the program from the main program, initializes itself, resets the peripheral masters and slaves by applying the / RESET signal, and waits for the transmission request signal / XFR_REQ from each master. The data transfer count circuit 214 is a circuit for counting the number of data transfer bytes input to the bus arbiter 202 and includes a control state detection circuit 224 and a counter CNT1 as shown in FIG. The control state detection circuit 224 includes inverters IN1 to IN5, NAND gates NAND1 and NAND2, and flip-flops FF1 and FF2 as shown in FIG.

The above-described bus master (MST) will now be described in more detail. The bus master MST includes a transfer request and source confirmation signal generation circuit 226, an oragate OR1 to OR3, a read signal generation circuit 228, a bus use detection circuit 230, and an address counter as shown in FIG. CNT2). Referring to FIG. 10 showing the operation timing of each part of the bus master MST, the module to be transmitted fills all the data in the line buffer and sets the transmission start signal / XFR_SRT low to its bus master MST. send. Upon receiving this signal, the bus master (MST) generates a transmission request signal / XFR_REQ and sends it to the bus arbiter 202. From the bus arbiter 202, the source inquiry signal / S_ASK (where / STA [2: 0] = 1 ), It sends out the source confirmation signal SID. In addition, the bus arbiter 202 determines a bus master (MST) to use the image data bus 200, and gives each master a source address SAD [3: 0]. Compare and find out if you are selected. SW [3: 0] is initially a fixed value. Thus, the selection bus master (MST) receives the source memory addressing signal SMA (where / STA [2: 0] = 10) from the bus arbiter 202 and the transmission start signal SRT (where / STA [2: 0] = 101). ) And send the lead signal / RD. At this time, the bus master (MST) issues a bus use status signal / IN_USE to inform the bus arbiter 202 that it is using the bus. In addition, the bus arbiter 202 counts the number of bytes of data to be transmitted through the data transmission counting circuit 214, and sends a counter reset signal / CT_RS to the bus master (MST) to complete transmission.

The transmission request and source confirmation signal generation circuit 226 is a transmission ready signal generation circuit 232, a transmission reserve processing circuit 234, a control state decoding circuit 236, inverters IN6 to IN8 and flip as shown in FIG. It consists of flops (FF4 to FF8) and NAND gates (NAND3 to NAND5). Referring to FIG. 12 showing the operation timing of the transmission request and the source confirmation signal generation circuit 226, when the bus master MST receives the transmission start signal / XFR_SRT signal from the corresponding module, the transmission request signal as shown in FIG. It generates / XFR_REQ and receives the source memory address designation signal SMA, the transmission amount notification signal XFC, the transmission start signal SRT, and the source inquiry signal / S_ASK from the bus arbiter 202 via the control status signal / STA [2: 0]. If the source inquiry signal / S_ASK is received, the source confirmation signal SID is sent out. / SAD_SET and / AS_SAD are to operate only when the source address SAD [3: 0] determined by the bus arbiter 202 and its SW [3: 0] coincide. The transmission ready signal generation circuit 232 is composed of flip-flops FF9 and FF10, inverters IN9 and IN10, and NAND gate NAND6 as shown in FIG. When the bus master (MST) receives the transmission start signal / XFR_SRT from the module, it generates one clock cycle of / XFR_RDY. This is later used to generate the transmit request signal / XFR_REQ. As shown in FIG. 15, the transfer reserve processing circuit 234 includes a latch circuit LAT1, a comparison circuit COMP1, an inverter IN11, an OR gate OR4, OR5, an AND gate AND1, and a flip-flop FF11. Configure. If the source address SAD [3: 0] and SW [3: 0] determined by the bus arbiter 202 coincide with each other, / SAD_SET is outputted, and / AS_SAD is outputted when the address strobe signal / AS is received. The transmission request signal / XFR_REQ goes low when / XFR_RDY is low, and goes high when / AS_SAD is low. The source acknowledge signal SID only occurs while / SASK_S is low. The control state decoding circuit 236 comprises inverters IN12 to IN14 and NAND gates NAND7 to NAND10 as shown in FIG. 16, and decodes the control state signal / STA [2: 0]. 2: 0] In case of 1, source inquiry signal / S_ASK is generated. In case of 10, source memory addressing signal SMA is generated. In case of 100, transmission amount notification signal XFC is generated. In case of 101, transmission start signal SRT is generated. do.

As shown in FIG. 17, the read signal generating circuit 228 includes the OR gates OR6 and OR7, the inverters IN15 to IN18, the AND gates AND2 to AND5, the flip-flops FF13 to FF16, and the source address control circuit 238. ). Referring to FIG. 18 showing the operation timing of each part of the read signal generation circuit 228, if the source address SAD [3: 0] and SW [3: 0] determined by the bus arbiter 202 coincide with / SAD_SET is sent low. In this case, the read signal / RD and the write signal / WR become effective. The read signal / RD is generated first after the transmission start signal SRT (SAD [3: 0] = 101) occurs. When the read signal / RD goes high, the write signal / WR goes low and the write signal / WR As the read signal / RD goes low again when the signal goes low, reads and writes are performed between the bus master MST and the bus slave SLV. When the number of data to be transmitted in the logger bus arbiter 202 is transmitted, a transmission completion signal / UNDER_F is generated to terminate transmission and reception. The source address control circuit 238 is composed of the AND gate AND6, the flip-flops FF17 to FF23, and the inverter IN19 as shown in FIG. 19 to delay the input pulse by 7 clocks.

The bus use detection circuit 230 includes inverters IN20 to IN22, flip-flops FF24 to FF27, an oragate OR8, and a NAND gate NAND11 as shown in FIG. Referring to FIG. 21 showing the operation timing of each part of the bus usage detection circuit 230, the bus usage status signal / IN_USE is a pair of bus master (MST) and bus slave (SLV) is the image data bus 200 It is a signal to indicate that it is in use, it goes low when / AS_SAD is low and goes high when the last slave data is written by bus slave (SLV).

The above-described bus slave SLV will now be described in more detail. First, as shown in FIG. 22, the bus slave SLV includes an ID generation circuit 24, an oragate OR9, a write signal generation circuit 242, and an address counter CNT3. Referring to FIG. 23 showing the operation timing of each part of the bus slave SLV, each slave receives a high active transmission control signal XFR_CONT from the module when its buffer is used by its module. Receiving the transmission control signal XFR_CONT indicates that the corresponding module can receive data. Therefore, upon receiving the destination inquiry signal / D_ASK (where / STA [2: 0] = 11) from the bus arbiter 202, it sends a destination acknowledgment DID to the bus arbiter 202 indicating that it can receive data. Then, the bus arbiter 202 determines the bus slave to use the image data bus 200 and gives the destination address DAD [3: 0] to each bus slave, and each bus slave compares with its SW [3: 0]. You will know whether you are chosen. The selected bus slave SLV receives the destination memory addressing signal DMA (where / STA [2: 0 '= 110) from the bus arbiter 202 and receives the read signal / RD from the bus master MST. When you send WR, it starts to receive video data. This is valid only when the source transfer end signal / SXFR_END is low. If the source transfer end signal / SXFR_END rises high, the reception is completed by not generating the write signal / WR from that point on.

The destination confirmation signal generation circuit 24 includes the inverters IN23 to IN27, the latch circuit LAT2, the comparison circuit COMPP2, the control state decoding circuit 244, the oragate OR10 to OR15, and flip as shown in FIG. The flop FF28 to FF34 is composed of a wand gate AND7 and a NAND gate NAND12 to NAND14. Referring to FIG. 25 showing the operation timing of each part of the destination confirmation signal generation circuit 240, the destination inquiry signal / D_ASK from the bus arbiter 202 through the control status signal / STA [2: 0] (where / STA [2: 0] = 11), the destination memory address designation signal DMA (at this time / STA [2: 0] = 110) and the transmission start signal SRT (at this time / STA [2: 0] = 101) When the destination inquiry signal / D_ASK (/ STA [2: 0] = 11) is received, the destination confirmation signal DID is sent out. When the source transfer termination signal / SXFR_END is received from the bus master (MST), if its SW [3: 0] and the destination address DAD [3: 0] determined by the bus arbiter 202 are correct, the signal is converted to / DXFR_END and exported. To be used at. The / DAD-SET, / DEST_RD, / DEST_RS, etc. are the gates of the signal made valid only when their SW [3: 0] and the destination address DAD [3: 0] determined from the bus arbiter 202 match. ~ NAND17) and decode the control status signal / STA [2: 0]. Accordingly, if the control status signal / STA [2: 0] is 11, the destination inquiry signal / D_ASK is generated. If the control status signal / STA [2: 0] is 11, the destination memory address designation signal DMA is generated, and if it is 101, the transmission start signal SRT is generated. do.

The write signal generation circuit 242 is composed of inverters IN31 and IN32, AND gates AND8 and AND9, flip-flops FF35 to FF37, and a light control circuit 246 as shown in FIG. Referring to FIG. 28 showing the operation timing of each part of the write signal generation circuit 242, when the / DEST_RD goes high, the write signal / WR goes low and the read signal / RD goes high. Is supposed to come down. The destination address control circuit 246 is composed of an AND gate AND9, flip-flops FF38 to FF46, and an inverter IN33 as shown in FIG. 29 to delay the input pulse by 9 clocks.

As described above, the image data bus 200 is separated from the general system bus used by the CPU of the image processing system and the image data bus 200 for the processing of the image data to secure real-time control of the system and to program the system control. At the same time, it can reduce the overhead and process high-capacity / high-speed image data.

FIG. 30 shows an example in which the image data bus of the present invention as described above is applied to the spirituality processing system as shown in FIG. When the color image input from the color scanner 25 is transmitted to the other side through proper color correction and encoding process suitable for the user's network, the transmission of all image data between each module is performed through the image data bus 200 to control this. The real-time performance can be easily secured by not interrupting the program execution of the CPU 248. At this time, the image data is transmitted to the network via the color scanner 250 → color compensator 252 → page memory 254 → encoder 256 → network interface 258.

In addition, the characteristics of image data are easy to block, and in fact, image processing systems require data transmission in units of blocks. In this case, in the present invention, the overhead of the bus arbitration cycle surrounding the video data bus usage rights is relatively reduced when processing data in units of blocks, thereby greatly improving the transmission efficiency.

As described above, the present invention has an advantage of improving data transmission speed by transmitting image data between separate modules of the image processing system through a separate dedicated passage.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalents of the claims and the claims.

Claims (8)

An image processing system having at least two modules each transmitting image data to each other for unique image data processing, wherein the modules exclusively transmit the image data separately from the system bus of the image processing system. A source data source having a video data bus providing a passage, a bus mediation means for mediating the use of the video data bus for transmission and reception of the video data between the modules, and a video data to be transmitted to another module of the modules. Bus master means for transmitting the image data of the source module to the destination module through the image data bus under the arbitration of the bus arbitration means, and provided to the destination module through the image data bus under the arbitration of the bus arbitration means. The video data from the bus master means Received by an image processing system having a data bus of the image only, it characterized in that it comprises a means for providing the bus slave to the destination module. The image processing system according to claim 1, wherein the transmission of the image data through the image data bus is performed in units of blocks. The image processing system according to claim 2, wherein the image data bus performs address control through data lines. An image processing system having at least two modules for transmitting image data to each other for processing unique image data, wherein the image provides a path for exclusively transmitting image data separately from the system bus of the image processing system. A bus master means for transmitting the video data of the own module to the corresponding destination module through the video data bus in response to a data start bus and a transmission start signal applied from the own module; The bus slave which is provided in each module and receives the video data through the video data bus from the bus master means of the source module requesting the transmission start when its own module is selected as the destination module and applies it to its own module. Means and a bus master number of the source module And a bus arbitration means for selecting the destination module in response to a request of the controller and for arbitrating transmission of the video data through the video data bus between the bus master means of the source module and the bus slave means of the destination module. An image processing system having a data bus dedicated to video. The image processing system according to claim 4, wherein the transmission of the image data through the image data bus is performed in units of blocks. 6. The image processing system according to claim 5, wherein the image data bus performs address control through a data line. Image data buses which transmit image data to each other for processing unique image data, each of which provides at least two or more modules each having a bus master and a bus slave, and a passage for exclusively transmitting image data between the modules. And a bus arbitration means for arbitrating data transmission through the video data bus, the control method comprising the steps of: identifying a bus master of a corresponding module in response to a request for video data transmission from the modules; Checking a bus slave of a module capable of receiving the image data, comparing a priority of the identified bus master and slaves to determine a source and a destination module, and a memory start address of the determined source and destination modules; And specify the number of bytes to send And a process of starting data transmission through a data bus and checking a use state of the image data bus and ending the data transfer cycle when the use ends. Control method. 8. The control method according to claim 7, wherein the transfer of the image data through the image data bus is performed in units of blocks.