KR0137716B1 - Contact etching method of semiconductor device - Google Patents
Contact etching method of semiconductor deviceInfo
- Publication number
- KR0137716B1 KR0137716B1 KR1019940014575A KR19940014575A KR0137716B1 KR 0137716 B1 KR0137716 B1 KR 0137716B1 KR 1019940014575 A KR1019940014575 A KR 1019940014575A KR 19940014575 A KR19940014575 A KR 19940014575A KR 0137716 B1 KR0137716 B1 KR 0137716B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact
- gas
- semiconductor device
- etching
- fluorine
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 반도체 소자의 콘택 식각방법에 관한 것으로 식각하는 가스를 탄소에 대한 불소(Fluorine) 의 구성비가 1인 가스를 사용하여 콘택식각을 하거나 또는 종래의 사용되고 있는 탄소에 대한 탄소에 대한 불소의 구성비가 1 이상인 가스에 수소를 첨가한 가스를 사용하여 건식식각하여 기판에 대한 선택도(Selectivity)를 증가시키며 콘택홀의 프로파일 기울기(Tapering)를 억제하며 마이크로 로우딩(Micro Loading)영향도 감소시키는 반도체 소자의 콘택 식각 방법에 관한 것이다.The present invention relates to a contact etching method of a semiconductor device, wherein the etching of the gas to be etched using a gas having a composition ratio of fluorine to carbon is 1 or a composition ratio of fluorine to carbon to carbon conventionally used A semiconductor device that increases the selectivity of a substrate by dry etching using a gas containing hydrogen to gas of 1 or more, suppresses the profile taping of the contact hole, and also reduces the effect of micro loading. The contact etching method of the present invention.
Description
제 1도 및 제 2도는 본 발명의 반도체 소자 콘택 식각방법에 따라 산화막을 식각한 상태의 단면도.1 and 2 are cross-sectional views of the oxide film etched in accordance with the semiconductor device contact etching method of the present invention.
제 3도는 본 발명의 반도체 소자 콘택 식각방법에 따라 서로 다른 크기의 콘택을 형성한 상태의 단면도.3 is a cross-sectional view of forming a contact of different sizes according to the semiconductor device contact etching method of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 기판(기저부), 2 : 산화막(Oxide),1: substrate (base), 2: oxide,
3 : 감광막, 4,5,6,7 : 콘택,3: photosensitive film, 4,5,6,7: contact,
8 : 폴리머8: polymer
본 발명은 반도체 소자의 콘택 식각방법에 관한 것으로, 식각에 사용하는 가스를 탄소(C:Carbon)에 대한 불소(F:Fluorine)의 구성비가 1인 가스를 사용하여 콘택식각을 하거나 또는 종래의 사용되고 있는 CHF3가스등과 같이 탄소에 대한 불소의 구성비가 1 이상인 가스에 수소와 같은 첨가물을 넣은 가스를 사용하여 식각함으로써 기판에 대한 선택도(Selectivity)를 증가시키며 콘택의 프로파일 기울기(Tapering)를 억제하며 콘택의 크기에 따라 식각깊이가 달라지는 마이크로 로우딩(Micro Loading) 영향도 감소시키는 반도체 소자의 콘택 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a contact of a semiconductor device, wherein the gas used for etching is used for etching the contact using a gas having a composition ratio of fluorine (F: fluorine) to carbon (C) of 1 By using a gas containing an additive such as hydrogen in a gas having a fluorine to carbon composition ratio of 1 or more, such as a CHF 3 gas, the selectivity to the substrate is increased, and the profile profile of the contact is suppressed. The present invention relates to a contact etching method of a semiconductor device which also reduces the effect of micro loading, in which the etching depth varies depending on the size of the contact.
종래의 콘택식각 공정시에는 대개 CHF3나 CF4가스를 사용하는데, 선택도를 향상시키기 위해서 CFx 폴리머를 형성하게 되는 경우, 폴리머가 콘택의 바닥뿐만 아니라 측벽에도 형성되기 때문에 프로파일이 테이프링(Tapering) 되고 따라서 식각비율도 떨어져서 결국, 심한 마이크로 로우딩(Micro loading)영향을 보이는 문제점이 있다.Conventional contact etching processes typically use CHF 3 or CF 4 gas, but when CFx polymers are formed to improve selectivity, the profile is taped because the polymers are formed on the sidewalls as well as the bottom of the contact. Therefore, the etching rate is also lowered, which results in a severe micro loading effect.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 C2H2F2나 CH3F 가스와 같이 탄소(C)에 대한 불소(F)의 구성비(즉, F/C)가 1인 가스를 사용하여 콘택 식각을 하거나 수소와 같은 첨가물을 넣은 가스를 사용하여 식각을 하여 산화막이 아닌 기판에는 폴리머 형성을 증가시키고 콘택 측벽의 산화막에서는 폴리머 형성을 감소시키켜 기판에 대한 선택도를 증가시키고 프로파일이 테이퍼링 되는 것을 억제시키면서 마이크로 로우딩 영향을 방지하는 반도체 소자의 콘택 식각방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problem, the present invention uses a gas having a composition ratio of fluorine (F) to carbon (C), such as C 2 H 2 F 2 or CH 3 F gas, that is, F / C. Either by contact etching or by etching with an additive gas such as hydrogen to increase polymer formation on substrates other than oxides, and polymer formation on oxide sidewalls on contact sidewalls to increase selectivity to substrates and to taper profiles. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for etching contacts of a semiconductor device which prevents the micro-loading effect from being suppressed.
이하, 첨부된 도면을 참조하여 본 발명의 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 1도와 제 2도는 본 발명의 반도체 소자 콘택 식각방법에 따라 식각한 상태의 단면도이다.1 and 2 are cross-sectional views of etching states according to the semiconductor device contact etching method of the present invention.
제 1도는 콘택(4)을 형성하기 위해 산화막(2)을 식각하되, 탄소(C)에 대한 불소(F)의 비가 1인 C2H2F2나 CH3F와 같은 가스를 사용하거나, 탄소(C)에 대한 불소(F)의 구성비가 1 이상인 종래의 CHF3와 같은 가스에 대한 수소와 같은 첨가물을 넣은 가스를 사용하여 산화막(2)을 식각한 상태를 도시하고 있다.1 is used to etch the oxide film 2 to form a contact 4, using a gas such as C 2 H 2 F 2 or CH 3 F having a ratio of fluorine (F) to carbon (C) 1, or The oxide film 2 is etched using a gas containing an additive such as hydrogen to a gas such as CHF 3 having a composition ratio of fluorine (F) to carbon (C) of 1 or more.
이때, 생성되는 폴리머(8)는 불소기가 적은 로우 불소 폴리머(Low Fluorine Polymer)로서 산소와 반응하게 되면 쉽게 감소되는 특성을 가지며, 측벽의 산화막(2)에 포함된 산소와 결합함으로써 폴리머가 쉽게 제거된다.At this time, the produced polymer (8) is a low fluorine polymer (Low Fluorine Polymer) having a small amount of fluorine group is easily reduced when reacting with oxygen, the polymer is easily removed by combining with oxygen contained in the oxide film 2 of the side wall do.
제 2도는 산화막(2)이 아닌 다른 성분으로 된 기저부(1)가 노출되고, 노출된 기저부(1)에 폴리머(8)가 형성된 상태를 도시하고 있다.2 shows a state in which the base 1 made of a component other than the oxide film 2 is exposed and the polymer 8 is formed in the exposed base 1.
산화막이 아닌 기저부가 노출되었을 때 오버 식각을 행한 경우에도 콘택 측벽의 산화막(2)에서는 산소가 발생하기 때문에 CxF계 폴리머를 쉽게 제거시켜 콘택 프로파일이 기울어 지면서 테이퍼링 되는 것을 막을 수 있다.Even when over-etching is performed when the base, not the oxide film, is exposed, oxygen is generated in the oxide film 2 on the sidewall of the contact, so that the CxF-based polymer can be easily removed to prevent the contact profile from tapering while tilting.
한편, 산화막이 아닌 기저부(1)에서는 불소 함량이 작은 폴리머〔-CxF-〕가 기저부(1)위에 분해되지 않고 퇴적되기 때문에 높은 선택도를 얻을 수 있다.On the other hand, since the polymer [-CxF-] having a small fluorine content is deposited on the base 1 without being decomposed on the base 1 rather than the oxide film, high selectivity can be obtained.
따라서, 제 3도에 도시한 바와같이, 콘택(5,6,7)의 크기가 서로 다른 경우에도 기저부(1)에 대한 높은 선택도를 얻을 수 있고 동시에 콘택의 프로파일이 수직으로 형성되고 식각비율이 차이가 나지 않으므로 마이크로 로우딩 영향을 효과적으로 감소시킬 수 있다.Thus, as shown in FIG. 3, even when the sizes of the contacts 5, 6 and 7 are different, high selectivity with respect to the base 1 can be obtained, and at the same time the profile of the contact is formed vertically and the etching rate Since there is no difference, the micro-loading effect can be effectively reduced.
아울러, 본 발명에서는 탄소(C)에 대한 불소(F) 비가 1 이하인 C2H2F2나 CH3F를 사용하고 불소(F)원소와 결합 중화시키는 수소 첨가물을 넣은 가스를 사용하기 때문에 종래의 기술과 달리 불소 함량이 적은 폴리머(8)를 형성시킬 수 있고 이 폴리머(8)는 콘택 식각시 콘택 측벽의 산화막(2)에서는 분해가 잘 되고 산화막이 아닌 기저부(1)에서는 퇴적이 잘되어 콘택 프로파일이 수직적으로 형성되도록 하고 기저부(1)에 대한 선택도도 증가시키고 마이크로 로우딩 영향도 감소시킬 수 있는 효과를 가진다.In addition, since the present invention uses a gas containing C 2 H 2 F 2 or CH 3 F having a fluorine (F) ratio to carbon (C) of 1 or less and containing a hydrogenated substance that neutralizes the bond with the fluorine (F) element. Unlike the technique described above, a polymer (8) having a low fluorine content can be formed, and the polymer (8) is well decomposed in the oxide film (2) on the sidewall of the contact during etching, and deposited in the base (1) rather than the oxide film. The contact profile can be formed vertically, and the selectivity to the base 1 can be increased and the micro-loading influence can be reduced.
이상에서 설명한 바와 같이 C2H2F2나 CH3F와 같이 탄소(C)에 대한 불소(F)의 비가 1인 가스를 사용하여 콘택식각을 하거나 또는 수소와 같은 첨가물을 넣은 가스를 사용하여 식각을 하는 본 발명의 반도체 소자 콘택 식각방법은 산화막이 아닌 기저부에는 폴리머형성을 증가시키고 콘택 측벽의 산화막에서는 폴리머 형성을 감소시켜 기저부에 대한 선택성도를 증가시키고 콘택의 크기가 서로 다른 경우에도 기저부에 대한 높은 선택도를 얻을 수 있으면서도 콘택의 프로파일이 수직으로 형성되고 식각비율이 차이가 나지 않으므로 마이크로 로우딩 영향을 효과적으로 감소시킬 수 있다.As described above, contact etching may be performed using a gas having a ratio of fluorine (F) to carbon (C) of 1, such as C 2 H 2 F 2 or CH 3 F, or a gas containing an additive such as hydrogen may be used. The semiconductor device contact etching method of etching according to the present invention increases the polymer formation at the base of the non-oxide film and decreases the polymer formation at the oxide film of the contact sidewall, thereby increasing selectivity to the base and increasing the selectivity to the base even when the contact sizes are different. While the high selectivity can be obtained, the contact profile is formed vertically and the etching rate is not different, which effectively reduces the micro-loading effect.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940014575A KR0137716B1 (en) | 1994-06-24 | 1994-06-24 | Contact etching method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940014575A KR0137716B1 (en) | 1994-06-24 | 1994-06-24 | Contact etching method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960001885A KR960001885A (en) | 1996-01-26 |
| KR0137716B1 true KR0137716B1 (en) | 1998-04-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940014575A KR0137716B1 (en) | 1994-06-24 | 1994-06-24 | Contact etching method of semiconductor device |
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| Country | Link |
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| KR (1) | KR0137716B1 (en) |
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1994
- 1994-06-24 KR KR1019940014575A patent/KR0137716B1/en not_active IP Right Cessation
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| KR960001885A (en) | 1996-01-26 |
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