KR0137548B1 - Getting method of semiconductor device - Google Patents
Getting method of semiconductor deviceInfo
- Publication number
- KR0137548B1 KR0137548B1 KR1019940035736A KR19940035736A KR0137548B1 KR 0137548 B1 KR0137548 B1 KR 0137548B1 KR 1019940035736 A KR1019940035736 A KR 1019940035736A KR 19940035736 A KR19940035736 A KR 19940035736A KR 0137548 B1 KR0137548 B1 KR 0137548B1
- Authority
- KR
- South Korea
- Prior art keywords
- buried layer
- layer
- semiconductor substrate
- gettering
- investment
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000007547 defect Effects 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 239000007769 metal material Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005247 gettering Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- ATVLVRVBCRICNU-UHFFFAOYSA-N trifluorosilicon Chemical compound F[Si](F)F ATVLVRVBCRICNU-UHFFFAOYSA-N 0.000 abstract description 3
- 229910004014 SiF4 Inorganic materials 0.000 abstract description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Physical Vapour Deposition (AREA)
Abstract
본 발명은 반도체 기판상에 이온주입되어 도핑된 영역이 매몰층 내부의 미세결함이나 금속성 물질을 매몰층 밖으로 게터링하는 방법에 있어서, 상기 메몰층 하부의 반도체 기판에 격자 손상된 결함을 형성하기 위하여 SiF3 이온을 상기 매몰층 하부로 이온주입시키는 단계, 상기 매몰층 하부의 반도체 기판 결합으로 상기 매몰층 내부의 미세결함이나 금속성 물질이 게터링되도록 열공정을 실시하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 매몰층의 게터링 방법에 관한 것으로, 상기 설명과 같은 본 발명은 종래 Si, C, O 등과 같은 원소와 달리 SiF3는 SiF4 가스 소오스로 부터 쉽게 다량의 빔커런트를 확보할 수 있고, 한개의 이온 분자가 Si, C, O 등의 원소에 비하여 3배 이상의 게더링 효과를 나타내므로 짧은 시간의 이온주입으로도 동일한 게더링 효과를 볼 수 있으며, F를 이용한 게더링 방법은 F가 실리콘과 결합시 짧은 결합거리로(Si와 Si의 결합거리에 비하여 약 80% 짧음) 스트레스를 유발하여 자체 스트레스의 완화를 위하여 미세결함이나 금속성 물질을 강하게 게더링 하는 효과가 있다.The present invention relates to a method for gettering a fine defect or a metallic material inside an investment layer out of an investment layer by ion implanted and doped regions on a semiconductor substrate, in order to form lattice damaged defects in the semiconductor substrate under the investment layer. Implanting ions into the lower portion of the buried layer, and performing a thermal process so that fine defects or metallic materials inside the buried layer are gettered by bonding the semiconductor substrate under the buried layer. The present invention relates to a gettering method of the buried layer, and the present invention as described above, unlike conventional elements such as Si, C, O, SiF3 can easily secure a large amount of beam current from the SiF4 gas source, one ion molecule Has more than three times the gathering effect compared to elements such as Si, C, O, etc. Gathering method using F has a short bonding distance when F is bonded with silicon (about 80% shorter than Si and Si bonding distance), causing stress, so that microdefects or metallics can be used to alleviate self stress. It has a strong gathering effect.
Description
제1a도 내지 제1e도는 본 발명에 따른 게터링 방법을 나타내는 개념도.1a to 1e is a conceptual diagram showing a gettering method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11:실리콘 기판12:필드산화막11: silicon substrate 12: field oxide film
13, 17:결함14:매몰층13, 17: Defect 14: buried layer
15:미세 결함16:금속성 물질15: micro defect 16: metallic material
본 발명은 반도체 소자 제조 공정중 반도체 기판상에 이온주입되어 도핑된 영역인 매몰층(Well) 내부의 미세결함이나 금속성 물질을 매몰층 밖으로 게터링(Gettering)하는 방법에 관한 것이다.The present invention relates to a method of gettering a microdefect or a metallic material in a buried layer, which is a region doped with ions implanted onto a semiconductor substrate during a semiconductor device manufacturing process, out of the buried layer.
반도체 소자의 동작시 매몰층 내부에 존재하는 미세 결함이나 Au, Cu, Ni, Fe 등의 금속성 물질은 매몰층으로 부터 기판 하부로의 누설 전류를 유도하여 소자의 오동작 및 저장된 정보의 손실을 가져와 소프트 에러를 유발함으로, 소자 제조시 매몰층 하부에 미세결합이나, 금속성 물질을 게터링하는 기술이 계속 연구되고 있다.During the operation of the semiconductor device, minute defects inside the buried layer or metallic materials such as Au, Cu, Ni, and Fe induce leakage current from the buried layer to the lower part of the substrate, leading to malfunction of the device and loss of stored information. By causing an error, techniques for gettering fine bonds or metallic materials under the buried layer during device fabrication have been continuously studied.
종래에는 200KeV 이내의 중 에너지 이온주입에 의한 매몰층 형성시에 메몰층의 깊이를 깊게하기 위하여 1100℃ 이상의 온도로 약 15 시간 정도의 열공정을 실시하여 실리콘 박막에 존재하는 O2원소를 매몰층 하부에 집중시켜 결함을 형성하고 매몰층에 존재하는 미세결함이나 금속성 물질을 이 결함으로 게터링하였으나, 500keV 이상의 고에너지 이온주입에 의한 1000℃ 이하의 온도로 3시간 이내의 열공정을 실시하는 매몰층 형성기술이 차세대 소자제조 기술로 사용되면서 O2에 의한 결합층을 형성시킬 수 없어, 3MeV 이상의 고에너지로 Si, O2, C 등의 이온을 매몰층 하부의 실리콘 기판에 깊숙히 주입시켜 결함을 형성한 후 이후에 열공정을 실시하여 이 결함으로 매몰층내부의 미세결함이나 금소겅 불순물을 게터링 하였다.Conventionally, in order to deepen the depth of the buried layer when forming the buried layer by the implantation of heavy energy ions within 200 KeV, the thermal process is performed at about 1100 ° C. for about 15 hours to bury the O 2 elements present in the silicon thin film. The defect was formed by concentrating on the lower part, and the micro defect or metallic material present in the buried layer was gettered with this defect, but the investment was performed within 3 hours at a temperature of 1000 ° C. or lower by high energy ion implantation of 500 keV or more. the layer forming technique can not be formed in the bonded layer by the O 2 as used in manufacturing technology next-generation devices, by deeply implanted into the silicon substrate by ions of the buried layer below, such as Si, O 2, C with high-energy than 3MeV defects After the formation, a thermal process was performed to getter the microdefects and the metal impurities in the buried layer.
그러나, 상기와 같이 게터링을 위한 결함층을 형성하기 위해서는 3.0E14 ions/㎤ 이상의 이온을 주입하여야 하는데 현재 사용되고 있는 고에너지 이온주입기로는 장시간 이온을 주입하여야 하는 문제점을 가지고 있다.However, in order to form a defect layer for gettering as described above, ions of 3.0E14 ions / cm 3 or more must be implanted, but the high energy ion implanter currently used has a problem of implanting ions for a long time.
따라서, 본 발명은 적은 양의 이온을 주입하여 게터링 효과를 극대화 시키는 반도체 소자 메몰층(WELL)의 게터링 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a gettering method of a semiconductor device buried layer (WELL) that maximizes the gettering effect by implanting a small amount of ions.
상기 목적을 달성하기 위하여 본 발명은 반도체 기판상에 이온주입되어 도핑된 영역인 매몰층 내부의 미세결합이나 금속성 물질을 매몰층 밖으로 게터링하는 방법에 있어서, 상기 메몰층 하부의 반도체 기판에 격자 손상된 결함을 형성하기 위하여 SiF3 이온을 상기 매몰층 하부로 이온주입시키는 단계, 상기 매몰층 하부의 반도체 기판 결함으로 상기 매몰층 내부의 미세결함이나 금속성 물질이 게터링되도록 열공정을 실시하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of gettering microbonding or a metallic material inside an investment layer, which is an ion doped region on a semiconductor substrate, out of the investment layer, wherein the lattice damage is caused to the semiconductor substrate under the investment layer. Implanting SiF 3 ions into the bottom of the buried layer to form a defect, and performing a thermal process to getter the micro defects or metallic material inside the buried layer with a semiconductor substrate defect under the buried layer; It is characterized by.
종래기술에서는 Si, C, O 등의 단일원소를 이온주입하여 게더링층인 결함층을 형성하였기 때문에 적정량 이상의 이온주입을 위하여 오랜 시간 동안 이온주입 공정을 실시하여야 하나, SiF3는 하나의 Si원소와 세개의 F원소로 구성되어 약 1/3의 양만을 이온주입하여도 동일한 효과를 얻을 수 있으며, 또한 이온주입 시간을 결정하는 가장 큰 요소인 이온 빔 커런트의 확보에 있어서도 Si, C, O 보다도 수월하게 많은 양을 얻을 수있다.In the prior art, since a defect layer, which is a gathering layer, was formed by ion implantation of a single element such as Si, C, O, etc., the ion implantation process should be performed for a long time to inject an appropriate amount or more, but SiF3 has one Si element and three The same effect can be obtained even by ion implantation of about 1/3 of F element, and it is easier than Si, C, and O to secure ion beam current, which is the biggest factor that determines ion implantation time. You can get a large amount.
이하, 첨부된 도면을 참조하여 본 발명에 따른 게더링 방법을 상세히 설펴본다.Hereinafter, a gathering method according to the present invention will be described in detail with reference to the accompanying drawings.
먼저, 제1a도는 실리콘 기판(11)상에 필드산화막(12)을 형성한 상태의 단면도이고, 제1b도는 매몰층의 형성을 위하여 약 1MeV의 고에너지로 이온을 주입한 단면도로서, 매몰층이 형성된 지역에 고에너지의 이온주입시 발생한 격자의 손상된 결합(13)이 발생함을 보여준다.First, FIG. 1A is a cross-sectional view of the field oxide film 12 formed on the silicon substrate 11, and FIG. 1B is a cross-sectional view of implanting ions at a high energy of about 1 MeV to form a buried layer. It shows that a damaged bond 13 of the lattice generated during high energy ion implantation occurs in the formed area.
이어서, 제1c도는 900℃ 정도의 온도에서 3시간 정도 열공정을 실시하여 이온주입된 원소와 실리콘과의 격자 재배열을 이루어 전기적 특성이 주어진 매몰층(14)이 형성된 상태의 단면도이다.Subsequently, FIG. 1C is a cross-sectional view of a buried layer 14 in which electrical properties are given by performing a lattice rearrangement between ion-implanted elements and silicon by performing a thermal process at a temperature of about 900 ° C. for about 3 hours.
이때, 결함(13)은 열공정 동안 대부분은 소멸이 되나, 미처 치유되지 않은 손상은 실리콘의 격자구조를 변형시키는 미세 결함(15)으로 남아, 소자의 동작시 누설전류를 유도하게 된다. 또한 여러 경로로 침투한 Au, Cu, Ni, Fe 등의 금속성 물질(16)은 뛰어난 유동성 때문에 극소량 만으로도 소자의 수명을 단축시키는 치명적인 불순물로 작용한다.At this time, the defect 13 is mostly eliminated during the thermal process, but the undamaged damage remains as a micro defect 15 that deforms the lattice structure of silicon, leading to leakage current during operation of the device. In addition, the metallic material 16 such as Au, Cu, Ni, and Fe penetrated through various paths acts as a fatal impurity that shortens the life of the device even with a very small amount due to its excellent fluidity.
계속해서, 제1d도는 상기 매몰층 내의 미세결함(15)과 금속성 물질(16)을 게터링하기 위하여 3MeV 이상의 에너지로 SiF3이온을 약 1.0E14 ion/㎤ 의 량으로 이온주입하여 매몰층 하부에 SiF3의 이온주입으로 심하게 손상된 결합(17)을 형성한다.Subsequently, FIG. 1D illustrates ion implantation of SiF 3 ions in an amount of about 1.0E14 ions / cm 3 with an energy of 3 MeV or more to getter the microdefects 15 and the metallic material 16 in the buried layer, and the SiF 3 under the buried layer. Ion implantation of to form a severely damaged bond (17).
제1e도는 900~1000℃에서 1~2시간 동안 열공정을 실시하여 상기 결함(17)으로 매몰층 내의 미세결합(15)과 금속성 물질(16)을 매몰층 밖으로 게더링 한다.FIG. 1E illustrates a thermal process performed at 900 to 1000 ° C. for 1 to 2 hours to gather the fine bond 15 and the metallic material 16 in the buried layer out of the buried layer with the defect 17.
이상, 상기 설명과 같은 본 발명은 종래의 Si, C, O 등과 같은 원소와 달리 SiF3는 SiF4 가스 소오스로 부터 쉽게 다량의 빔커런트를 확보할 수 있고, 한개의 이온 분자가 Si, C, O 등의 원소에 비하여 3개 이상의 게더링 효과를 나타내므로 짧은 시간의 이온주입으로도 동일한 게더링 효과를 볼 수 있으며, F를 이용한 게더링 방법은 F가 실리콘과 결합시 짧은 결합거리로(Si와 Si의 결합거리에 비하여 약 80% 짧음) 스트레스를 유발하여 자체 스트레스의 완화를 위하여 미세결함이나 금속성 물질을 강하게 게더링 하는 효과가 있다.As described above, the present invention as described above, unlike conventional elements such as Si, C, O, SiF3 can easily secure a large amount of beam current from the SiF4 gas source, one ion molecule is Si, C, O, etc. Compared to the element of, it shows three or more gathering effects, so the same gathering effect can be obtained even with short time ion implantation.The gathering method using F has a short bonding distance when F is combined with silicon (bonding distance between Si and Si). It is about 80% shorter than that). It causes stress and strongly gathers fine defects or metallic materials to alleviate its own stress.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940035736A KR0137548B1 (en) | 1994-12-21 | 1994-12-21 | Getting method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940035736A KR0137548B1 (en) | 1994-12-21 | 1994-12-21 | Getting method of semiconductor device |
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| KR960026412A KR960026412A (en) | 1996-07-22 |
| KR0137548B1 true KR0137548B1 (en) | 1998-06-01 |
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| KR1019940035736A KR0137548B1 (en) | 1994-12-21 | 1994-12-21 | Getting method of semiconductor device |
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