KR100328708B1 - A method of isolating semiconductor layer - Google Patents
A method of isolating semiconductor layer Download PDFInfo
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- KR100328708B1 KR100328708B1 KR1019990025124A KR19990025124A KR100328708B1 KR 100328708 B1 KR100328708 B1 KR 100328708B1 KR 1019990025124 A KR1019990025124 A KR 1019990025124A KR 19990025124 A KR19990025124 A KR 19990025124A KR 100328708 B1 KR100328708 B1 KR 100328708B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 56
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims description 13
- -1 nitrogen ions Chemical class 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 26
- 238000002955 isolation Methods 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 7
- 238000002513 implantation Methods 0.000 abstract description 3
- 238000000926 separation method Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- 239000010408 film Substances 0.000 description 10
- 239000013078 crystal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체층 격리방법에 관한 것으로서, 특히, 반도체기판을 SIMNI(separation by implantation of nitrogen) 구조로 형성할 때 이온주입 및 어닐링 공정을 개선하여 반도체층인 실리콘층과 절연층의 계면에 결함을 개선하여 기판의 특성을 향상시키고 형성되는 질화막의 보이드 형성을 방지하여 필링(peeling)현상을 방지하도록한 질화막을 이용한 반도체기판 절연층 형성방법에 관한 것이다. 본 발명에 따른 반도체기판 격리방법은 반도체 기판의 소정 깊이에 질소 이온주입으로 이온매몰층을 형성하는 단계와, 소정 온도 조건 및 질소 및 저압 산소 분위기에서 이온배몰층이 형성된 반도체 기판에 어닐링을 실시하여 이온매몰층으로부터 질화막을 형성하고 질화막의 상부에 산화막을 형성하여 반도체 기판의 상층부와 하층부를 절연시키는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor layer isolation method. In particular, when the semiconductor substrate is formed in a separation by implantation of nitrogen (SIMNI) structure, ion implantation and annealing processes are improved to prevent defects at the interface between the silicon layer and the insulating layer. The present invention relates to a method for forming a semiconductor substrate insulating layer using a nitride film to improve the characteristics of the substrate and to prevent voiding of the formed nitride film to prevent peeling. The semiconductor substrate isolation method according to the present invention comprises the steps of forming an ion buried layer by nitrogen ion implantation at a predetermined depth of the semiconductor substrate, and performing annealing on the semiconductor substrate on which the ion diffusion layer is formed under a predetermined temperature condition and a nitrogen and low pressure oxygen atmosphere. Forming an nitride film from the ion buried layer and forming an oxide film over the nitride film to insulate the upper and lower layers of the semiconductor substrate.
Description
본 발명은 반도체층 격리방법에 관한 것으로서, 특히, 반도체기판을 SIMNI(separation by implantation of nitrogen) 구조로 형성할 때 이온주입 및 어닐링 공정을 개선하여 반도체층인 실리콘층과 절연층의 계면에 결함을 개선하여 기판의 특성을 향상시키고 형성되는 질화막의 보이드 형성을 방지하여 필링(peeling)현상을 방지하도록한 질화막을 이용한 반도체기판 절연층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor layer isolation method. In particular, when the semiconductor substrate is formed in a separation by implantation of nitrogen (SIMNI) structure, ion implantation and annealing processes are improved to prevent defects at the interface between the silicon layer and the insulating layer. The present invention relates to a method for forming a semiconductor substrate insulating layer using a nitride film to improve the characteristics of the substrate and to prevent voiding of the formed nitride film to prevent peeling.
반도체 소자가 더욱 미세화됨에 따라 현재 사용되고 있는 실리콘기판을 개선한 기판중의 하나가 SIMNI 구조를 갖는 반도체기판이다. 반도체기판인 실리콘기판에 소자들을 형성하기 위한 소자분리방법중 SOI(silicon on insulator)방법이 있다. 그중 실리콘기판에 질소이온주입을 실시하여 기판 내부에 질화실리콘층을 형성하는방법을 SIMNI라 한다. SIMNI 구조를 갖는 반도체기판은 빠른 소자의 동작특성, 낮은 전압, 방사능에 대한 내성 등의 특성을 가지며 고집적 CMOS 소자, 동일 칩상에 형성된 바이폴라와 CMOS 소자 등에 사용된다.As semiconductor devices are further miniaturized, one of the substrates which improves the silicon substrate currently used is a semiconductor substrate having a SIMNI structure. A silicon on insulator (SOI) method is one of device isolation methods for forming devices on a silicon substrate, which is a semiconductor substrate. Among them, the method of forming a silicon nitride layer inside the substrate by injecting nitrogen ion into the silicon substrate is called SIMNI. A semiconductor substrate having a SIMNI structure has characteristics such as fast device operation characteristics, low voltage, and resistance to radiation, and is used for a high density CMOS device, bipolar and CMOS devices formed on the same chip.
도 1은 종래기술에 따른 반도체층 격리방법에 의하여 절연층이 형성된 기판 단면도이다.1 is a cross-sectional view of a substrate on which an insulating layer is formed by a semiconductor layer isolation method according to the prior art.
도 1을 참조하면, 반도체기판인 실리콘기판(10)에 이온주입기를 이용하여 질소를 소정의 농도와 에너지로 질소이온주입을 실시한다. 이때 이온주입기를 사용하는 이유는 기판의 내부에 형성될 절연층, 즉 질화실리콘층의 형성 두께와 기판(10) 표면으로 부터의 형성 깊이 그리고 농도를 정확하게 조절하여 균일한 특성을 얻기 위해서이며, 이온주입 파라미터는 에너지 180 KV와 도우즈(dose) 1.0E18/㎠ 정도로 한다.Referring to FIG. 1, nitrogen is implanted into a silicon substrate 10, which is a semiconductor substrate, using a ion implanter at a predetermined concentration and energy. In this case, the reason for using the ion implanter is to obtain uniform characteristics by precisely controlling the thickness of the insulating layer to be formed inside the substrate, that is, the silicon nitride layer, the depth of formation from the surface of the substrate 10, and the concentration. The injection parameters are about 180 KV of energy and about 1.0E18 / cm 2 dose.
이온주입된 실리콘기판의 실리콘의 결정구조가 깨어져 비정질화 되어 있으므로 이를 원상복구시키기 위하여 약 1200℃와 질소 및 낮은 압력의 산소분위기에서 기판에 어닐링을 소정시간 실시한다.Since the crystal structure of silicon in the ion implanted silicon substrate is broken and amorphous, the substrate is annealed at a temperature of about 1200 ° C. and nitrogen and a low pressure oxygen atmosphere for a predetermined time.
어닐링이 끝나면 기판의 전체적인 형태는 이온주입된 질소와 기판의 실리콘이 결합되어 질화실리콘층(110,111)이 기판 내부에 형성되고 이를 중심으로 상측에 소자 등이 형성될 상부 실리콘층(100)이 위치하고 질화실리콘층(111)의 하측에는 본래의 단결정으로 이루어진 하부 실리콘층(10)이 위치한다. 따라서, 기판이 소자 형성층(100)과 하부층(10)이 질화실리콘층으로 차단되는 SIMNI구조가 형성된다.After the annealing is completed, the overall shape of the substrate is ion-implanted nitrogen and silicon of the substrate are bonded to form silicon nitride layers (110, 111) inside the substrate, and the upper silicon layer (100) where the device is to be formed on the upper side and the nitride Below the silicon layer 111, the lower silicon layer 10 made of the original single crystal is positioned. Thus, a SIMNI structure is formed in which the substrate is blocked by the element formation layer 100 and the lower layer 10 by the silicon nitride layer.
그러나, 상술한 종래 기술에 따른 절연층 형성방법은 상부 실리콘층과 질화실리콘층(110)의 계면은 매끄럽지 못하고 다양한 결함이 존재하며, 질화실리콘층(110,111) 내부에는 공극(void, V)이 존재하여 반도체장치 제조공정 진행시 스트레스에 의하여 필링(peeling)이 발생하는 등의 제반 문제점이 있다.However, in the method of forming the insulating layer according to the related art, the interface between the upper silicon layer and the silicon nitride layer 110 is not smooth and various defects exist, and voids V exist in the silicon nitride layers 110 and 111. Therefore, there are various problems such as peeling due to stress during the semiconductor device manufacturing process.
따라서, 본 발명의 목적은 반도체기판을 SIMNI(separation by implantation of nitrogen) 구조로 형성할 때 이온주입 및 어닐링 공정을 개선하여 반도체층인 실리콘층과 절연층의 계면에 결함을 개선하여 기판의 특성을 향상시키고 형성되는 질화막의 보이드 형성을 방지하여 필링(peeling)현상을 방지하도록한 질화막을 이용한 반도체층 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to improve ion implantation and annealing processes when forming a semiconductor substrate with a SIMNI (separation by implantation of nitrogen) structure, thereby improving defects at the interface between the silicon layer and the insulating layer. The present invention provides a method of forming a semiconductor layer using a nitride film to improve and prevent voiding of a nitride film to be formed, thereby preventing peeling.
상기 목적을 달성하기 위한 본 발명에 따른 반도체층 격리방법은 반도체 기판의 소정 깊이에 질소 이온주입으로 이온매몰층을 형성하는 단계와, 소정 온도 조건 및 질소 및 저압 산소 분위기에서 이온배몰층이 형성된 반도체 기판에 어닐링을 실시하여 이온매몰층으로부터 질화막을 형성하고 질화막의 상부에 산화막을 형성하여 반도체 기판의 상층부와 하층부를 절연시키는 단계를 포함하여 이루어진다.The semiconductor layer isolation method according to the present invention for achieving the above object is a step of forming an ion buried layer by nitrogen ion implantation in a predetermined depth of the semiconductor substrate, a semiconductor in which the ion distribution layer is formed in a predetermined temperature conditions and nitrogen and low pressure oxygen atmosphere Annealing the substrate to form a nitride film from the ion buried layer, and forming an oxide film on the nitride film to insulate the upper and lower portions of the semiconductor substrate.
도 1은 종래 기술에 따른 반도체기판 격리방법에 의하여 절연층이 형성된 기판 단면도1 is a cross-sectional view of a substrate on which an insulating layer is formed by a semiconductor substrate isolation method according to the related art.
도 2는 본 발명에 따른 반도체기판 격리방법에 의하여 절연층이 형성된 기판 단면도Figure 2 is a cross-sectional view of the substrate formed with an insulating layer by a semiconductor substrate isolation method according to the present invention
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체층 격리방법에 의하여 절연층이 형성된 기판 단면도이다.2 is a cross-sectional view of a substrate on which an insulating layer is formed by a semiconductor layer isolation method according to the present invention.
도 2를 참조하면, 반도체기판인 실리콘기판(20)에 이온주입기를 이용하여 질소를 소정의 농도와 에너지로 질소이온주입을 실시한다. 이때 이온주입기를 사용하는 이유는 기판의 내부에 형성될 절연층, 즉 질화실리콘층의 형성 두께와 기판 표면으로 부터의 형성 깊이 그리고 농도를 정확하게 조절하여 균일한 특성을 얻기 위해서이며, 본 발명에서의 이온주입 파라미터는 에너지 100 KV와 도우즈(dose) 1.0E17-3.0E17 이온/㎠ 범위중 약 2.0E17 ions/㎠ 정도로 한다.Referring to FIG. 2, nitrogen is implanted into a silicon substrate 20, which is a semiconductor substrate, using a ion implanter at a predetermined concentration and energy. In this case, the reason for using the ion implanter is to obtain uniform characteristics by precisely controlling the thickness of the insulating layer to be formed inside the substrate, that is, the forming depth and concentration from the surface of the substrate. The ion implantation parameters are about 2.0E17 ions / cm 2 in the range of 100 KV of energy and 1.0E17-3.0E17 ions / cm 2 dose.
이온주입된 실리콘기판의 실리콘의 결정구조가 깨어져 비정질화 되어 있으므로 이를 원상복구시키기고 또한 절연층인 질화막(21)과 산화막(22) 형성을 위하여 약 1300℃와 질소 및 낮은 압력의 산소분위기에서 기판에 어닐링을 소정시간 실시한다. 이때, 실시가능 어닐링 온도범위는 1300-1400℃이다.Since the crystal structure of silicon in the ion implanted silicon substrate is broken and amorphous, the substrate is recovered at about 1300 ° C. and nitrogen and low pressure oxygen atmosphere to recover the original shape and to form the nitride layer 21 and the oxide layer 22 as insulating layers. Annealing is performed for a predetermined time. At this time, the practical annealing temperature range is 1300-1400 ° C.
어닐링이 끝나면 기판의 전체적인 형태는 이온주입된 질소와 기판의 실리콘이 결합되어 질화실리콘층(Si3N4,21)이 기판 내부에 형성되고 이를 중심으로 상측에 소자 등이 형성될 실리콘층(200)이 형성되고 질화실리콘층(21)의 하측에는 본래의 단결정으로 이루어진 하부 실리콘층(20)이 위치한다. 따라서, 기판이 소자 형성층(200)과 하부층(20)이 질화실리콘층(21)으로 차단되는 SIMNI구조가 형성된다.After the annealing is completed, the overall shape of the substrate is a silicon layer (200) in which silicon nitride layers (Si 3 N 4 , 21) are formed inside the substrate by forming ion-nitrogen nitrogen and silicon on the substrate, and an element or the like is formed thereon. ) Is formed and the lower silicon layer 20 made of the original single crystal is located below the silicon nitride layer 21. Thus, a SIMNI structure is formed in which the substrate is blocked by the element formation layer 200 and the lower layer 20 by the silicon nitride layer 21.
본 발명에서는 실리콘기판에 질소 이온주입을 실시하고 고온인 약 1300℃에서 질소 및 저압의 산소분위기에서 열처리를 실시하였으므로 상부 실리콘층(200)과 질화실리콘층(21) 사이에 양질의 얇은 신화막(SiO2,22)이 형성되었고, 또한 이러한 산화막(22)과 상부 실리콘층(200) 사이의 계면은 아주 매끄럽고 결함도 존재하지 않는다.In the present invention, since nitrogen ion implantation is performed on the silicon substrate and heat treatment is performed in a nitrogen and low pressure oxygen atmosphere at a high temperature of about 1300 ° C., a thin thin film of high quality between the upper silicon layer 200 and the silicon nitride layer 21 ( SiO 2 , 22 was formed, and the interface between the oxide film 22 and the upper silicon layer 200 was very smooth and there were no defects.
왜냐하면, 질소 이온주입 에너지를 종래 기술에서의 180KV에서 100KV로 약화시키고대신 어닐링 온도를 1200℃에서 1300℃로 상승시켰으므로 어닐링공정시 산소가 기판 표면으로부터 용이하게 기판내로 침투하여 산화막(22)을 형성할 수 있고, 또한, 고온 공정이므로 종래 기술과 다르게 질화실리콘층(21)의 보이드가 질화실리콘층의 상부로 이동하여 결함(defect)부위와 결합하여 소멸되기 때문이다. 그리고, 계면 부위가 매끄러운 이유는 이온주입 에너지를 낮추었으므로 질소이온이 실리콘기판에 분포하는 면적이 상대적으로 작기 때문이다.Because the nitrogen ion implantation energy was weakened from 180KV to 100KV in the prior art and the annealing temperature was raised from 1200 ° C to 1300 ° C, oxygen easily penetrated from the substrate surface into the substrate during the annealing process to form the oxide film 22. This is because the void of the silicon nitride layer 21 moves to the upper part of the silicon nitride layer and dissipates in combination with a defect site because it is a high temperature process. The reason why the interface portion is smooth is that the ion implantation energy is lowered, so that the area where nitrogen ions are distributed on the silicon substrate is relatively small.
따라서, 본 발명은 기판의 상층부와 하층부를 질화실리콘층으로 격리시키기 위하여 질화실리콘층과 상부 실리콘층 사이에 산화막을 형성하여 질화실리콘층 내부의 보이드를 소멸시켜 필링 현상을 개선하고 계면의 결함을 제거하여 반도체기판 특성을 개선하는 장점이 있다.Accordingly, the present invention forms an oxide film between the silicon nitride layer and the upper silicon layer in order to isolate the upper and lower layers of the substrate from the silicon nitride layer to eliminate voids in the silicon nitride layer, thereby improving the peeling phenomenon and eliminating defects at the interface. There is an advantage to improve the semiconductor substrate characteristics.
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