KR0131551B1 - Circuit to change a down data - Google Patents

Abstract

The present invention relates to a downlink data changing circuit of a radio base station capable of changing a specific bit of downlink data on the IOM2 bus in a DECT radio base station based on a specific time of an exchange. To this end, the present modification circuit includes a high frequency clock generator for generating a predetermined high frequency signal; Means for generating a frame synchronization reset signal in synchronization with a clock signal provided by an FSC generated on an IOM2 bus unit and provided from a high frequency clock generation section; When the reset signal is generated from the frame synchronization reset signal generator, the DCL generated from the master controller of the IOM2 bus unit is counted, and the counted value is compared with a predetermined value specified from the outside, and the counted value is equal to the predetermined value. Comparison means for detecting a point having the same value; A gate signal generation unit which is started by an output signal of the comparing means and generates a gate signal for a predetermined DDN in synchronization with the DCL output from the IOM2 bus unit; A downlink data setting unit configured to set the first predetermined data applied from the outside to the first predetermined DDN to be transmitted during the period in which the gate signal is generated from the point where the DCL of the point having the same value is generated; A mask signal setting unit which sets a second predetermined data applied from the outside as a mask signal; A downlink data transmitter for selectively transmitting a second predetermined DDN and a first predetermined DDN to a slave controller; And a selection signal generation unit for generating a signal for controlling a selection mode of the downlink data transmission unit by ANDing the gate signal output from the gate signal generation unit and the mask signal provided from the mask signal setting unit.

Description

Downlink data change circuit of wireless base station

1 is a detailed circuit diagram illustrating an embodiment of a downlink data change circuit according to the present invention.

2 (a) to (h) are timing diagrams for respective parts of FIG.

* Explanation of symbols for main parts of the drawings

10: IOM2 bus unit 14: frame synchronization reset signal generator

20: high frequency clock generator (OSC) 24: comparison circuit

26: downlink data (DDN) setting unit 28: mask signal setting unit

30: gate signal generator 32: selection signal generator

34: downlink data transmission unit 36: I / O address decoder

The present invention relates to a connection device of a DECT (Digital European Codeless Telecommunication) wireless base station and an ISDN (Integrated Services Digital Network (ISDN)) exchange period, and in particular, a master IOM2 (ISDN Oriented Modulo) in a DECT wireless base station from an ISDN exchange. The present invention relates to a downlink data change circuit of a wireless base station for changing downlink data (also called down data or data down (DDN)) transmitted through a bus to a slave IOM2 bus. For connection with an ISDN exchange, the DECT radio base station is equipped with an ISDN communication controller for connection with the U interface, a D-channel controller for the D-channel processing, and a B-channel controller for the B-channel processing in transmitting information through the U interface. Is provided on the IOM2 bus.

However, because only the B and D channel controllers are provided on the IOM2 bus provided in the DECT radio base station, downlink data synchronization at the DECT radio base station cannot be synchronized with the ISDN exchange. That is, when it is necessary to match specific bits of downlink data of the DECT radio base station based on the specific time of the ISDN exchange, there is no means and a method for randomly manipulating the specific bits on the IOM2 bus. Congruence with time was not possible.

Accordingly, the present invention provides a downlink data changing circuit of a radio base station capable of changing a specific bit of downlink data on the IOM2 bus in a DECT radio base station based on a specific time of an exchange.

In order to achieve the above object, the downlink data changing circuit according to the present invention is a circuit for changing predetermined downlink data on a modular (IOM2) bus unit of an integrated telecommunication network connection method in a wireless base station having a master controller and a slave controller. A high frequency clock generator for generating a predetermined high frequency signal; A frame synchronous reset signal generator for starting a frame synchronous signal generated on the IOM2 bus unit and generating a short frame synchronous reset signal in synchronization with a clock signal provided from a high frequency clock generator; When a reset signal is generated from the frame synchronization reset signal generator, the data clock signal generated from the mast controller of the IOM2 bus unit is counted, and the counted value is compared with a predetermined value specified from the outside, and the counted value is predetermined. Comparison means for detecting a point having a value equal to the value; A gate signal generator which is started by an output signal of the comparing means and generates a gate signal for a predetermined downlink data in synchronization with a data clock (DCL) output from the IOM2 bus unit; Downlink data setting for setting the first predetermined data applied from the outside to the first predetermined downlink data (DDN) to be transmitted during the period in which the gate signal is generated from the point where the data clock (DCL) of the point having the same value is generated. part; A mask signal setting unit for setting the second predetermined data applied from the outside into a mask signal indicating whether the first predetermined downlink data is transmitted; A downlink data transmitter for selectively transmitting the second predetermined downlink data and the first predetermined downlink data transmitted from the master controller to the slave controller; And a selection signal generation unit generating a signal for controlling a selection mode of the downlink data transmission unit by ANDing the gate signal output from the gate signal generation unit and the mask signal provided from the mask signal setting unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a detailed circuit diagram of a downlink data change circuit of a wireless base station according to the present invention, which separates data received from an exchange into a D channel and a B channel, respectively, and performs downlink data processing to a terminal or another device in the wireless base station or Alternatively, the case in which the IOM2 bus unit 10 that performs data upstream from the other device of the wireless base station to the exchange is configured as the master controller 10A and the slave controller 10B.

The frame synchronization signal (hereinafter referred to as FSC), the data clock signal (hereinafter referred to as DCL), the uplink data (hereinafter referred to as DUP) and the downlink data (hereinafter referred to as DDN) between the illustrated master controller 10A and the slave controller 10B. ), A length of one frame is set to 125 mu sec, and each frame is divided by a frame synchronization signal. 192 DCL signals are generated in one frame period, and uplink and downlink data are transmitted one bit in two DCL periods, so that up to 96 bits of data can be transmitted in one frame period. However, not all 96 bits are used for information transmission. For example, in the case of 2B + D, voice information is transmitted using the B channel, and various control information is transmitted using the D channel.

In addition, the downlink data change circuit shown in FIG. 1 is a frame synchronization logic having a short duration based on the rising edge or falling edge of the FSC among the signals generated between the master controller 10A and the slave controller 10B. A frame synchronous reset signal generator 14 for generating a set signal, and a high frequency clock generator (hereinafter abbreviated as OSC) 20 for generating a predetermined high frequency clock signal and providing it to the frame synchronous reset signal generator 14 When the FSC is generated, the comparison circuit 24 counts the DCL signal and compares it with a predetermined value, a downlink data setting unit 26 corresponding to the specific DCL, and a mask signal indicating whether or not the specific data is masked for the specific DCL. The mask signal setting unit 28 to be set, the gate signal generation unit 30 to generate a gate signal for a specific DDN, and the original DDN and downlink data setting unit 26 generated by the master controller 10A. The apparatus further includes a downlink data transmitter 34 for selectively transmitting a specific DDN provided by the PDU and a selection signal generator 32 for generating a signal for controlling a selection mode of the downlink data transmitter 34.

The operation of the downlink data changing circuit configured as described above will be described in detail with reference to the timing diagram shown in FIG.

First, the frame synchronizing reset signal generator 14 sustains the frame synchronizing signal (FSC, hereinafter abbreviated as FSC) transmitted from the IOM2 bus unit 10 over one cycle 1T of the data clock signal DCL. Therefore, as shown in (a) and (b) of FIG. 2, it serves to reduce the one-level duration of the FSC signal for use from the first clock of the DCL signal. To this end, the frame synchronization reset signal generator 14 includes a plurality of D flip-flops DF11, DF12, and DF13, a plurality of buffers BUF11A and BUF12A, and an AND gate AND11A, as shown in FIG. To operate.

That is, the D flip-flops DF11, DF12, and DF13 are all preset when the system power is turned on to store a value of zero. Accordingly, 0 is output at the output terminal Q of each of the D flip-flops DF11, DF12, and DF13, and 1 is output at each inverting output terminal / Q. Then, when the bus controllers 10A and 10B of the IOM2 bus unit 10 start to transmit data on the IOM2 bus, an FSC signal and a DCL signal are generated. The generated FSC is transmitted to the clock stage CLK of the D flip-flop DF11.

When the input terminal D and the crystal stage / PR of the flip-flop DF11 are connected to the supply power supply Vcc and the FSC is applied through the clock terminal CLK as shown in FIG. 1 is output from the output terminal Q, and 0 is output from the inverting output terminal / Q. The signal output from the output terminal Q is transmitted to the input terminal D of the D flip-flop DF12 of the next stage. The signal output through the inverting output terminal / Q is a frame synchronization reset signal (FSC-FC), which is transmitted to the clear terminal of the counters COUNT 11 and 24A provided in the comparison circuit 24, and thus the counter 24A. ).

The D flip-flop DF12 connects the preset stage / PR to the supply power supply Vcc, and outputs a signal applied through the input terminal D in synchronization with the signal provided from the OSC 20. That is, after the FSC is generated, the signal applied to the input terminal D is output from the first rising edge of the high frequency clock signal having the period shown in FIG. 2C from the OSC 20. As a result of FSC, 1 is output from the output terminal Q of the D flip-flop DF11 and 1 is applied to the input terminal D of the D flip-flop DF12, so that 1 is output from the output terminal Q of the D flip-flop DF12. Is output. The signal at the output terminal (Q) is transmitted to the input terminal D of the D flip-flop DF13.

The D flip-flop DF13 connects the preset stage / PR to the supply power supply Vcc, and synchronizes the input terminal D in synchronization with a signal provided from the OSC 20, such as the D flip-flop DF12 described above. Output the signal applied through. Accordingly, after the FSC is generated, at the second rising edge of the clock signal transmitted from the OSC 20, the D flip-flop DF13 outputs 1 through the output terminal Q and 0 through the inverted output terminal / Q. Outputs

The buffers BUF11A and BUF12A are configured to transmit a signal transmitted through the inverted output terminal / Q of the D flip-flop DF13 as an input signal of one side of the AND gate AND11A. When 0 is output through the inverting output terminal / Q, 0 is transmitted to the AND gate AND11A.

The AND gate AND11A performs a logical AND operation on the reset signal / RESET applied from the outside and the signal transmitted from the buffer BUF12A. The output signal is transmitted to the reset terminal (/ RES) of the D flip-flops DF11, DF12, and DF13, respectively, and 0 is transmitted from the buffer BUF12A regardless of an externally provided reset signal. Reset all by providing 0 as the set terminal (/ RES).

Accordingly, when the OSC 20 is set to generate a clock frequency of several tens to hundreds of megabytes or more, the FSC is generated from the IOM2 bus unit 10 and then continues for two clock cycles of the OSC 20. A very short duration FSC (FSCFC) can be obtained. For example, the original frame synchronization signal has a duration of 700 nsec, and the FSC obtained by the frame synchronization reset signal generation unit 14 is set to have a duration of less than 700 nsec.

The comparison circuit 24 is generated from the IOM2 bus unit 10 after the buffer BUF 24b and the frame synchronization reset signal FSC-FC that hold a specific DCL value provided from the CPU (not shown) are generated. IOM2 bus unit (ICOM2) consists of counters (COUNT11, 24a) for counting DCLs and comparators (COM1, 24C) for outputting a result of comparing the DCL provided from the counter 24a with a specific DCL provided from the buffer 24b. Detects the point where the DCL generated from 10) matches the specific DCL.

That is, the counter 24a uses a general counter and resets the DCL applied through the clock terminal CLK when it is reset according to the frame synchronization reset signal FSC_FC transmitted from the frame synchronization reset signal generation unit 14. Count. For example, the number of rising edges of the applied DCL is counted, and the counting result is transmitted to the inputs A0 to A7 of the comparator 24c.

The buffer 24B is constituted by an element such as an 8-bit data latch D flip-flop 8DF to store a specific DCL value transmitted from a CPU (not shown), and the stored specific DCL value is stored in B0 to B0 of the comparator 24c. Transmit to B7 input terminal. The specific DCL value is the DCL of the downlink data to be changed. The buffer 24B is cleared by a reset signal / FESET applied from the outside, and writes and reads a specific DCL value in synchronization with a signal provided from the I / O address decoder 36.

The comparator 24c compares the DCL value transmitted from the counter 24a with the specific DCL value transmitted from the buffer 24b, outputs 1 if they match, and outputs 0 if they do not match. For example, when a value corresponding to a 2 m (where m is a positive integer) second DCL is set to a specific DCL value stored in the buffer 24b, where m is a positive integer, the comparator 24c Generates one level of data when the counting value of the counter 24a reaches the 2m-th DCL as shown in (d) of FIG. 2 (at the rising edge portion of the DCL). The output signal of the comparator 24c is transmitted to the gate signal generator 30.

The gate signal generator 30 is configured in the same manner as the frame synchronization reset signal generator 14 described above to generate a gate signal for a DCL period in which a specific DDN is transmitted. That is, the plurality of D flip-flops DF51, which are started with respect to the output signal of the comparison circuit 24 (state 1 according to the example described above) and which are provided in synchronization with the DCL signal output from the IOM2 bus unit 10, are provided. The DF52 and DF53, the buffers BUF21A and BUF22A, and the AND gate AND12A are driven in the same manner as the frame synchronous reset signal generator 14 described above.

That is, the D flip-flop DF51 is synchronized with the signal output from the comparison circuit 24, and the D flip-flops DF52, DF53 are driven in synchronization with the DCL signal output from the IOM2 bus unit 10, The inverted output signal / Q of the D flip-flop DF51 becomes a gate signal for a specific DDN. The inverted output signal / Q of the D flip-flop DF51 is output as 1 from the rising edge portion of the 2mth DCL data to the rising edge of the 2m + 2th DCL as shown in (e) of FIG. The output signal is transmitted to the selection signal generator 32.

The downlink data setting unit 26 is composed of one DF / F (DF21) to set a DDN for a specific DCL. That is, the power supply line is connected to the preset terminal / PRE, and the data D0 transmitted from an external CPU (not shown) in synchronization with the signal transmitted from the I / O address decoder 36 is stored in the DDN. do. That is, the specific data transmitted from the CPU is recorded using the signal transmitted from the I / O address decoder 36 as a clock signal, and stored after the predetermined time has elapsed by the clock signal following the I / O address decoder 36. Output data to a specific DDN. The output DDN is transmitted to the downlink data transmitter 34.

The mask signal setting unit 28 stores and provides a mask signal for a predetermined period when a change to a specific downlink signal is desired. The mask signal setting unit 28 is configured and operated in the same manner as the downlink data setting unit 26 described above. However, the data D1 applied through the input terminal D is a signal indicating a mask state as transmitted from a CPU not shown. When 0, only the original DDN is transmitted as shown in (g) of FIG. 1 is a case where a value set in the downlink data setting unit 26 is transmitted for a period of time until a specific DCL and the next DCL, as shown in (h) of FIG. This input data D1 is written to the D flip-flop DF31 and output in synchronization with the signal transmitted from the I / O address decoder 36. The output signal is transmitted to the selection signal generator 32.

The selection signal generator 32 includes an AND gate AND13A to logically multiply the gate signal output from the gate signal generator 30 and the masking signal output from the mask signal setup unit 28. The AND signal is transmitted to the downlink data transmitter 34.

The downlink data transmitter 34 is controlled by the select signal transmitted from the selector signal generator 32 and the original DDN signal transmitted from the IOM2 bus unit 10 and the specific DDN transmitted from the downlink data setter 26. Select one and transmit it to the slave controller 10B. That is, the original DDN data is selected and transmitted as shown in (g) or (h) of FIG.

As shown in (e) of FIG. 2, a specific DDN is selected and transmitted during the gate signal period generated from the gate signal generator 30. Accordingly, the existing DDN and the newly designated DDN can be synthesized and transmitted.

As described above, the present invention provides a circuit capable of changing a specific bit of downlink data on the IOM2 bus in a DECT wireless base station so as to be synchronized with a specific time of the exchange, thereby providing a desired signal among the signals transmitted from the ISDN exchange in the wireless base station. The advantage is that the part can be changed at any time by the structure used in the wireless section. For example, using the downlink data change circuit according to the present invention, voice data transmitted in a 64K PCM scheme at an exchange on an IOM2 bus of a wireless base station can be changed to 32K ADPCM or 13K QCELP or 8K QCELP.

Although the present invention has been described as the above-described embodiment, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (1)

A specific bit of a predetermined downlink data (DDN) is specified on a modular (IOM2) bus unit 10 of a comprehensive information network connection system in a wireless base station having a master controller 10A and a slave controller 10B. A downlink data change circuit for changing based on time, comprising: a high frequency clock generator (20) for generating a predetermined high frequency signal; A frame synchronization reset signal, which is started by a frame synchronization signal generated on the IOM2 bus unit 10 and generates a frame synchronization reset signal having a short duration in synchronization with a clock signal provided from the high frequency clock generation unit 20. Generation unit 14; When a reset signal is generated from the frame synchronization reset signal generator 14, the data clock signal DCL generated from the mast controller 10A of the IOM2 bus unit 10 is counted, and the counted value is externally counted. Comparison means (24) for detecting a point at which the counted value has a value equal to the predetermined value by comparing with a predetermined value designated by A gate signal generator (30) which is started by an output signal of the comparing means and generates a gate signal for a predetermined downlink data in synchronization with the data clock (DCL) output from the IOM2 bus unit (10); The first predetermined data applied from the outside is set as the first predetermined downlink data (DDN) to be transmitted during the period in which the gate signal is generated from the point where the data clock (DCL) of the point having the same value is generated. Downlink data setting unit 26; A mask signal setting unit 28 for setting the second predetermined data applied from the outside into a mask signal indicating whether the first predetermined downlink data is transmitted; A downlink data transmitter (34) for selectively transmitting the second predetermined downlink data and the first predetermined downlink data transmitted from the master controller (10A) to the slave controller (10B); Selecting to generate a signal for controlling the selection mode of the downlink data transmission unit 34 by ANDing the gate signal output from the gate signal generation unit 30 and the mask signal provided from the mask signal setting unit 28. Downlink data change circuit of a wireless base station, characterized in that it comprises a signal generator (32).