KR0125881Y1 - Semiconductor wafer etching device - Google Patents
Semiconductor wafer etching deviceInfo
- Publication number
- KR0125881Y1 KR0125881Y1 KR2019950024635U KR19950024635U KR0125881Y1 KR 0125881 Y1 KR0125881 Y1 KR 0125881Y1 KR 2019950024635 U KR2019950024635 U KR 2019950024635U KR 19950024635 U KR19950024635 U KR 19950024635U KR 0125881 Y1 KR0125881 Y1 KR 0125881Y1
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- Prior art keywords
- etching
- wafer
- chamber
- semiconductor wafer
- conveyor belt
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
- H01L21/67051—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly spraying means, e.g. nozzles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67742—Mechanical parts of transfer devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67754—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber horizontal transfer of a batch of workpieces
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Robotics (AREA)
- Weting (AREA)
- ing And Chemical Polishing (AREA)
Abstract
본 고안은 반도체 웨이퍼 에칭장치에 관한 것으로, 종래의 반도체 웨이퍼 에칭장치는 챔버의 출구쪽에서 웨이퍼의 에칭상태를 확인하고 속도를 조절하면 챔버의 내부를 진행하는 전체 웨이퍼의 속도가 영향을 받게되어 균일한 에칭이 어려운 문제점이 있었다.The present invention relates to a semiconductor wafer etching apparatus. In the conventional semiconductor wafer etching apparatus, if the etching state of the wafer is checked at the exit side of the chamber and the speed is adjusted, the speed of the entire wafer traveling through the inside of the chamber is affected and is uniform. There was a problem that etching is difficult.
본 고안 반도체 웨이퍼 에칭장치는 챔버(1)와 웨이퍼 아웃풋 인덱스(3) 사이에 에칭조절수단(10)을 설치하고, 1차적으로 에칭된 웨이퍼를 묽은 에칭용액으로 미세하게 속도를 조절하며 에칭상태를 균일하게 조절함으로써 에칭을 균일하게 할 수 있을뿐 아니라 그 조절이 용이한 효과가 있다.In the semiconductor wafer etching apparatus of the present invention, the etching control means 10 is provided between the chamber 1 and the wafer output index 3, and the first etching wafer is finely controlled with a thin etching solution and the etching state is adjusted. By uniformly adjusting, not only the etching can be made uniform but also the effect is easy to adjust.
Description
제1도는 종래 반도체 웨이퍼 에칭장치의 구성을 보인 개략구성도.1 is a schematic configuration diagram showing a configuration of a conventional semiconductor wafer etching apparatus.
제2도는 본 고안 반도체 웨이퍼 에칭장치의 구성을 보인 개략구성도.2 is a schematic diagram showing the configuration of the inventive semiconductor wafer etching apparatus.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 챔버 2 : 웨이퍼 인풋 인덱스1,11 chamber 2: wafer input index
3 : 웨이퍼 아웃풋 인덱스 4,12 : 에칭용액 공급라인3: wafer output index 4, 12: etching solution supply line
7,16 : 컨베이어 벨트 10 : 에칭조절수단7,16: conveyor belt 10: etching control means
12a : 분사노즐 13 : 구동모터12a: injection nozzle 13: drive motor
14 : 롤러 17a : 속도 조절밸브14 roller 17a speed control valve
17 : 속도 조절부 18 : 관찰구17: speed control unit 18: observation port
본 고안은 반도체 웨이퍼 에칭장치에 관한 것으로, 특히 에칭조절수단을 설치하여 정확하고 균일한 웨이퍼 에칭을 하도록 하는데 적합한 반도체 웨이퍼 에칭장치에 관한 것이다.The present invention relates to a semiconductor wafer etching apparatus, and more particularly, to a semiconductor wafer etching apparatus suitable for providing accurate and uniform wafer etching by providing etching control means.
현상된 웨이퍼를 최종 베이크 한 후에는 에칭(ETCHING)을 실시하게 되는데, 상온에서 약 10 내지 250초 동안 이루어진다.After final baking of the developed wafer, etching is performed, which takes about 10 to 250 seconds at room temperature.
제1도는 상기와 같은 종래 반도체 웨이퍼 에칭장치의 구성을 보인 개략구성도이다.1 is a schematic block diagram showing the configuration of a conventional semiconductor wafer etching apparatus as described above.
도시된 바와 같이, 종래의 반도체 웨이퍼 에칭장치는 장비의 본체를 이루는 챔버(1)의 양측에 웨이퍼 인풋 인덱스(2)와 웨이퍼 아웃풋 인덱스(3)가 각각 설치되어 있다.As shown, the conventional semiconductor wafer etching apparatus is provided with a wafer input index 2 and a wafer output index 3 on both sides of the chamber 1 constituting the main body of the equipment.
그리고, 상기 챔버(1)의 내부에는 에칭용액을 분사하기 위하여 수개의 분사노즐(4a)을 구비한 에칭용액 공급라인(4)이 설치되어 있고, 그 에칭용액 공급라인(4)의 하부에는 구동모타(5)에 의해 회전하는 수개의 롤러(6)와 그 롤러(6)에 감겨진 상태로 회전하는 컨베이어 벨트(7)로 구성되어 있다.In addition, an etching solution supply line 4 having several injection nozzles 4a is provided inside the chamber 1 to inject an etching solution, and a lower portion of the etching solution supply line 4 is driven. It consists of several rollers 6 which rotate by the motor 5, and the conveyor belt 7 which rotates in the state wound by the rollers 6. As shown in FIG.
또한, 상기 챔버(1)의 상부에는 상기 컨베이어 벨트(7)의 속도를 조절하기 위한 속도 조절밸브(8a)가 구비된 속도 조절부(8)가 설치되어 있고, 상기 챔버(1)의 상면 웨이퍼 아웃풋 인덱스(3) 방향에는 웨이퍼(W)의 에칭상태를 관찰하기 위한 관찰구(9)가 설치되어 있다.In addition, the upper portion of the chamber (1) is provided with a speed adjusting unit (8) having a speed control valve (8a) for adjusting the speed of the conveyor belt (7), the upper wafer of the chamber (1) An observation port 9 for observing the etching state of the wafer W is provided in the output index 3 direction.
상기와 같이 구성되어 있는 종래의 반도체 웨이퍼 에칭장치의 동작을 제1도를 참조하여 설명하면 다음과 같다.The operation of the conventional semiconductor wafer etching apparatus constructed as described above will be described with reference to FIG.
구동모터(5)에 전원이 인가되면 롤러(6)가 회전되며, 그 롤러(6)에 감겨있는 컨베이어 벨트(7)가 회전하게 된다.When power is applied to the drive motor 5, the roller 6 is rotated, and the conveyor belt 7 wound around the roller 6 is rotated.
이와 같이 컨베이어 벨트(7)가 회전하는 상태에서 웨이퍼 인풋 인덱스(2)에 수납되어 있던 웨이퍼(W)를 컨베이어 벨트(7)의 상면에 공급하고, 그 웨이퍼(W)가 컨베이어 벨트(7)의 상면에 올려진 상태로 이동하는 동안 에칭용액 공급라인(4)의 분사노즐(4a)로 에칭용액이 분사되어 웨이퍼(W)를 에칭하게 된다.Thus, the wafer W accommodated in the wafer input index 2 is supplied to the upper surface of the conveyor belt 7 in the state in which the conveyor belt 7 rotates, and the wafer W of the conveyor belt 7 While moving on the upper surface, the etching solution is injected into the injection nozzle 4a of the etching solution supply line 4 to etch the wafer W.
상기와 같이 챔버(1)의 내부에서 웨이퍼(W)가 이동하는 동안 에칭이 진행된 상태를 웨이퍼 아웃풋 인덱스(3) 방향의 챔버(1) 상면에 설치되어 있는관찰구(9)로 확인하고, 웨이퍼(W)가 챔버(1)의 내부를 빠져나오기 전에 에칭이 이루어지도록 속도 조절밸브(8a)로 컨베이어 벨트(7)의 속도를 조절한다.As described above, the state in which the etching is performed while the wafer W moves inside the chamber 1 is confirmed by the observation hole 9 provided on the upper surface of the chamber 1 in the wafer output index 3 direction, and the wafer The speed of the conveyor belt 7 is adjusted by the speed regulating valve 8a so that etching is performed before W exits the inside of the chamber 1.
즉, 상기 관찰구(9)로 웨이퍼(W)의 에칭정도를 색으로 관찰하여 에칭이 이루어지지 않았을 경우에 컨베이어 벨트(7)의 속도를 느리도록 하여 에칭량을 많게 함으로써 웨이퍼(W)가 챔버(1)의 내부를 빠져나오기 전에 충분한 에칭이 진행되도록 하는 것이다.That is, the wafer W is chambered by increasing the amount of etching by slowing the speed of the conveyor belt 7 when the etching degree of the wafer W is observed in color through the observation port 9. Sufficient etching advances before leaving the inside of (1).
그러나, 상기와 같은 종래의 반도체 웨이퍼 에칭장치는 챔버(1)의 출구쪽에 설치되어 있는 관찰구(9)로 웨이퍼(W)의 에칭상태를 확인하여 속도 조절밸브(8a)로 컨베이어 벨트(7)의 속도를 조절하게 되는데, 이때 챔버(1) 출구쪽의 웨이퍼(W)의 에칭상태를 확인하고 컨베이어 벨트(7)의 속도를 조절하게 되면 챔버(1)의 입구나 중간부의 컨베이어 벨트(7) 상면에 위치하고 있는 웨이퍼(W) 전체의 속도가 느려지거나 혹은 빨라지게 되어 웨이퍼(W)의 에칭이 균일하지 못한 문제점이 있었고, 또한 조절이 어려운 문제점이 있었다.However, the conventional semiconductor wafer etching apparatus as described above checks the etching state of the wafer W with the observation port 9 provided at the outlet side of the chamber 1, and the conveyor belt 7 with the speed regulating valve 8a. In this case, the etching state of the wafer (W) at the exit side of the chamber (1) is checked, and the speed of the conveyor belt (7) is adjusted, and the conveyor belt (7) at the inlet or the middle of the chamber (1) is adjusted. There was a problem that the etching of the wafer W was not uniform because the speed of the entire wafer W located on the upper surface was slowed or increased, and it was difficult to adjust.
본 고안의 목적은 컨베이어 벨트의 속도를 미세하게 조절하고, 농도가 묽은 에칭용액을 사용하여 웨이퍼의 에칭을 조절하는 에칭조절수단을 설치하여 웨이퍼를 균일하게 에칭하는데 적합한 반도체 웨이퍼 에칭장치를 제공함에 있다.It is an object of the present invention to provide a semiconductor wafer etching apparatus suitable for uniformly etching a wafer by installing etching control means for finely controlling the speed of the conveyor belt and controlling the etching of the wafer using a thinner etching solution. .
본 고안의 다른 목적은 웨이퍼의 에칭상태의 조절이 용이한 반도체 웨이퍼 에칭장치를 제공함에 있다.Another object of the present invention is to provide a semiconductor wafer etching apparatus that is easy to control the etching state of the wafer.
상기와 같은 본 고안의 목적을 달성하기 위하여 챔버의 양측에 웨이퍼 인풋 인덱스와 웨이퍼 아웃풋 인덱스가 각각 설치되고, 챔버의 내부에 에칭용액 공급라인과 웨이퍼를 이동시키는 컨베이어 벨트가 설치되어 있는 반도체 웨이퍼 에칭장치에 있어서, 상기 챔버와 웨이퍼 아웃풋 인덱스 사이에 설치하여 웨이퍼의 에칭을 균일하게 조절하기 위한 에칭 조절수단을 포함하여서 구성된 것을 특징으로 하는 반도체 웨이퍼 에칭장치가 제공된다.In order to achieve the object of the present invention as described above, the wafer input index and the wafer output index are respectively provided on both sides of the chamber, and the semiconductor wafer etching apparatus is provided with a conveyor belt for moving the etching solution supply line and the wafer inside the chamber. A semiconductor wafer etching apparatus is provided, comprising etching control means for uniformly adjusting the etching of a wafer provided between the chamber and the wafer output index.
상기 에칭조절수단은 챔버의 내부에 분사노즐이 구비된 에칭용액 공급라인이 설치되고, 그 에칭용액 공급라인의 하부에는 구동모터에 의해 회전하는 롤러가 수개 서리되며, 그 롤러에 감겨진 상태로 웨이퍼를 이동시키는 컨베이어 벨트가 설치되고, 상기 챔버의 상부에는 속도 조절밸브가 구비된 속도 조절부가 설치되며, 상기 챔버의 상면에 웨이퍼의 에칭상태를 관찰하기 위한 관찰구가 설치되어 있는 것을 특징으로 한다.The etching control means is provided with an etching solution supply line having an injection nozzle inside the chamber, and several rollers rotating by a driving motor are frosted under the etching solution supply line, and the wafer is wound on the roller. Conveyor belt for moving the is installed, the speed control unit provided with a speed control valve is installed on the upper portion of the chamber, characterized in that the observation port for observing the etching state of the wafer is installed on the upper surface of the chamber.
이하, 상기와 같이 구성되어 있는 본 고안의 반도체 웨이퍼 에칭장치의 실시예를 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of a semiconductor wafer etching apparatus of the present invention configured as described above will be described in more detail with reference to the accompanying drawings.
제2도는 본 고안 반도체 웨이퍼 에칭장치의 구성을 보인 개략구성도로서, 도시된 바와 같이, 본 고안의 반도체 웨이퍼 에칭장치는 챔버(1)의 양측에 웨이퍼 인풋 인덱스(2)와 웨이퍼 아웃풋 인덱스(3)가 각각 설치되어 있고, 상기 챔버(1)의 내부에는 에칭용액을 분사하기 위하여 수개의 분사노즐(4a)을 구비한 에칭용액 공급라인(4)이 설치되어 있으며, 그 에칭용액 공급라인(4)의 하부에는 구동모타(5)에 의해 회전하는 수개의 롤러(6)와 그 롤러(6)에 감겨진 상태로 회전하는 컨베이어 벨트(7)가 설치되어 있고, 상기 챔버(1)의 상부에는 상기 컨베이어 벨트(7)의 속도를 조절하기 위한 속도 조절밸브(8a)가 구비된 속도 조절부(8)가 설치되어 있는 구성은 종래와 같다.2 is a schematic configuration diagram showing the structure of the semiconductor wafer etching apparatus of the present invention. As shown in the drawing, the semiconductor wafer etching apparatus of the present invention has a wafer input index 2 and a wafer output index 3 at both sides of the chamber 1. Are respectively provided, and an etching solution supply line 4 having several injection nozzles 4a is provided in the chamber 1 to inject the etching solution. In the lower part of), several rollers 6 rotated by the driving motor 5 and a conveyor belt 7 which rotates while being wound around the rollers 6 are installed. The configuration in which the speed control unit 8 provided with the speed control valve 8a for controlling the speed of the conveyor belt 7 is installed.
여기서, 본 고안은 상기 챔버(1)와 아웃풋 인덱스(3) 사이에 설치하여 웨이퍼(W)의 에칭을 균일하게 조절하기 위한 에칭조절수단(10)을 설치한 것을 특징으로 한다.Here, the present invention is characterized in that the etching control means 10 is installed between the chamber 1 and the output index 3 to uniformly control the etching of the wafer (W).
상기 에칭조절수단(10)은 챔버(11)의 내부에 분사노즐(12a)이 구비된 에칭용액 공급라인(12)이 설치되고, 그 에칭용액 공급라인(12)의 하부에는 구동모타(13)에 의해 회전하는 롤러(14)가 수개 설치되며, 그 롤러(14)에 감겨진 상태로 웨이퍼(W)를 이동시키는 컨베이어 벨트(16)가 설치되고, 상기 챔버(11)의 상부에는 속도 조절밸브(17a)가 구비된 속도 조절부(17)가 설치되며, 상기 챔버(11)의 상면에 웨이퍼(W)의 에칭상태를 관찰하기 위한 관찰구(18)가 설치되어 있는 것을 특징으로 한다.The etching control means 10 is provided with an etching solution supply line 12 having an injection nozzle 12a inside the chamber 11, and a driving motor 13 below the etching solution supply line 12. The roller 14 which rotates by several is provided, The conveyor belt 16 which moves the wafer W in the state wound by the roller 14 is provided, The speed control valve is provided in the upper part of the chamber 11. A speed adjusting unit 17 provided with a 17a is provided, and an observation port 18 for observing the etching state of the wafer W is provided on the upper surface of the chamber 11.
그리고, 상기 관찰구(18)는 상기 챔버(11)의 상면에 길이방향으로 길게 형성하여 에칭조절수단(10)의 챔버(11) 내부를 이동하는 웨이퍼(W)의 에칭상태를 챔버(11)의 입구쪽으로 출구쪽까지 넓은 범위에서 확인할 수 있도록 하였다.In addition, the observation port 18 is formed on the upper surface of the chamber 11 in the longitudinal direction to move the etching state of the wafer (W) to move inside the chamber 11 of the etching control means 10 chamber 11 From the inlet side of the exit to the wide range can be confirmed.
상기 도면중 미설명부호 19는 에칭용액을 공급하는 에칭용액 탱크이다.In the figure, reference numeral 19 denotes an etching solution tank for supplying an etching solution.
상기와 같이 구성되어 있는 본 고안 반도체 웨이퍼 에칭장치의 동작을 제2도를 참조하여 설명하면 다음과 같다.The operation of the inventive semiconductor wafer etching apparatus constructed as described above will be described with reference to FIG.
에칭조절수단(10)외의 동작은 종래와 동일하므로 상세한 설명은 생략하고, 여기서는 에칭조절수단(10)을 중심으로 설명한다.Since the operation other than the etching control means 10 is the same as in the prior art, a detailed description thereof will be omitted, and the description will be given with reference to the etching control means 10.
상기 컨베이어 벨트(16)의 상면에 1차적으로 에칭이 진행된 웨이퍼(W)가 공급되고, 상기 구동모터(13)의 회전에 의하여 롤러(14)가 회전하면 컨베이어 벨트(16)의 상면에 공급된 웨이퍼(W)가 챔버(11)의 입구쪽에서 출구쪽으로 이동하게 되는데, 이때 상기 컨베이어 벨트(16)는 상기 속도 조절밸브(17a)에 의해 조절되어 미세하게 움직이고, 또한 상기 에칭용액 공급라인(12)에는 묽은 상태의 에칭용액을 공급하여 분사노즐(17a)를 통하여 웨이퍼(W)에 분사한다.The wafer W, which is primarily subjected to etching, is supplied to the upper surface of the conveyor belt 16. When the roller 14 rotates by the rotation of the driving motor 13, the wafer W is supplied to the upper surface of the conveyor belt 16. The wafer W is moved from the inlet side to the outlet side of the chamber 11, wherein the conveyor belt 16 is finely moved by the speed control valve 17a, and the etching solution supply line 12 is also moved. To the wafer W, a thin etching solution is supplied to the wafer W through the injection nozzle 17a.
이와 같이 이동되며 에칭상태가 조절되는 웨이퍼(W)를 챔버(11)의 상면에 형성된 관찰구(18)를 통하여 확인하고, 웨이퍼(W)의 에칭이 많이 진행됐으면 속도 조절밸브(17a)를 이용하여 컨베이어 벨트(16)의 속도를 빠르게하고, 에칭이 조금 진행됐으면 속도를 느리게 조절하여 에칭량을 균일하게 조절하는 것이다.The wafer W, which is moved in this manner and whose etching state is controlled, is checked through the observation port 18 formed on the upper surface of the chamber 11, and when the etching of the wafer W has proceeded a lot, the speed control valve 17a is used. By increasing the speed of the conveyor belt 16, if the etching is a little progress is to slow the speed to adjust the amount of etching uniformly.
이상에서 상세히 설명한 바와 같이 본 고안의 반도체 웨이퍼 에칭장치는 챔버와 웨이퍼 아웃풋 인덱스 사이에 에칭조절수단을 설치하고, 1차적으로 에칭된 웨이퍼를 묽은 에칭용액으로 미세하게 속도를 조절하며 에칭상태를 균일하게 조절함으로써 에칭을 균일하게 할 수 있을뿐 아니라 그 조절이 용이한 효과가 있다.As described in detail above, in the semiconductor wafer etching apparatus of the present invention, an etching control means is provided between the chamber and the wafer output index, the first etched wafer is finely controlled with a thin etching solution, and the etching state is uniform. By adjusting, not only the etching can be made uniform but also the effect is easy to adjust.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950024635U KR0125881Y1 (en) | 1995-09-13 | 1995-09-13 | Semiconductor wafer etching device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR2019950024635U KR0125881Y1 (en) | 1995-09-13 | 1995-09-13 | Semiconductor wafer etching device |
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| KR0125881Y1 true KR0125881Y1 (en) | 1998-11-02 |
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| KR100770047B1 (en) * | 2006-05-30 | 2007-10-26 | 세종대학교산학협력단 | Etching device and method for electroless plating |
| KR101756743B1 (en) | 2016-12-30 | 2017-07-12 | 김태훈 | Buffer chamber unit for wafer fabricating equipment |
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