KR0125780B1 - Semiconductor memory cell and its manufacture - Google Patents

Abstract

A semiconductor memory cell and method thereof are disclosed. The semiconductor memory cell comprises a capacitor and a switching transistor formed at an active region, and connected to a bit line and an word line. A storage electrode of the capacitor has a tube-shaped structure entirely surrounding the bit line of desired length. Also, the tube axis of the storage electrode of the capacitor is arranged to same direction as the arranged direction of the source, gate and drain of the switching transistor. The active region is arranged to horizontal direction to the bit line and to vertical direction to the line.

Description

Semiconductor memory cell and manufacturing method thereof

1 is a view and layout showing a conventional memory cell manufacturing method.

2 is a layout of a memory cell manufacturing method according to the present invention,

3 is a cross-sectional view for explaining a first embodiment of a method of manufacturing a memory cell according to the present invention;

4 is a cross-sectional view for explaining a second embodiment of the method for manufacturing a memory cell according to the present invention.

* Description of the symbols for the main parts of the drawings *

10,31 active region 11,30 silicon substrate

12,22: field oxide film 13,33: gate: word line

1,344: source and drain regions 35,38,43: oxide film

15 polysilicon: bit line 17,39: oxide film sidewall

18: storage electrode 37, 41, 42, 45: polysilicon

42: metal layer film 51, 53: nitride film

6,19,55: dielectric film 20,56: plate polysilicon

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell and a method of fabricating the same, and in particular, to form a capacitor node electrode in a tunnel shape so that bit lines pass therethrough to reduce distortion of patterning, and to increase capacitor capacity and capacitor capacity. It relates to a memory cell.

Stacked capacitor cells (Stacked) announced as a shielded bit line structure in which a capacitor is formed on a bit line, which is one of the conventional methods for manufacturing a memory cell and its layout, which is considered to be the technology closest to the present invention. Capacitor Cell) and the method of manufacturing the same are shown in FIG.

One such prior art is described in 12.13.1990 issued U.S. Pat, No. 4970546.

(E) of FIG. 1 shows the layout, in which the active region 10 in which the element is formed is defined. The bit line and the word line which meet at right angles to each other are inclined at an angle of 45 ° so that they partially overlap with the storage electrode 18 and the bit line to be densely distributed. To make it possible. (A)-(D) of FIG. 1 is sectional drawing of the A-A line of FIG.

The manufacturing method first distinguishes a field region from an active region on a semiconductor substrate as shown in FIG. 1A, and then source and drain regions 12 on the active region. The gate 13 electrode is formed, the oxide layer 14 for insulating the gate electrode 14 is deposited, and a bit line contact is opened by a photolithography process.

Subsequently, as shown in FIG. 1B, the bit line wiring film 15 and the oxide film 16, which are made of a high melting point metal or silicide, are deposited and then patterned using a photosensitive film as a mask. After forming (15), the photosensitive film is removed.

Subsequently, as shown in FIG. 1C, the oxide film is deposited and etched back without the photoresist mask to form the oxide film 17 on the sidewalls of the bit lines 15, and then the active region and storage. The buried contact to which the electrode is connected is formed.

Next, as shown in FIG. 1D, the storage electrode 18, the capacitor dielectric film 19, and the plate electrode 20 are formed in this order to fabricate a memory cell.

In the conventional cell fabricated in this way, as shown in FIG. 1, the bit line 15 and the word line 13 are orthogonal to each other, and the active region 10 is arranged obliquely with respect to the bit line and the word line. .

In addition, since the bit line 15 is formed before the capacitor, the contact between the storage electrode and the active region of the capacitor should be formed at a position where the bit line does not pass. Therefore, the active area is diagonally formed with respect to the bit line and the word line. It should be arranged as much as possible.

Therefore, since there is a portion where the active region, which is to pattern the active region of the cell, forms an angle of 45 ° with the gate and the bit line, distortion of the pattern occurs in the photolithography process, and thus, there is a difficulty in the process. Will increase.

In the present invention, in order to solve these problems, the bit line is formed to pass through the storage node electrode of the capacitor, and the active region, the bit line, the capacitor, and the like are three-dimensionally overlapped.

That is, in a memory cell composed of a switching transistor and a capacitor, the storage electrode of the capacitor is formed to surround the bit line, so that the active region is formed in a parallel or overlapping direction with respect to the bit line and a vertical direction with respect to the word line. Therefore, the unit cell (switching transistor + capacitor) is made into a straight line.

An object of the present invention is to provide a gate, a source and a drain formed in the active region of the semiconductor substrate, a first polysilicon connected to the source region of the active region and formed on the gate, a first insulating film formed on the first polysilicon; A bit line comprising a second polysilicon connected to the drain region of the active region and formed on the first insulating film, a high melting point metal formed on the second polysilicon, a second insulating film formed on the bit line, and a second insulating film And a storage electrode formed of a third polysilicon formed thereon and connected to the first polysilicon, the semiconductor memory cell comprising a capacitor connected to a bit line and a word line and a switching transistor formed in an active region. A semiconductor memory cell having a tubular structure in which a storage electrode of a capacitor completely surrounds a bit line of a predetermined length is formed. Is to provide.

Another object of the present invention is to provide a semiconductor memory cell in which the source gate drain of the switching transistor and the tube longitudinal axis of the storage electrode of the capacitor are in the same direction, and the first polysilicon and the third polysilicon are connected to the sidewall protrusion.

The method of the present invention comprises the steps of (1) forming a field oxide film as an active region in which a device is formed and a device isolation region on a silicon substrate, and then forming a switching transistor by forming a gate, a source and a drain, and (2) a first oxide film. After depositing the buried contact by the exposure etching process and depositing the first polysilicon on the entire wafer, the second oxide film is deposited, and the second oxide film is parallel to the direction perpendicular to the length rectangle of the active region. And forming a portion of the capacitor storage electrode connected to the source of the switching transistor by patterning the first polysilicon film. (3) Deposition and etch back the oxide film on the front surface, and an oxide film sidewall next to the patterned first polysilicon film. (4) opening the bit line contact by a photolithography process, depositing the second polysilicon and etching back only the appropriate thickness, and then forming eutectic gold on it. After the film to position and a third position having the oxide film. Patterning the third oxide film, the high melting point metal film, and the second polysilicon in parallel to the longitudinal axis of the active region to form a bit line; (5) depositing the fourth oxide film and exposing the fourth oxide film and the surface; Patterning the oxide film parallel to the longitudinal axis of the active region by a photolithography process, (6) depositing a third polysilicon layer, and patterning the third polysilicon film and the first polysilicon film by photolithography process Forming a capacitor storage electrode, (7) coating a capacitor dielectric film on the surface of the capacitor storage electrode, and forming a plate electrode of the capacitor thereon.

Furthermore, (1) forming a field oxide film as an active region and a device isolation region on which a device is formed on a silicon substrate, and then forming a switching transistor by forming a gate, a source and a drain, and (2) forming a first oxide film. Position and open the buried contact by an exposure etching process, deposit the first polysilicon on the entire wafer, deposit the second oxide film, and deposit the second oxide film and the second oxide film in parallel to the direction perpendicular to the longitudinal direction of the active region. Patterning the polysilicon film to form a portion of the capacitor storage electrode connected to the source of the switching transistor; and (3) depositing an oxide film on the front surface and etching back to form an oxide sidewall next to the patterned first polysilicon film. Forming, (4) opening the bit line contact by photolithography process, depositing the second polysilicon and etching back only the appropriate thickness, and then And depositing a third oxide film, and then patterning the third oxide film, the high melting point metal film, and the second polysilicon in parallel to the longitudinal axis of the active region to form a bit line, (5) the oxide film and the poly Deposition a first insulating film made of an insulating material having a high etch selectivity in silicon, patterning the first insulating film to cover the bit line in parallel with the bit line, depositing the third polysilicon and etching the oxide film and polysilicon thereon Depositing a second insulating film made of a highly selective insulating material and patterning the second to cover the bit line in parallel with the bit line by a photolithography process; (6) a third polysilicon using the second insulating film as a mask layer; And etching the second oxide film and the first polysilicon in order to form an upper portion of the capacitor storage electrode, (7) depositing the fourth polysilicon and dry etching the third polysilicon and the bit above the bit line Forming a side protrusion connection of the capacitor storage electrode connecting the first polysilicon below, and then removing the second insulating layer by wet etching to form a storage node electrode of the capacitor, (8) a capacitor on the storage node electrode surface of the capacitor And forming a plate electrode of a dielectric film and a capacitor. Preferably, the first and second insulating films are nitride films.

The present invention will be described below with reference to FIGS. 2, 3, and 4.

2 is a view schematically showing the layout of the present invention, (A) to (H) of FIG. 3 and (E) to (I) of FIG. 4 are cross-sectional views taken along line K-K 'of FIG. (A ')-(H') of FIG. 4, and (E ')-(I') of FIG. 4 are sectional drawing of the L-L 'line | wire of FIG.

First, the first embodiment of the present invention will be described.

As shown in FIGS. 2 and 3, after forming the active region 31 on which the element is formed and the field oxide film 32 as the element isolation region, the element is formed on the silicon (Si) substrate 30. The gate 33, the source and the drain 34 are formed to form a switching transistor.

Thereafter, the first oxide layer 35 is deposited and a buried contact 36 is formed.

Next, first polysilicon is referred to as doped polysilicon or amorphous silicon 37 (hereinafter referred to as polysilicon), as shown in FIGS. 2B and 3B. After depositing (37), the second oxide film 38 is deposited and the second oxide film and the first polysilicon film are patterned in a direction parallel to the L-L 'line direction (the direction perpendicular to the longitudinal direction of the active region). As a result, a portion of the capacitor storage electrode connected to the source region of the switching transistor is formed.

Thereafter, as shown in Figs. 2 and 3, (C) and (C '), the oxide film is deposited on the entire surface and etched back to form an oxide film sidewall 39 next to the patterned first polysilicon film. The line contact 40 is formed by a photolithography process.

Subsequently, as shown in FIGS. 2 and 3, (D) and (D '), the second polysilicon 41 is deposited, and only the proper thickness is etched back without the photoresist mask, and then the high melting point metal film 42 is removed. After positioning, the third oxide film 43 is deposited, and the bit line is patterned in parallel to the K-K 'line to expose a part of the second oxide film 38.

Thereafter, as shown in FIGS. 2 and 3 (E) and (E '), the fourth oxide film 44 is deposited and the fourth oxide film 44 and the second oxide film (in the direction parallel to the KK' direction). 38) is patterned by a photolithography process to expose a portion of the first polysilicon 37.

Thereafter, the third polysilicon 45 is deposited as shown in FIGS. 2 and 3 (F) and (F ').

After that, the third polysilicon film 45 and the first polysilicon film 37 are patterned by a photolithography process as shown in FIGS. 2 and 3 (G) and (G ′) to form tube-type capacitor storage. The electrode 5 is formed.

Subsequently, as shown in FIGS. 2 and 3, the capacitor dielectric film 6 and the plate electrode 7 are sequentially formed to form a capacitor of the memory cell.

In this way, since the active area is parallel or overlapped with respect to the bit line and vertically with respect to the word line, the unit cell does not have an inclination angle and has a straight structure. When patterning, no distortion occurs and the unit cell area can be reduced.

Next, a second embodiment, which is another embodiment of the present invention, will be described with reference to FIG.

First, the steps up to (D) and (D ') in FIG. 3 described in the first embodiment are performed as in the second embodiment.

Subsequently, as shown in FIG. 4E, the first nitride film 51 is deposited to protect the third oxide film 43 when the second oxide film is etched, and the bit lines 41 and 42 are formed. A portion of the second oxide film 38 is exposed by patterning the bit line so as to cover the bit line in parallel.

As shown in FIG. 4 (F) (F '), the third polysilicon 52 is deposited, the second nitride film 53 is deposited, and the second nitride film 53 is patterned by a photolithography process.

Thereafter, as shown in FIG. 4 (G) (G '), the third polysilicon 52, the second oxide film 38, and the first polysilicon 37 are sequentially patterned using the second nitride film 53 as a mask layer. do.

Subsequently, as shown in FIG. 4 (H) (H '), the fourth polysilicon 54 is deposited and the sidewall protrusion connection 8 of the capacitor storage electrode is formed by dry etching, followed by the second nitride film 53. Remove by wet etching.

At this time, the sidewall protruding portion serves to connect the third polysilicon of the upper layer of the bit line and the first polysilicon of the lower layer of the bit line, and increases the capacitance of the capacitor by widening the surface area of the storage electrode.

Subsequently, as shown in FIG. 4 (I) (I '), the capacitor dielectric film 55 and the capacitor plate electrode 56 are formed to complete the capacitor.

In the process performed in FIG. 4F, instead of the second nitride film 53, an insulating material having a large etching selectivity with respect to polysilicon may be used.

When the cells are configured in this way, since the active region is formed in parallel or overlapping directions with respect to the bit line and in the vertical direction with respect to the word line, there is no part having an inclination angle in the unit cell, and the structure has a straight structure. When patterning, distortion does not occur, and the unit cell area can be reduced, and the capacitor area can be increased without increasing the unit cell area.

Claims (7)

A semiconductor memory cell comprising: a gate, a source, and a drain formed in an active region of a semiconductor substrate, a first polysilicon connected to a source region of the active region and formed above the gate, and a first insulating layer formed on the first polysilicon. And a second polysilicon connected to the drain region of the active region and formed on the first insulating layer, a bit line formed of a high melting point metal formed on the second polysilicon, and a second insulating layer formed on the bit line. And a storage electrode formed on the second insulating layer and comprising a third polysilicon connected to the first polysilicon, wherein the storage electrode has a tube shape completely enclosing a bit line of a predetermined length. A semiconductor memory cell. The semiconductor memory cell of claim 1, wherein an arrangement direction of the gate, the source, and the drain and a vertical axis of the storage electrode are arranged in the same direction. The semiconductor memory cell of claim 1, wherein the active region is arranged in parallel or overlapping with respect to the bit line and at right angles with respect to a word line. A method of manufacturing a semiconductor memory cell, comprising the steps of: (1) forming a field oxide film as an active region and an isolation region on a silicon substrate, and then forming a switching transistor by forming a gate, a source, and a drain, (2 ) Deposition of the first oxide film and opening the buried contact by the exposure etching process, depositing the first polysilicon on the entire wafer, depositing the second oxide film, parallel to the direction perpendicular to the longitudinal direction of the active region Patterning the second oxide film and the first polysilicon film to form a portion of the capacitor storage electrode connected to the ososo of the switching transistor; (3) depositing and etching back the coral film to the front surface of the first poly; Forming an oxide sidewall next to the silicon film, (4) opening the bit line contacts by a photolithography process, depositing the second polysilicon and etching back only the appropriate thickness. Thereafter, a high melting point metal film is deposited thereon, and a third oxide film is deposited, and then a third oxide film, a high melting point metal film, and a second polysilicon are patterned in parallel to the longitudinal axis of the active region to form a bit line. (5) depositing the fourth oxide film, patterning the fourth oxide film and the second oxide film exposed to the surface in parallel with the longitudinal axis of the active region by photolithography, (6) depositing the third polysilicon and Patterning the third polysilicon film and the first polysilicon film by a photolithography process to form a capacitor storage electrode in the form of a tube, (7) coating a capacitor dielectric film on the surface of the capacitor storage electrode, and forming a plate electrode of the capacitor thereon A semiconductor memory cell manufacturing method comprising the step of. A method of manufacturing a semiconductor memory cell, comprising the steps of: (1) forming a field oxide film as an active region and an isolation region on a silicon substrate, and then forming a switching transistor by forming a gate, a source, and a drain, (2 ) Deposition of the first oxide film and opening the buried contact by the exposure etching process, depositing the first polysilicon on the entire wafer, depositing the second oxide film, parallel to the direction perpendicular to the longitudinal direction of the active region Patterning the second oxide film and the first polysilicon film to form a portion of the capacitor storage electrode connected to the source of the switching transistor; and (3) depositing the oxide film on the front surface and etching back to the side of the patterned first polysilicon film. Forming an oxide film sidewall at (4) opening the bit line contacts by a photolithography process, depositing the second polysilicon and etching back only the appropriate thickness Thereafter, a high melting point metal film is deposited thereon, and a third oxide film is deposited, and then a third oxide film, a high melting point metal film, and a second polysilicon are patterned in parallel to the longitudinal axis of the active region to form a bit line. (5) depositing a first insulating film made of an insulating material having high etch selectivity over the oxide film and polysilicon, patterning the first insulating film so as to cover the bit line in parallel with the bit line, and depositing the third polysilicon. Depositing a second insulating film made of an insulating material having high etch selectivity over the oxide film and polysilicon, and then patterning the second insulating film so as to cover the bit lines in parallel with the bit lines by a photolithography process, (6) forming the second insulating film. Etching the third polysilicon, the second oxide film, and the first polysilicon in order as a mask layer to form an upper portion of the capacitor storage electrode, (7) depositing the fourth polysilicon and non-driing by dry etching Forming a sidewall protrusion connection of the capacitor storage electrode connecting the third polysilicon above the upper wire and the first polysilicon below the bit line, and then removing the second insulating layer by wet etching to form the storage node electrode of the capacitor, (8 ) Forming a dielectric film of the capacitor and a plated electrode (56) of the capacitor on the surface of the storage node electrode of the capacitor. 6. The method of claim 5, wherein the first and second insulating films in the fifth step are nitride films. The semiconductor memory cell of claim 1, wherein the first polysilicon and the third polysilicon are connected to sidewall protrusions.