KR0124723Y1 - Read clock generating device for tbc circuit - Google Patents
Read clock generating device for tbc circuitInfo
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- KR0124723Y1 KR0124723Y1 KR2019920002711U KR920002711U KR0124723Y1 KR 0124723 Y1 KR0124723 Y1 KR 0124723Y1 KR 2019920002711 U KR2019920002711 U KR 2019920002711U KR 920002711 U KR920002711 U KR 920002711U KR 0124723 Y1 KR0124723 Y1 KR 0124723Y1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
- G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
- G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
- G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
- G11B27/3036—Time code signal
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Abstract
본 고안은 VCR에서 칼라 또는 휘도신호 처리시에 사용되는 TBC(Time Base Correction)회로에서 리드 클록(Read Clock)을 발생시키는 장치에 관한 것으로 종래의 TBC회로 리드클록 발생장치에 의하면 PLL회로가 요구되며, PLL회로에 의한 수평동기신호와 피이드백 신호의 동기가 어렵고, 이에따른 클록발생 동작의 신뢰성 저하가 초래되는 문제점을 해결하기 위한 것이다.The present invention relates to a device for generating a read clock in a TBC (Time Base Correction) circuit used in processing a color or luminance signal in a VCR. According to a conventional TBC circuit lead clock generator, a PLL circuit is required. In order to solve the problem, it is difficult to synchronize the horizontal synchronization signal and the feedback signal by the PLL circuit, and the reliability of the clock generation operation is consequently caused.
본 고안은 PLL회로의 사용을 배제하고 제어신호들에 동기된 리드클록을 발생시켜 공급하므로서 회로구성의 간소화 및 이를 통한 원가절감을 도모하고, 정확히 동기된 신호출력이 가능하여 기기 동작의 신뢰성 향상을 확보할 수 있도록 한 것으로 VCR, VDP등의 TBC회로에 적용한다.The present invention eliminates the use of the PLL circuit and generates and supplies a lead clock synchronized to the control signals, thereby simplifying the circuit configuration and reducing the cost, and accurately synchronizing the signal output, thereby improving the reliability of the operation of the device. Applied to TBC circuits such as VCR and VDP.
Description
제1도는 종래 TBC회로의 리드클록 발생장치 회로도.1 is a circuit diagram of a lead clock generator of a conventional TBC circuit.
제2도는 본 고안 TBC회로의 리드클록 발생장치 회로도.2 is a circuit diagram of a lead clock generator of a TBC circuit of the present invention.
제3도는 본 고안의 피일드신호 발생기 상세회로도.3 is a detailed circuit diagram of a feed signal generator of the present invention.
제4도는 본 고안의 동기신호 발생기 상세회로도.4 is a detailed circuit diagram of a synchronization signal generator of the present invention.
제5도는 본 고안의 블랭킹신호 발생기 상세회로도.5 is a detailed circuit diagram of a blanking signal generator of the present invention.
제6도는 본 고안의 빈트신호 발생기 상세회로도.6 is a detailed circuit diagram of the vint signal generator of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
7 : 피일드신호 발생기 8 : 동기신호 발생기7: Feed signal generator 8: Synchronization signal generator
9 : 블랭킹신호 발생기 10 : 빈트발생기9: Blanking Signal Generator 10: Vint Generator
본 고안은 VCR에서 칼라 또는 휘도신호 처리시에 사용되는 TBC(Time Base Correction)회로에서 리드 클록(Read Clock)을 발생시키는 장치에 관한 것이다.The present invention relates to an apparatus for generating a read clock in a time base correction (TBC) circuit used in processing a color or luminance signal in a VCR.
종래 TBC회로의 리드클록 발생장치는 제1도를 참조하면, 수평동기신호(H.Sync)를 출력하는 동기신호 발생기(1)와, 수평동기신호 및 PLL회로(6)에서 피이드백된 신호로 부터 10MHz클록, 빈트신호(VINT), 피일드신호(Field)등의 제반 제어신호들을 출력하는 제어신호 발생기(2)와, 제어신호 발생기(2)의 수직블랭킹신호(VBLK)및 동기신호 발생기(1)의 수평동기신호(H.Sync)를 위상 비교하는 위상비교기(3)와, 위상비교신호의 필터링을 행하는 루프필터(4)와, 필터링된 신호를 제어전압으로 하여 발진주파수가 가변 출력되는 전압제어 발진기(5)로 구성되며, 상기 위상비교기(3)와 루프필터(4)및 전압제어 발진기(5)는 PLL회로(6)를 구성한다.A lead clock generator of a conventional TBC circuit is referred to as a synchronization signal generator 1 for outputting a horizontal synchronization signal (H.Sync), and a feedback signal from the horizontal synchronization signal and the PLL circuit (6). Control signal generator 2 for outputting various control signals such as a 10 MHz clock, a Vint signal, a field signal, a vertical blanking signal VBLK, and a synchronization signal generator of the control signal generator 2. A phase comparator 3 for comparing the phase synchronization signal H.Sync of 1), a loop filter 4 for filtering the phase comparison signal, and an oscillation frequency are variablely output using the filtered signal as a control voltage. It consists of a voltage controlled oscillator (5), and the phase comparator (3), the loop filter (4) and the voltage controlled oscillator (5) constitute a PLL circuit (6).
이와같이 구성된 종래 TBC회로의 리드클록 발생장치의 동작을 설명하면, 제1도에서와 같이 동기신호 발생기(1)에서 910fH 발진기 출력을 입력받아 수평동기신호(H.Sync)를 출력하고, 이 수평동기신호(H.Sync)는 제어신호 발생기(2)와 위상비교기(3)에 입력된다.Referring to the operation of the lead clock generator of the conventional TBC circuit configured as described above, as shown in FIG. 1, the synchronous signal generator 1 receives the 910fH oscillator output and outputs a horizontal synchronous signal (H.Sync). The signal H.Sync is input to the control signal generator 2 and the phase comparator 3.
제어신호 발생기(2)는 수직 블랭킹신호(VBLK) (피이드백, 하이(H)신호)를 출력하여 위상비교기(3)에 공급하고, 위상비교기(3)는 입력된 두신호(VBLK)(H.Sync)의 위상을 비교하여 비교결과를 루프필터(4)에 공급한다.The control signal generator 2 outputs the vertical blanking signal VBLK (feedback, high (H) signal) and supplies it to the phase comparator 3, and the phase comparator 3 receives the two input signals VBLK (H). .Sync) phase is compared and the comparison result is supplied to the loop filter 4.
루프필터(4)에서 필터링되어 출력된 신호는 전압제어 발진기(5)에 제어전압으로 인가되고 이에 따라 전압제어 발진기(5)에서 출력되는 신호의 주파수가 제어되며, 이와같이 출력된 20MHz신호는 다시 제어신호 발생기(2)로 피이드백된다.The signal filtered and output from the loop filter 4 is applied to the voltage controlled oscillator 5 as a control voltage, and accordingly, the frequency of the signal output from the voltage controlled oscillator 5 is controlled, and the output 20 MHz signal is controlled again. It is fed back to the signal generator 2.
즉, PLL회로(6)에서 출력되는 20MHz와 동기신호 발생기(1)의 수평동기신호(H.Sync)를 동기시켜서 제어신호 발생기(2)에서 신호처리에 요구되는 제반 제어신호(10MHz, VINT, Field)들을 출력시키게 된다.That is, by synchronizing the 20 MHz output from the PLL circuit 6 with the horizontal synchronization signal H.Sync of the synchronization signal generator 1, the control signal generator 2 controls all the control signals (10 MHz, VINT, Fields will be printed.
그러나 상기와 같은 종래의 TBC회로 리드클록 발생장치에 의하면 PLL회로가 요구되며, PLL회로에 의한 수평동기신호와 피이드백 신호의 동기가 어렵고, 이에따른 클록발생 동작의 신뢰성 저하가 초래되는 문제점이 있었다.However, according to the conventional TBC circuit lead clock generator as described above, a PLL circuit is required, and it is difficult to synchronize a horizontal synchronization signal and a feedback signal by the PLL circuit, resulting in a problem of deterioration in reliability of a clock generation operation. .
본 고안은 PLL회로의 사용을 배제하고 제어신호들에 동기된 리드클록을 발생시켜 공급하므로서 회로구성의 간소화 및 이를 통한 원가절감을 도모하고, 정확히 동기된 신호출력이 가능하여 기기동작의 신뢰성 향상을 확보할 수 있도록 한 TBC회로의 리드클록 발생장치를 제공함을 목적으로 하며, 제2도를 참조하여 본 고안의 구성부터 설명하면 다음과 같다.The present invention eliminates the use of the PLL circuit and generates and supplies a read clock synchronized with the control signals, thereby simplifying the circuit configuration and reducing the cost, and accurately synchronizing the signal output, thereby improving the reliability of the operation of the device. It is an object of the present invention to provide a lead clock generator of a TBC circuit, which can be ensured. Referring to FIG.
즉, 제2도를 참조하면 본 고안의 TBC회로의 리드클록 발생장치는 클록(CLK)을 계수하여 피일드 신호(field)를 출력하는 피일드신호 발생기(7)와, 클록(CLK)을 계수하여 수평동기신호(H.Sync)를 출력하는 동기신호 발생기(8)와, 상기 피일드신호(field)및 수평동기신호(H.Sync)를 입력받아 수직 블랭킹신호(VBLK)와 스위프 블랭킹신호(SBLK)를 발생시키는 블랭킹신호 발생기(9)와, 상기 피일드신호(field)및 스위프 블랭킹신호(SBLK)를 입력받아 빈트신호(VINT)를 발생시키는 빈트발생기(10)로 구성되며, 그 동작은 다음과 같다.That is, referring to FIG. 2, the lead clock generator of the TBC circuit of the present invention counts the clock signal generator 7 which outputs the field signal by counting the clock CLK, and counts the clock CLK. A synchronization signal generator 8 that outputs a horizontal synchronization signal H.Sync, the feed signal field and the horizontal synchronization signal H.Sync, and receive a vertical blanking signal VBLK and a sweep blanking signal And a blanking signal generator 9 for generating SBLK, and a vint generator 10 for receiving the feed signal field and the sweep blanking signal SBLK and generating a blank signal VINT. As follows.
즉, 제2도에서 피일드신호 발생기(7)는 클록(CLK)(20MHz)을 입력받은후 영상신호의 1피일드 기간동안은 로우신호를 출력하고 다른 1피일드 기간동안은 하이를 출력하여 짝수 피일드와 홀수 피일드를 나타내는 피일드신호(field)를 출력한다.That is, in FIG. 2, the feed signal generator 7 receives the clock CLK (20 MHz) and outputs a low signal during one feed period of the video signal, and outputs a high one during the other one feed period. A feed signal (field) indicating even and odd feeds is output.
즉, 제3도에 도시된 피일드신호 발생기(7)에서와 같이 입력단(IN)에 공급된 클록(CLK)은 카운터(7A)(7B)(7C)에서 카운트되고 카운트 출력은 인버터부(7D)(7E)(7F)를 통해 반전되어 앤드게이트부(7I)(7J)(7K)에 인가되며, 앤드게이트부(7I)(7J)(7K)의 출력신호는 낸드게이트부(7L)와 앤드게이트부(7M)를 통해 낸드게이트(7N)에 공급되어 그 출력된(OUT)에서는 영상신호의 홀수 피일드와 짝수 피일드에 각각 대응하는 피일드신호(field)가 출력된다.That is, as in the feed signal generator 7 shown in FIG. 3, the clock CLK supplied to the input terminal IN is counted in the counters 7A, 7B and 7C and the count output is the inverter section 7D. (7E) and 7F are inverted and applied to the AND gate portions 7I, 7J, and 7K, and the output signals of the AND gate portions 7I, 7J, and 7K are coupled to the NAND gate portion 7L. The NAND gate 7N is supplied to the NAND gate 7N through the AND gate portion 7M, and at the output OUT, a feed signal field corresponding to the odd and even feeds of the video signal is output.
이와같이 출력된 피일드신호(field)는 제2도에서와 같이 블랭킹신호 발생기(9)와 빈트 발생기(10)에 입력된다.The output signal field thus output is input to the blanking signal generator 9 and the vint generator 10 as shown in FIG.
한편, 동기신호 발생기(8)는 클록(CLK)을 입력받아 수평동기신호(H.Sync)와 10MHz신호를 발생시켜 출력한다.On the other hand, the synchronization signal generator 8 receives the clock CLK and generates and outputs a horizontal synchronization signal H.Sync and a 10 MHz signal.
즉, 제4도에 도시된 동기신호 발생기(8)에서와 같이 입력단(IN)에 공급된 클록(CLK)은 카운터(8A)(8B)(8C)에서 카운트되고 카운트 출력은 인버터부(8D)를 통해 반전되어 앤드게이트부(8E)에 인가되며, 앤드게이트부(8E)의 출력신호는 노아게이트(8F)에 공급되어 그 출력단(OUT)에서는 63.5μsec 주기의 수평동기신호(H.Sync)가 출력된다.That is, as in the synchronization signal generator 8 shown in FIG. 4, the clock CLK supplied to the input terminal IN is counted in the counters 8A, 8B, 8C, and the count output is the inverter section 8D. It is inverted through and applied to the AND gate portion 8E, and the output signal of the AND gate portion 8E is supplied to the NOA gate 8F, and at the output terminal OUT, a horizontal synchronization signal (H.Sync) of 63.5 μsec period is performed. Is output.
그리고 입력단(IN)에 공급된 클록(CLK)은 D플립플롭(8G)를 통과시켜 그 출력단(OUT2)에서는 20MHz클록을 10MHz클록으로 출력하게 되며, 또한 카운터(8H)의 카운트 결과는 D플립플롭(8G)에 클록으로 공급된다.The clock CLK supplied to the input terminal IN passes through the D flip-flop 8G. The output terminal OUT2 outputs a 20 MHz clock as a 10 MHz clock, and the count result of the counter 8H is a D flip flop. It is supplied as a clock at 8G.
이와같이 출력된 수평동기신호(H.Sync)는 제2도에서와 같이 블랭킹신호 발생기(9)에 공급되고, 블랭킹신호 발생기(9)는 입력된 피일드신호(field)와 수평동기신호(H.Sync)로 부터 홀수 및 짝수 피일드에 따라 9H의 수직 블랭킹신호(VBLK)와 스위프(SWEEP) 블랭킹신호(SBLK)를 발생시킨다.The horizontal synchronous signal H.Sync thus output is supplied to the blanking signal generator 9 as shown in FIG. 2, and the blanking signal generator 9 receives the input feed signal field and the horizontal synchronous signal H. Sync) generates vertical blanking signals VBLK and SWEEP blanking signals SBLK of 9H according to odd and even feeds.
즉, 제5도에 도시된 블랭킹신호 발생기(9)에서와 같이 피일드신호(field)를 입력으로 하고 수평동기신호(H.Sync)를 클록으로하여 D플립플롭(9A)의 출력신호가 노아게이트(9B)와 오아게이트(9C)를 통해 카운터(9D)(9E)(9F)에 공급되고, 카운터(9D)(9E)(9F)의 출력은 인버터부(9G)와 앤드게이트부(9H)를 통해 출력 게이트부(9I)에 공급되어 그 출력단(OUT1)에서는 9H의 수직블랭킹신호(VBLK)가 출력되고 출력단(OUT2)에서는 스위프 블랭킹신호(SBLK)가 출력된다.That is, as in the blanking signal generator 9 shown in FIG. 5, the output signal of the D flip-flop 9A is noahed with the feed signal field as the input and the horizontal synchronization signal H.Sync as the clock. The counters 9D, 9E, and 9F are supplied to the counters 9D, 9E, and 9F through the gate 9B and the oragate 9C, and the outputs of the counters 9D, 9E, and 9F are the inverter section 9G and the end gate section 9H. The vertical blanking signal VBLK of 9H is output from the output terminal OUT1, and the swept blanking signal SBLK is output from the output terminal OUT2.
이와같이 출력된 스위프 블랭킹신호(SBLK)는 제2도에서와 같이 빈트발생기(10)에 공급되고, 빈트발생기(10)는 피일드신호(field)와 스위프 블랭킹신호(SBLK)로부터 빈트신호(VINT)를 발생시켜 출력한다.The swept blanking signal SBLK output in this manner is supplied to the vint generator 10 as shown in FIG. 2, and the vint generator 10 is a Vint signal VINT from the field signal and the swept blanking signal SBLK. Generate and print
즉, 제6도에 도시된 빈트발생기(10)에서와 같이 피일드신호(field)와 스위프 블랭킹신호(SBLK)는 오아게이트(10A)로 논리합되어 카운터(10B)에 로드되고 각 카운터(10B)(10C)(10D)에서 카운트된 최종 결과가 D플립플롭(10F)을 통해 빈트신호(VINT)로서 출력된다.That is, as in the vint generator 10 shown in FIG. 6, the feed signal field and the swept blanking signal SBLK are logically summed into the oragate 10A, loaded into the counter 10B, and each counter 10B. The final result counted at (10C) (10D) is output as the vint signal VINT via the D flip-flop 10F.
이상에서 설명한 바와같이 본 고안에 의하면 20MHz클록을 이용하여 제어신호 발생이 가능하므로 PLL회로가 배제되고 따라서 회로구성의 간소화 및 원가절감과 이를 통한 생산성 향상을 도모할 수 있는 효과가 있다.As described above, according to the present invention, since a control signal can be generated using a 20 MHz clock, the PLL circuit is excluded, thereby simplifying the circuit configuration, reducing the cost, and improving productivity.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019920002711U KR0124723Y1 (en) | 1992-02-24 | 1992-02-24 | Read clock generating device for tbc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019920002711U KR0124723Y1 (en) | 1992-02-24 | 1992-02-24 | Read clock generating device for tbc circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930020350U KR930020350U (en) | 1993-09-24 |
| KR0124723Y1 true KR0124723Y1 (en) | 1998-10-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019920002711U KR0124723Y1 (en) | 1992-02-24 | 1992-02-24 | Read clock generating device for tbc circuit |
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| Country | Link |
|---|---|
| KR (1) | KR0124723Y1 (en) |
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1992
- 1992-02-24 KR KR2019920002711U patent/KR0124723Y1/en not_active IP Right Cessation
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| KR930020350U (en) | 1993-09-24 |
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