KR0124548Y1 - Lead frame - Google Patents
Lead frameInfo
- Publication number
- KR0124548Y1 KR0124548Y1 KR92018103U KR920018103U KR0124548Y1 KR 0124548 Y1 KR0124548 Y1 KR 0124548Y1 KR 92018103 U KR92018103 U KR 92018103U KR 920018103 U KR920018103 U KR 920018103U KR 0124548 Y1 KR0124548 Y1 KR 0124548Y1
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- inner lead
- chip
- lead frame
- adhesive
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본고안은 리드프레임으로, 내부리드의 칩접착부위에 수개의 구멍을 형성시킨 것이며, 칩에 접착재를 기재시켜 접착시에 구멍을 통하여 습기나 보이드가 배출되게 하므로 내부리드의 오픈현상이 제거되고, 구멍을 통하여 3차원적으로 접착되어 접착력이 증대된다.This is a lead frame, which is formed of several holes in the chip bonding part of the inner lead, and the adhesive material is written on the chip so that moisture or voids are discharged through the hole at the time of bonding, so that the open phenomenon of the inner lead is eliminated, Adhesion is increased by three-dimensional bonding through the hole.
Description
제1도는 종래 리드프레임의 사용상태 단면도.1 is a cross-sectional view of a state of use of a conventional lead frame.
제2도(a),(b)는 종래 리드프레임의 내부리드 단면 사시도.Figure 2 (a), (b) is a cross-sectional perspective view of the inner lead of the conventional lead frame.
제3도(a)~(c)는 종래의 리드프레임에 접착테이프가 가열 접착되는 상태 설명도.3 (a) to 3 (c) are explanatory diagrams in which the adhesive tape is heat-bonded to a conventional lead frame.
제4도는 본고안의 리드프레임의 내부리드 확대 평면도.4 is an enlarged plan view of the inner lead of the lead frame in the present article.
제5도는 본고안의 사용상태 단면도이다.5 is a cross-sectional view of the state of use of the present article.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 내부리드 11 : 접착부위1: inside lead 11: adhesive site
12 : 구멍 14 : 와이어본딩부위12: hole 14: wire bonding portion
본고안은 리드프레임에 관한 것으로, 특히 내부리드의 접착부위에 구멍을 뚫어 칩의 접착에 따른 보이드 생성등을 없애도록 한것이다.This paper is related to the lead frame, in particular, to remove the voids caused by the bonding of the chip by drilling holes in the bonding portion of the inner lead.
일반적으로 리드프레임은 내부리드와 칩사이에 접착테이프를 가열한 다음 접착테이프를 경화시킴으로써 내부리드에 칩을 어태치한다.Generally, the lead frame attaches the chip to the inner lead by heating the adhesive tape between the inner lead and the chip and then curing the adhesive tape.
이는 제1도와 같이 도시할수 있는바 리드프레임의 내부리드(1)와 칩(2) 사이에 접착테이프(3)를 개재시킨다. 접착테이프(3)는 내부리드(1)와 접착되는 제1접착층(3-1)과, 칩(2)과 접착되는 제2접착층(3-2)과, 상기 제1 및 제2접착층(3-1, 3-2) 사이에서 절연시키는 절열층(3-3)으로 이루어진다. 내부리드(1)와 칩(2)간을 접착테이프(3)로 접착한 다음에는 와이어(4)로 와이어본딩시킨다.As shown in FIG. 1, the adhesive tape 3 is interposed between the inner lead 1 and the chip 2 of the lead frame. The adhesive tape 3 includes a first adhesive layer 3-1 bonded to the inner lead 1, a second adhesive layer 3-2 adhered to the chip 2, and the first and second adhesive layers 3. It consists of a heat insulation layer 3-3 which insulates between -1 and 3-2. After bonding the inner lead 1 and the chip 2 with the adhesive tape 3, wire bonding is performed with the wire 4.
이경우 내부리드(1)의 구조는 제2도(a)와 같은 평면형(ETCHED LEAD FRAME)과 제2도(b)와 같은 캡형(STAMP LEAD FRAME)으로 구분할수 있다. 이경우 평면형은 양측면에 에칭면(1-1)이 만들어진 상태로 되어있어, 접착테이프(3)의 제1접착층(3-1)의 일부가 에칭면(1-1)으로 올라와서 내부리드(1)와 칩(2)간의 접착력을 증대시켜준다. 그러나 측면에 에칭면(1-1)을 만들어야 하므로 원가상승의 요인이 된다. 또한 캡형은 제조가격이 저렴하나 제2도(b)와 같이 제조시에 하부양측면에 버(BURR)(1-2)가 생성되어 접착테이프(3)로 칩(2)을 접착시에 보이드(Void)등이 성장되므로 리드틸트(LEAD TILT) 및 리드오픈(LEAD OPEN)의 원인이 되어 생산성이 감소된다. 즉, 제3도와 같이 리드(1)와 칩(2)에 접착테이프(3)를 위치시키면, 제1접착층(3-1) 자체의 특성이 흡습성이 좋고 내부리드(1)의 버(1-2)에 의한 공간으로 인하여, 가열접착시 보이드(Void) 또는 습기(1-4)가 빠져나오지 못하고 제3도(b) 및 (c)와 같이 점차 팽창되어 내부리드(1)와 제1접착층(3-1) 사이에 갇히게 된다.In this case, the structure of the inner lead 1 may be classified into a flat type (ETCHED LEAD FRAME) as shown in FIG. 2 (a) and a cap type (STAMP LEAD FRAME) as shown in FIG. In this case, the planar surface is in a state where etching surfaces 1-1 are formed on both sides, and a part of the first adhesive layer 3-1 of the adhesive tape 3 rises up to the etching surface 1-1 so that the inner lead 1 is formed. ) And the adhesion between the chip (2). However, since the etching surface (1-1) must be formed on the side surface, it becomes a factor of cost increase. In addition, the cap type has a low manufacturing price, but as shown in FIG. 2 (b), burrs 1-2 are formed on both sides of the lower part at the time of manufacture so that the voids when bonding the chip 2 with the adhesive tape 3 Void) grows, which leads to lead tilt and lead open, which reduces productivity. That is, when the adhesive tape 3 is placed on the lid 1 and the chip 2 as shown in FIG. 3, the characteristics of the first adhesive layer 3-1 itself are hygroscopic and the burrs 1-1 of the inner lead 1 are disposed. Due to the space by 2), the voids or moisture (1-4) do not escape during heat bonding and gradually expand as shown in FIGS. 3 (b) and (c), so that the inner lead 1 and the first adhesive layer You are trapped between (3-1).
즉, 갇힌 보이드 또는 습기(1-4)는 히팅되면서 큰 덩어리로 성장하는바, 이 현상은 구조의 특성상 제2도(a)의 평면형보다는 제2도(b)의 캡형 리드(1)에 더 심하게 나타난다. 이렇게 확장성장된 보이드 또는 습기는 내부리드(1)에 휨 현상을 유발하고, 경우에 따라서는 리드오픈(LEAD OPEN)의 원인으로 되어, 다음 공정인 와이어 본딩공정에서 내부리드(1)에 와이어(4)를 와이어본딩이 제대로 되지 않게 하여 생산성 감소 및 불량의 주원인이 되는 단점이 있다.That is, the trapped voids or moisture (1-4) grows into a large mass while heating, this phenomenon is more in the cap-shaped lead (1) of FIG. 2 (b) than the planar form of FIG. Appears badly. The expansion or growth of voids or moisture causes warpage in the inner lead 1, and in some cases, leads to a lead open (LEAD OPEN). 4) There is a disadvantage in that wire bonding is not properly made, leading to a decrease in productivity and a defect.
본고안은 이를 해결코자 하는 것으로, 내부리드에 구멍을 형성하여 보이드나 습기를 배출시키도록 함을 특징으로 한다. 즉, 칩을 접착제로 접착시키는 내부리드를 포함하는 리드프레임에서, 내부리드의 접착부위에 수개의 구멍을 형성한 것이다.The present invention is to solve this problem, it is characterized in that to form a hole in the inner lead to discharge the void or moisture. That is, in the lead frame including the inner lead for adhering the chip with an adhesive, several holes are formed in the bonding portion of the inner lead.
이하 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the drawings as follows.
본고안은 칩을 접착제로 접착시키는 내부리드를 포함하는 리드프레임을 구성함에 있어서, 내부리드(1)의 접착부위(11)에 수개의 구멍(12)이 관통형성된 것이다. 따라서 내부리드(1)의 접착부위(11)와 칩(2) 사이에 접착테이프(3)를 위치시키고, 가열시키면 제5도와 같이 구멍(12)으로 보이드나 습기가 배출되므로 보이드나 습기에 의한 접착에러가 없게 되고, 동시에 구멍(12)으로 제1접착층(3-1)의 일부가 스며들어 리드(1)와의 접촉면적이 증대되므로 그만큼 접착력을 증대시킨다.In the present proposal, in constructing a lead frame including an inner lead for adhering the chip with an adhesive, several holes 12 are penetrated through the bonding portion 11 of the inner lead 1. Therefore, when the adhesive tape 3 is placed between the adhesive part 11 and the chip 2 of the inner lead 1 and heated, voids or moisture are discharged into the holes 12 as shown in FIG. There is no adhesion error, and at the same time, a part of the first adhesive layer 3-1 penetrates into the hole 12, and the contact area with the lead 1 is increased, thereby increasing the adhesive force.
또한 와이어본딩시 열이 가해질 경우에도 보이드나 습기가 없으므로 내부리드의 오픈현상이 발생하지 않게된다. 본고안에서의 구멍(12)수나 크기등을 필요에 따라 조절사용 가능함은 물론이다. 또한 구멍(12)의 위치는 접착부위(11)에서 와이어본딩부위(14)를 제외하고 형성하여야 와이어본딩이 용이하다.In addition, even when heat is applied during wire bonding, there is no void or moisture, so the open phenomenon of the inner lead does not occur. Of course, the number and size of the holes 12 can be adjusted and used as necessary. In addition, the position of the hole 12 should be formed except for the wire bonding portion 14 in the adhesive portion 11 to facilitate the wire bonding.
이상과 같이 본고안은 LOC(LEAD ON CHIP)용 패키지등의 제작시 내부리드의 오픈현상 및 경사(Tilt)현상을 제거하여 와이어본딩 불량을 제거한다. 즉, 내부리드의 위치가 달라지지 않아 와이어본딩이 용이하다. 또한 보이드 및 습기가 제거되므로 신뢰성이 향상된다. 즉, 패키지 내부에 잔존하는 보이드 및 습기는 압력쿠커시험(PRESSURE COOKER TEST) 및 온도사이클에서 온도가 상승과 하강을 반보가는 동안 팽창과 압축이 되어 패키지 크랙(PACKAGE CRACK) 및 칩크랙(CHIP CRACK)의 직접적인 원인이 제거되어 제품의 신뢰성이 향상된다.As mentioned above, this paper eliminates the open phenomenon and tilt phenomenon of the inner lead when manufacturing the package for the lead on chip (LOC) to remove the wire bonding defect. That is, since the position of the inner lead does not change, wire bonding is easy. In addition, voids and moisture are removed to improve reliability. That is, the voids and moisture remaining inside the package are expanded and compressed during the pressure cooker test and temperature cycles as the temperature rises and falls, resulting in package cracks and chip cracks. The direct cause of the removal is eliminated, improving the reliability of the product.
또한 와이어본딩시 접착력 저하에 의한 내부리드팁 오픈현상이 줄어든다. 즉, 접착이 완료된 내부리드도 와이어본딩시 열이 가해져서 접착력의 저하로 인한 내부리드의 오픈현상이 발생하려고 하여도, 구멍에서 제1접착층의 일부가 위치되므로 접착력의 저하로 인한 리드팁 오픈현상을 구멍에서 충격을 흡수하여 주고, 구멍의 벽면을 통해 3차원적으로 접착시켜 주므로써 접착력이 증대된다.In addition, the internal lead tip opening phenomenon due to the adhesive strength decreases during wire bonding. In other words, even when the inner lead is bonded, heat is applied during wire bonding, and even though the inner lead is opened due to a decrease in the adhesive force, a part of the first adhesive layer is positioned in the hole, so that the lead tip is opened due to the lowered adhesive force. The adhesive force is increased by absorbing the impact from the hole and attaching it three-dimensionally through the wall of the hole.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92018103U KR0124548Y1 (en) | 1992-09-23 | 1992-09-23 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92018103U KR0124548Y1 (en) | 1992-09-23 | 1992-09-23 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940008684U KR940008684U (en) | 1994-04-21 |
| KR0124548Y1 true KR0124548Y1 (en) | 1998-10-01 |
Family
ID=19340529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92018103U KR0124548Y1 (en) | 1992-09-23 | 1992-09-23 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0124548Y1 (en) |
-
1992
- 1992-09-23 KR KR92018103U patent/KR0124548Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940008684U (en) | 1994-04-21 |
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