JPWO2024171697A1 - - Google Patents
Info
- Publication number
- JPWO2024171697A1 JPWO2024171697A1 JP2025500729A JP2025500729A JPWO2024171697A1 JP WO2024171697 A1 JPWO2024171697 A1 JP WO2024171697A1 JP 2025500729 A JP2025500729 A JP 2025500729A JP 2025500729 A JP2025500729 A JP 2025500729A JP WO2024171697 A1 JPWO2024171697 A1 JP WO2024171697A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023023321 | 2023-02-17 | ||
| PCT/JP2024/001086 WO2024171697A1 (ja) | 2023-02-17 | 2024-01-17 | 半導体パッケージ基板 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPWO2024171697A1 true JPWO2024171697A1 (https=) | 2024-08-22 |
Family
ID=92421518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025500729A Pending JPWO2024171697A1 (https=) | 2023-02-17 | 2024-01-17 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPWO2024171697A1 (https=) |
| WO (1) | WO2024171697A1 (https=) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11186677A (ja) * | 1997-12-25 | 1999-07-09 | Shin Etsu Polymer Co Ltd | プリント配線板用積層板 |
| JP2001185848A (ja) * | 1999-12-22 | 2001-07-06 | Sony Corp | 多層回路基板およびその製造方法 |
| JP3819701B2 (ja) * | 2000-11-10 | 2006-09-13 | 三菱樹脂株式会社 | ビルドアップ多層プリント配線基板用コア基板 |
| JP2002353580A (ja) * | 2001-05-23 | 2002-12-06 | Matsushita Electric Ind Co Ltd | 回路基板用絶縁材，回路基板およびその製造方法 |
| JP4030285B2 (ja) * | 2001-10-10 | 2008-01-09 | 株式会社トクヤマ | 基板及びその製造方法 |
| JP2012049423A (ja) * | 2010-08-30 | 2012-03-08 | Sumitomo Bakelite Co Ltd | 回路基板、半導体装置、回路基板の製造方法および半導体装置の製造方法 |
| JP2018120918A (ja) * | 2017-01-24 | 2018-08-02 | 日本特殊陶業株式会社 | セラミックパッケージ、電子部品装置、及びセラミックパッケージの製造方法 |
| WO2020188923A1 (ja) * | 2019-03-15 | 2020-09-24 | 京セラ株式会社 | 配線基板およびその製造方法 |
-
2024
- 2024-01-17 JP JP2025500729A patent/JPWO2024171697A1/ja active Pending
- 2024-01-17 WO PCT/JP2024/001086 patent/WO2024171697A1/ja not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024171697A1 (ja) | 2024-08-22 |