JPWO2022170661A5 - - Google Patents
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- JPWO2022170661A5 JPWO2022170661A5 JP2022566225A JP2022566225A JPWO2022170661A5 JP WO2022170661 A5 JPWO2022170661 A5 JP WO2022170661A5 JP 2022566225 A JP2022566225 A JP 2022566225A JP 2022566225 A JP2022566225 A JP 2022566225A JP WO2022170661 A5 JPWO2022170661 A5 JP WO2022170661A5
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- 239000000758 substrate Substances 0.000 claims 43
- 239000004065 semiconductor Substances 0.000 claims 30
- 239000003990 capacitor Substances 0.000 claims 12
- 239000000463 material Substances 0.000 claims 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 230000006870 function Effects 0.000 claims 1
- 230000001105 regulatory effect Effects 0.000 claims 1
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Claims (21)
前記複数のサブ画素は、前記サブストレートに設けられ、複数行及び複数列に配列され、前記複数のサブ画素のうちの少なくとも１つは、画素回路を含み、各前記画素回路は、駆動回路、電圧調整回路、駆動リセット回路及び発光リセット回路を含み、
前記駆動回路は、制御端、第１の端及び第２の端を含み、発光素子に駆動電流を提供するように構成され、
前記電圧調整回路は、前記駆動回路の前記制御端、第１のノード及び電圧調整制御信号入力端に結合され、前記電圧調整制御信号入力端からの電圧調整制御信号の制御で前記駆動回路の前記制御端を前記第１のノードと導通させるように構成され、
前記駆動リセット回路は、駆動リセット制御信号入力端、前記第１のノード及び駆動リセット電圧端に結合され、前記駆動リセット制御信号入力端からの駆動リセット制御信号の制御で駆動リセット電圧端からの前記駆動リセット電圧を前記電圧調整回路に提供して、前記駆動回路の前記制御端をリセットするように構成され、
前記発光リセット回路は、発光リセット制御信号入力端、発光素子及び発光リセット電圧端に結合され、前記発光リセット制御信号入力端からの発光リセット制御信号の制御で前記発光リセット電圧端からの発光リセット電圧を前記発光素子に提供して前記発光素子をリセットするように構成され、
前記駆動リセット電圧線は、前記駆動リセット電圧端に結合され、前記駆動リセット電圧端に前記駆動リセット電圧を提供するように構成され、
前記発光リセット電圧線は、前記発光リセット電圧端に結合され、前記発光リセット電圧端に前記発光リセット電圧を提供するように構成される
ことを特徴とするアレイ基板。 An array substrate including a substrate, a plurality of sub-pixels, a driving reset voltage line, and a light emission reset voltage line,
the plurality of sub-pixels are provided on the substrate and are arranged in a plurality of rows and a plurality of columns, at least one of the plurality of sub-pixels includes a pixel circuit, each of the pixel circuits includes a driving circuit, a voltage adjusting circuit, a driving reset circuit, and a light emission reset circuit;
The driving circuit includes a control end, a first end and a second end, and is configured to provide a driving current to the light-emitting element;
the voltage adjustment circuit is coupled to the control end, a first node, and a voltage adjustment control signal input end of the drive circuit, and is configured to conduct the control end of the drive circuit with the first node under control of a voltage adjustment control signal from the voltage adjustment control signal input end;
the driving reset circuit is coupled to a driving reset control signal input terminal, the first node and a driving reset voltage terminal, and is configured to provide the driving reset voltage from a driving reset voltage terminal to the voltage adjustment circuit under control of a driving reset control signal from the driving reset control signal input terminal to reset the control terminal of the driving circuit;
The light emission reset circuit is coupled to a light emission reset control signal input terminal, a light emitting device, and a light emission reset voltage terminal, and is configured to provide a light emission reset voltage from the light emission reset voltage terminal to the light emitting device under control of a light emission reset control signal from the light emission reset control signal input terminal to reset the light emitting device;
the driving reset voltage line is coupled to the driving reset voltage end and configured to provide the driving reset voltage to the driving reset voltage end;
The light emitting reset voltage line is coupled to the light emitting reset voltage terminal and configured to provide the light emitting reset voltage to the light emitting reset voltage terminal.
前記駆動トランジスタの第１の極が前記駆動回路の前記第１の端に結合され、前記駆動トランジスタのゲートが前記駆動回路の前記制御端に結合され、前記駆動トランジスタの第２の極が前記駆動回路の前記第１の端に結合され、
前記電圧調整トランジスタの第１の極が前記駆動回路の前記制御端に結合され、前記電圧調整トランジスタの第２の極が前記第１のノードに結合され、前記電圧調整トランジスタのゲートが前記電圧調整制御信号入力端に結合され、
前記駆動リセットトランジスタの第１の極が前記駆動リセット電圧端に結合され、前記駆動リセットトランジスタのゲートが前記駆動リセット制御信号入力端に結合され、前記駆動リセットトランジスタの第２の極が前記第１のノードに結合され、
前記発光リセットトランジスタの第１の極が前記発光リセット電圧端に結合され、前記発光リセットトランジスタのゲートが前記発光リセット制御信号入力端に結合され、前記発光リセットトランジスタの第２の極が前記発光素子の第１の端に結合され、
前記電圧調整トランジスタの活性層は、酸化物半導体材料を含み、前記駆動トランジスタと前記駆動リセットトランジスタの活性層とは、シリコン半導体材料を含む
ことを特徴とする請求項１に記載のアレイ基板。 The drive circuit includes a drive transistor, the voltage regulation circuit includes a voltage regulation transistor, the drive reset circuit includes a drive reset transistor, and the light emission reset circuit includes a light emission reset transistor,
A first pole of the drive transistor is coupled to the first end of the drive circuit, a gate of the drive transistor is coupled to the control end of the drive circuit, and a second pole of the drive transistor is coupled to the first end of the drive circuit. coupled to the first end of the circuit;
A first pole of the voltage regulation transistor is coupled to the control end of the drive circuit, a second pole of the voltage regulation transistor is coupled to the first node, and a gate of the voltage regulation transistor is coupled to the control end of the drive circuit. coupled to the control signal input end,
A first pole of the drive reset transistor is coupled to the drive reset voltage terminal, a gate of the drive reset transistor is coupled to the drive reset control signal input terminal, and a second pole of the drive reset transistor is coupled to the drive reset voltage terminal. is joined to the node of
A first pole of the light emitting reset transistor is coupled to the light emitting reset voltage terminal, a gate of the light emitting reset transistor is coupled to the light emitting reset control signal input terminal, and a second pole of the light emitting reset transistor is coupled to the light emitting reset voltage terminal. coupled to the first end of the
The array substrate according to claim 1, wherein the active layer of the voltage adjustment transistor includes an oxide semiconductor material, and the active layers of the drive transistor and the drive reset transistor include a silicon semiconductor material.
ことを特徴とする請求項２に記載のアレイ基板。 The array substrate according to claim 2, wherein the active layer of the light emitting reset transistor includes the oxide semiconductor material.
前記第１の活性半導体層は、前記サブストレートに位置し、前記シリコン半導体材料を含み、
前記第２の活性半導体層は、前記第１の活性半導体層の前記サブストレートから離れる側に位置し、前記酸化物半導体材料を含む
ことを特徴とする請求項３に記載のアレイ基板。 a first active semiconductor layer; a second active semiconductor layer;
the first active semiconductor layer is located on the substrate and includes the silicon semiconductor material;
4. The array substrate of claim 3, wherein the second active semiconductor layer is located on a side of the first active semiconductor layer away from the substrate and includes the oxide semiconductor material.
前記第２の活性半導体層は、列方向に沿って設けられた第１の部分及び第２の部分を含み、前記第２の活性半導体層の前記第１の部分は、前記電圧調整トランジスタの活性層を含み、前記第２の活性半導体層の前記第２の部分は、前記発光リセットトランジスタの活性層を含む
ことを特徴とする請求項４に記載のアレイ基板。 the first active semiconductor layer includes an active layer of the driving transistor and an active layer of the driving reset transistor;
5. The array substrate according to claim 4, wherein the second active semiconductor layer includes a first portion and a second portion arranged along a column direction, the first portion of the second active semiconductor layer includes an active layer of the voltage adjustment transistor, and the second portion of the second active semiconductor layer includes an active layer of the light-emitting reset transistor.
ことを特徴とする請求項５に記載のアレイ基板。 The array substrate according to claim 5, wherein the first portion of the second active semiconductor and the second portion of the second active semiconductor are aligned along a column direction.
前記データ書き込み回路は、データ信号入力端、スキャン信号入力端及び前記駆動回路の前記第１の端に結合され、前記スキャン信号入力端からのスキャン信号の制御で前記データ信号入力端からのデータ信号を前記駆動回路の前記第１の端に提供するように構成され、
前記補償回路は、前記駆動回路の前記第２の端、前記第１のノード及び補償制御信号入力端に結合され、前記補償制御信号入力端からの補償制御信号に応じて、前記駆動回路に対して閾値補償を行うように構成され、
前記記憶回路は、第１の電源電圧端及び前記駆動回路の前記制御端に結合され、前記第１の電源電圧端と前記駆動回路の前記制御端との間の電圧差を記憶するように構成され、
前記発光制御回路は、発光制御信号入力端、前記第１の電源電圧端、前記駆動回路の前記第１の端及び前記第２の端、発光リセット回路、及び前記発光素子に結合され、前記発光制御信号入力端からの発光制御信号の制御で前記第１の電源電圧端からの第１の電源電圧を前記駆動回路に印加し、前記駆動回路により発生した駆動電流を前記発光素子に印加するように構成される
ことを特徴とする請求項１に記載のアレイ基板。 The pixel circuit further includes a data writing circuit, a compensation circuit, a memory circuit, and a light emission control circuit,
The data writing circuit is coupled to a data signal input terminal, a scan signal input terminal, and the first end of the drive circuit, and writes a data signal from the data signal input terminal under the control of a scan signal from the scan signal input terminal. to the first end of the drive circuit,
The compensation circuit is coupled to the second end, the first node, and a compensation control signal input terminal of the drive circuit, and the compensation circuit performs a function on the drive circuit in response to a compensation control signal from the compensation control signal input terminal. configured to perform threshold compensation,
The storage circuit is coupled to a first power supply voltage terminal and the control terminal of the drive circuit, and is configured to store a voltage difference between the first power supply voltage terminal and the control terminal of the drive circuit. is,
The light emission control circuit is coupled to a light emission control signal input terminal, the first power supply voltage terminal, the first end and the second end of the drive circuit, a light emission reset circuit, and the light emitting element, and is configured to control the light emission. A first power supply voltage from the first power supply voltage terminal is applied to the drive circuit under the control of a light emission control signal from a control signal input terminal, and a drive current generated by the drive circuit is applied to the light emitting element. The array substrate according to claim 1 , characterized in that it is configured as follows.
前記データ書き込みトランジスタの第１の極が前記データ信号入力端に結合され、前記データ書き込みトランジスタのゲートが前記スキャン信号入力端に結合され、前記データ書き込みトランジスタの第２の極が前記駆動回路の前記第１の端に結合され、
前記補償トランジスタの第１の極が前記駆動回路の前記第２の端に結合され、前記補償トランジスタのゲートが前記補償制御信号入力端に結合され、前記補償トランジスタの第２の極が前記第１のノードに結合され、
前記記憶コンデンサの第１の極が前記第１の電源電圧端に結合され、前記記憶コンデンサの第２の極が前記駆動回路の前記制御端に結合され、前記第１の電源電圧端と前記駆動回路の前記制御端との間の電圧差を記憶するように構成され、
前記第１の発光制御トランジスタの第１の極が前記第１の電源電圧端に結合され、前記第１の発光制御トランジスタのゲートが前記発光制御信号入力端に結合され、前記第１の発光制御トランジスタの第２の極が前記駆動回路の前記第１の端に結合され、
前記第２の発光制御トランジスタの第１の極が前記駆動回路の前記第２の端に結合され、前記第２の発光制御トランジスタのゲートが前記発光制御信号入力端に結合され、前記第２の発光制御トランジスタの第２の極が前記発光素子の第１の極に結合される
ことを特徴とする請求項７に記載のアレイ基板。 The data write circuit includes a data write transistor, the compensation circuit includes a compensation transistor, the memory circuit includes a storage capacitor, and the light emission control circuit includes a first light emission control transistor and a second light emission control transistor. Contains a transistor
A first pole of the data write transistor is coupled to the data signal input terminal, a gate of the data write transistor is coupled to the scan signal input terminal, and a second pole of the data write transistor is coupled to the data signal input terminal of the drive circuit. coupled to the first end;
A first pole of the compensation transistor is coupled to the second end of the drive circuit, a gate of the compensation transistor is coupled to the compensation control signal input terminal, and a second pole of the compensation transistor is coupled to the second end of the drive circuit. is joined to the node of
A first pole of the storage capacitor is coupled to the first power supply voltage terminal, and a second pole of the storage capacitor is coupled to the control terminal of the drive circuit, and the first pole of the storage capacitor is coupled to the control terminal of the drive circuit, and the first pole of the storage capacitor is coupled to the control terminal of the drive circuit. configured to store a voltage difference between said control end of the circuit;
A first pole of the first light emission control transistor is coupled to the first power supply voltage terminal, a gate of the first light emission control transistor is coupled to the light emission control signal input terminal, and the first light emission control transistor is coupled to the first light emission control signal input terminal. a second pole of the transistor is coupled to the first end of the drive circuit;
A first pole of the second light emission control transistor is coupled to the second end of the drive circuit, a gate of the second light emission control transistor is coupled to the light emission control signal input terminal, and a first pole of the second light emission control transistor is coupled to the second end of the drive circuit. The array substrate according to claim 7, wherein a second pole of a light emission control transistor is coupled to a first pole of the light emitting element.
ことを特徴とする請求項８に記載のアレイ基板。 9. The array substrate according to claim 8, wherein the first active semiconductor layer includes active layers of the data write transistor, the compensation transistor, the first light emission control transistor, and the second light emission control transistor.
ことを特徴とする請求項９に記載のアレイ基板。 The array substrate according to claim 9, wherein the light emission reset control signal and the light emission control signal are the same signal.
ことを特徴とする請求項９に記載のアレイ基板。 The array substrate according to claim 9, wherein the scan signal and the compensation control signal are the same signal.
前記第１の導電層は、前記第１の活性半導体層と前記第２の活性半導体層との間に位置し、前記第１の導電層は、列方向に沿って順に設けられた駆動リセット制御信号線、スキャン信号線、前記駆動トランジスタのゲート、前記記憶コンデンサの第１の極、及び発光制御信号線を含み、
前記駆動リセット制御信号線は、前記駆動リセット制御信号入力端に結合され、前記駆動リセット制御信号入力端に前記駆動リセット制御信号を提供するように構成され、
前記スキャン信号線は、前記スキャン信号入力端及び前記補償制御信号入力端に結合され、前記スキャン信号入力端に前記スキャン信号を提供し、前記補償制御信号入力端に前記補償制御信号を提供するように構成され、
前記記憶コンデンサの第１の極と前記駆動トランジスタのゲートとは、一体に構成され、
前記発光制御信号線は、前記発光制御信号入力端に結合され、前記発光制御信号入力端に前記発光制御信号を提供するように構成される
ことを特徴とする請求項１１に記載のアレイ基板。 further comprising a first conductive layer;
The first conductive layer is located between the first active semiconductor layer and the second active semiconductor layer , and the first conductive layer has a drive reset layer provided in order along the column direction. including a control signal line, a scan signal line, a gate of the drive transistor, a first pole of the storage capacitor, and a light emission control signal line,
the drive reset control signal line is coupled to the drive reset control signal input and configured to provide the drive reset control signal to the drive reset control signal input;
The scan signal line is coupled to the scan signal input terminal and the compensation control signal input terminal, and is configured to provide the scan signal to the scan signal input terminal and the compensation control signal to the compensation control signal input terminal. consists of
The first pole of the storage capacitor and the gate of the drive transistor are integrally configured,
The array substrate of claim 11, wherein the light emission control signal line is coupled to the light emission control signal input terminal and configured to provide the light emission control signal to the light emission control signal input terminal.
前記スキャン信号線の前記サブストレート上への正投影が前記第１の活性半導体層の前記サブストレート上への正投影と重なる部分は、前記補償トランジスタのゲート及び前記データ書き込みトランジスタのゲートであり、
前記発光制御信号線の前記サブストレート上への正投影が前記第１の活性半導体層の前記サブストレート上への正投影と重なる部分は、前記第１の発光制御トランジスタのゲート及び前記第２の発光制御トランジスタのゲートである
ことを特徴とする請求項１２に記載のアレイ基板。 A portion where the orthogonal projection of the drive reset control signal line onto the substrate overlaps with the orthogonal projection of the first active semiconductor layer onto the substrate is a gate of the drive reset transistor;
Portions where the orthogonal projection of the scan signal line onto the substrate overlaps the orthogonal projection of the first active semiconductor layer onto the substrate are a gate of the compensation transistor and a gate of the data write transistor,
A portion where the orthogonal projection of the light emission control signal line onto the substrate overlaps with the orthogonal projection of the first active semiconductor layer onto the substrate is the gate of the first light emission control transistor and the portion where the orthographic projection of the first active semiconductor layer onto the substrate overlaps. The array substrate according to claim 12, which is a gate of a light emission control transistor.
前記第２の導電層は、前記第１の導電層と前記第２の活性半導体層との間に位置し、前記第２の導電層は、列方向に沿って設けられた電圧調整制御信号線、前記記憶コンデンサの第２の極、第１の電源電圧線及び発光リセット制御信号線を含み、
前記電圧調整制御信号線は、前記電圧調整制御信号入力端に結合され、前記電圧調整制御信号入力端に前記電圧調整制御信号を提供するように構成され、
前記第１の電源電圧線は、前記第１の電源電圧端に結合され、前記第１の電源電圧端に前記第１の電源電圧を提供するように構成され、
前記記憶コンデンサの第２の極と前記記憶コンデンサの第１の極の前記サブストレート上への正投影とは、少なくとも一部が重なり、
前記記憶コンデンサの第２の極と前記第１の電源電圧線とは、一体に形成され、
前記発光リセット制御信号線は、前記発光リセット制御信号入力端に結合され、前記発光リセット制御信号入力端に前記発光リセット制御信号を提供するように構成される
ことを特徴とする請求項１３に記載のアレイ基板。 further comprising a second conductive layer;
The second conductive layer is located between the first conductive layer and the second active semiconductor layer , and the second conductive layer is connected to a voltage adjustment control signal provided along the column direction. line, a second pole of the storage capacitor, a first power supply voltage line and a light emission reset control signal line,
the voltage regulation control signal line is coupled to the voltage regulation control signal input and configured to provide the voltage regulation control signal to the voltage regulation control signal input;
the first power supply voltage line is coupled to the first power supply voltage terminal and configured to provide the first power supply voltage to the first power supply voltage terminal;
orthographic projections of the second pole of the storage capacitor and the first pole of the storage capacitor onto the substrate at least partially overlap;
the second pole of the storage capacitor and the first power supply voltage line are integrally formed;
14. The light emission reset control signal line is coupled to the light emission reset control signal input and configured to provide the light emission reset control signal to the light emission reset control signal input. array board.
前記発光制御信号線の前記サブストレート上への正投影が前記第２の活性半導体層の前記サブストレート上への正投影と重なる部分は、前記発光リセットトランジスタの第１のゲートである
ことを特徴とする請求項１４に記載のアレイ基板。 a portion where the orthogonal projection of the voltage adjustment control signal line onto the substrate overlaps with the orthographic projection of the second active semiconductor layer onto the substrate is a first gate of the voltage adjustment transistor;
A portion where the orthographic projection of the light emission control signal line onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer onto the substrate is the first gate of the light emission reset transistor. The array substrate according to claim 14.
前記第３の導電層は、前記第２の活性半導体層の前記サブストレートから離れる側に位置し、前記第３の導電層は、列方向に沿って設けられた前記電圧調整制御信号線、前記発光リセット制御信号線、及び発光リセット電圧線を含む
ことを特徴とする請求項１５に記載のアレイ基板。 further comprising a third conductive layer;
The third conductive layer is located on a side of the second active semiconductor layer away from the substrate , and the third conductive layer is connected to the voltage adjustment control signal line provided along the column direction; The array substrate according to claim 15, comprising the light emission reset control signal line and the light emission reset voltage line.
前記発光リセット制御信号線の前記サブストレート上への正投影が前記第２の活性半導体層の前記サブストレート上への正投影と重なる部分は、前記発光リセットトランジスタの第２のゲートであり、
前記発光リセット電圧線は、ビアを介して前記第２の活性半導体層に結合されて、前記発光リセットトランジスタの第１の極を形成する
ことを特徴とする請求項１６に記載のアレイ基板。 A portion where the orthographic projection of the voltage adjustment control signal line onto the substrate overlaps with the orthographic projection of the second active semiconductor layer onto the substrate is a second gate of the voltage adjustment transistor;
A portion where the orthographic projection of the light emission reset control signal line onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer onto the substrate is a second gate of the light emission reset transistor;
17. The array substrate of claim 16, wherein the emission reset voltage line is coupled to the second active semiconductor layer via a via to form a first pole of the emission reset transistor.
前記第４の導電層は、前記第３の導電層の前記サブストレートから離れる側に位置し、前記第４の導電層は、第１の接続部、第２の接続部、第３の接続部、第４の接続部、第５の接続部、第６の接続部、第７の接続部、及び第８の接続部を含み、
前記第１の接続部は、前記駆動リセット電圧線として動作され、
前記第１の接続部は、ビアを介して前記駆動リセットトランジスタのドレイン領域に結合され、前記駆動リセットトランジスタの第１の極を形成し、
前記第２の接続部は、ビアを介して前記発光リセット電圧線に結合され、
前記第３の接続部は、ビアを介して前記データ書き込みトランジスタのドレイン領域に結合され、前記データ書き込みトランジスタの第１の極を形成し、
前記第４の接続部は、ビアを介して前記駆動リセットトランジスタのソース領域及び前記補償トランジスタのソース領域に結合され、前記駆動リセットトランジスタの第２の極及び前記補償トランジスタの第２の極をそれぞれ形成し、前記第４の接続部は、ビアを介して前記電圧調整トランジスタのソース領域に結合され、前記電圧調整トランジスタの第２の極を形成し、
前記第５の接続部は、ビアを介して前記駆動トランジスタのゲート及び前記記憶コンデンサの第１の極に結合され、前記第５の接続部は、ビアを介して前記電圧調整トランジスタのドレイン領域に結合され、前記電圧調整トランジスタの第１の極を形成し、
前記第６の接続部は、ビアを介して前記第１の発光制御トランジスタのドレイン領域に結合され、前記第１の発光制御トランジスタの第１の極を形成し、
前記第７の接続部は、ビアを介して前記第２の発光制御トランジスタのソース領域に結合され、前記第２の発光制御トランジスタの第２の極を形成し、前記第７の接続部は、ビアを介して前記発光リセットトランジスタのソース領域に結合され、前記発光リセットトランジスタの第２の極を形成し、
前記第８の接続部は、ビアを介して前記発光リセットトランジスタのソース領域に結合され、前記発光リセットトランジスタの第１の極を形成する
ことを特徴とする請求項１７に記載のアレイ基板。 further comprising a fourth conductive layer;
The fourth conductive layer is located on a side of the third conductive layer away from the substrate , and the fourth conductive layer is located at a first connection portion, a second connection portion, and a third connection portion. part, a fourth connection part, a fifth connection part, a sixth connection part, a seventh connection part, and an eighth connection part,
the first connection part is operated as the drive reset voltage line,
the first connection is coupled to a drain region of the drive reset transistor via a via and forms a first pole of the drive reset transistor;
the second connection is coupled to the light emitting reset voltage line via a via;
the third connection is coupled to a drain region of the data write transistor via a via and forms a first pole of the data write transistor;
The fourth connection is coupled via a via to a source region of the drive reset transistor and a source region of the compensation transistor, and connects a second pole of the drive reset transistor and a second pole of the compensation transistor, respectively. forming, the fourth connection is coupled to a source region of the voltage adjustment transistor via a via, forming a second pole of the voltage adjustment transistor;
The fifth connection is coupled via a via to the gate of the drive transistor and the first pole of the storage capacitor, and the fifth connection is coupled via a via to the drain region of the voltage regulation transistor. coupled to form a first pole of the voltage regulating transistor;
the sixth connection portion is coupled to a drain region of the first light emission control transistor via a via, and forms a first pole of the first light emission control transistor;
The seventh connection is coupled to the source region of the second light emission control transistor via a via and forms a second pole of the second light emission control transistor, and the seventh connection includes: coupled to a source region of the light emitting reset transistor via a via, forming a second pole of the light emitting reset transistor;
18. The array substrate of claim 17, wherein the eighth connection is coupled to a source region of the light emitting reset transistor via a via and forming a first pole of the light emitting reset transistor.
前記第５の導電層は、前記第４の導電層の前記サブストレートから離れる側に位置し、前記第５の導電層は、行方向に沿って設けられたデータ信号線、前記第１の電源電圧線、及び第２の電源電圧線を含み、
前記データ信号線は、列方向に沿って延在され、ビアを介して前記第４の導電層の前記第３の接続部に結合され、
前記第１の電源電圧線は、列方向に沿って延在され、ビアを介して前記第４の導電層の前記第３の接続部に結合され、
前記第２の電源電圧線は、列方向に沿って延在され、ビアを介して前記第４の導電層の前記第７の接続部に結合される
ことを特徴とする請求項１８に記載のアレイ基板。 further comprising a fifth conductive layer,
The fifth conductive layer is located on a side of the fourth conductive layer that is away from the substrate , and the fifth conductive layer is located on a side of the fourth conductive layer that is away from the substrate, and the fifth conductive layer is connected to the data signal line provided along the row direction, and the first conductive layer. including a power supply voltage line and a second power supply voltage line;
The data signal line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer via a via,
the first power supply voltage line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer via a via;
19. The second power supply voltage line extends along the column direction and is coupled to the seventh connection portion of the fourth conductive layer via a via. array substrate.
ことを特徴とする表示パネル。 A display panel comprising the array substrate according to claim 1.
ことを特徴とする表示装置。 A display device comprising the display panel according to claim 20.
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| PCT/CN2021/081923 WO2022170661A1 (en) | 2021-02-10 | 2021-03-19 | Array substrate, and display panel and display apparatus thereof |
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