WO2022170661A1

WO2022170661A1 - Array substrate, and display panel and display apparatus thereof

Info

Publication number: WO2022170661A1
Application number: PCT/CN2021/081923
Authority: WO
Inventors: 刘利宾
Original assignee: 京东方科技集团股份有限公司
Priority date: 2021-02-10
Filing date: 2021-03-19
Publication date: 2022-08-18
Also published as: WO2022170661A9

Abstract

An array substrate (10), a related display panel (700), and a related display apparatus (800). The array substrate (10) comprises: a substrate (300); multiple subpixels (SPX) that are provided on the substrate (300) and arranged in multiple rows and multiple columns, at least one of the multiple subpixels (SPX) comprising a pixel circuit (100), and each pixel circuit (100) comprising a driving circuit (110), a voltage stabilizing circuit (120), a driving reset circuit (130), and a light-emitting reset circuit (140), wherein the driving circuit (110) is configured to provide a drive current for a light-emitting device (200), the voltage stabilizing circuit (120) is configured to enable a control terminal (G) of the driving circuit (110) to be connected to the driving reset circuit (130), the driving reset circuit (130) is configured to reset the control terminal (G) of the driving circuit (110), and the light-emitting reset circuit (140) is configured to reset the light-emitting device (200); a driving reset voltage line (VINL1) that is coupled to a driving reset voltage terminal (Vinit1) and configured to provide a driving reset voltage (VINT1) for the driving reset voltage terminal; and a light-emitting reset voltage line (VINL2) that is coupled to a light-emitting reset voltage terminal (Vinit2) and configured to provide a light-emitting reset voltage (VINT2) for the light-emitting reset voltage terminal.

Description

Array substrate, display panel and display device thereof

cross reference

The present disclosure claims the priority of the PCT International Application No. PCT/CN2021/076577, filed on February 10, 2021, entitled "Array Substrate, Display Panel and Display Device", the entire content of which is through Reference is incorporated herein in its entirety.

technical field

Embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a display panel and a display device thereof.

Background technique

Organic Light-Emitting Diode (OLED) display panels have the advantages of self-luminescence, high efficiency, bright colors, light weight, power saving, rollability, and wide temperature range, and have been gradually applied to large-area displays, lighting, and automotive displays. and other fields.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide array substrates and related display panels and display devices.

According to a first aspect of the present disclosure, there is provided an array substrate including a substrate. The array substrate further includes a plurality of sub-pixels arranged on the substrate and arranged in rows and columns. At least one of the plurality of subpixels includes a pixel circuit. Each pixel circuit includes: a driving circuit, a voltage regulator circuit, a driving reset circuit and a light-emitting reset circuit. The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current to the light emitting device. The voltage stabilizing circuit is coupled to the control terminal of the driving circuit, the first node and the voltage stabilizing control signal input terminal, and is configured to enable the control of the driving circuit under the control of the voltage stabilizing control signal from the voltage stabilizing control signal input terminal terminal and the first node are turned on. The driving reset circuit is coupled to the driving reset control signal input terminal, the first node and the driving reset voltage terminal, and is configured to convert the driving reset voltage terminal from the driving reset voltage terminal under the control of the driving reset control signal from the driving reset control signal input terminal. The reset voltage is provided to the voltage regulator circuit to reset the control terminal of the drive circuit. The light-emitting reset circuit is coupled to the light-emitting reset control signal input end, the light-emitting device and the light-emitting reset voltage end, and is configured to reset the light-emitting reset voltage from the light-emitting reset voltage end under the control of the light-emitting reset control signal from the light-emitting reset control signal input end A voltage is supplied to the light emitting device to reset the light emitting device. The array substrate further includes a driving reset voltage line and a light emitting reset voltage line. The driving reset voltage line is coupled to the driving reset voltage terminal to provide the driving reset voltage. The light-emitting reset voltage line is coupled to the light-emitting reset voltage terminal to provide the light-emitting reset voltage.

In an embodiment of the present disclosure, the driving circuit includes a driving transistor. The voltage regulator circuit includes a voltage regulator transistor. The drive reset circuit includes a drive reset transistor. The light-emitting reset circuit includes a light-emitting reset transistor. The first pole of the driving transistor is coupled to the first terminal of the driving circuit, the gate of the driving transistor is coupled to the control terminal of the driving circuit, and the second pole of the driving transistor is coupled to the second terminal of the driving circuit. The first electrode of the voltage-stabilizing transistor is coupled to the control terminal of the driving circuit, the gate of the voltage-stabilizing transistor is coupled to the input terminal of the voltage-stabilizing control signal, and the second electrode of the voltage-stabilizing transistor is coupled to the first node. The first electrode of the drive reset transistor is coupled to the drive reset voltage terminal, the gate of the drive reset transistor is coupled to the drive reset control signal input end, and the second electrode of the drive reset transistor is coupled to the first node. The first electrode of the light-emitting reset transistor is coupled to the light-emitting reset voltage terminal, the gate of the light-emitting reset transistor is coupled to the light-emitting reset control signal input end, and the second electrode of the light-emitting reset transistor is coupled to the first end of the light-emitting device . The active layer of the voltage regulator transistor includes an oxide semiconductor material. The active layers of the drive transistor and the drive reset transistor include silicon semiconductor material.

In an embodiment of the present disclosure, the active layer of the light-emitting reset transistor includes an oxide semiconductor material.

In an embodiment of the present disclosure, the array substrate further includes: a first active semiconductor layer on the substrate, the first active semiconductor layer comprising a silicon semiconductor material; and the first active semiconductor layer facing away from the substrate A second active semiconductor layer on one side and insulated from the first active semiconductor layer, the second active semiconductor layer comprising an oxide semiconductor material.

In an embodiment of the present disclosure, the first active semiconductor layer includes an active layer of a driving transistor and an active layer of a driving reset transistor. The second active semiconductor layer includes a first portion and a second portion arranged in a column direction. The first portion of the second active semiconductor includes the active layer of the voltage regulator transistor. The second portion of the second active semiconductor includes the active layer of the light emitting reset transistor.

In an embodiment of the present disclosure, the first portion of the second active semiconductor is aligned with the second portion of the second active semiconductor in the column direction.

In an embodiment of the present disclosure, the pixel circuit further includes a data writing circuit, a compensation circuit, a storage circuit, and a light emission control circuit. The data writing circuit is coupled to the data signal input terminal, the scan signal input terminal and the first terminal of the driving circuit, and is configured to provide the data signal from the data signal input terminal under the control of the scan signal from the scan signal input terminal to the first terminal of the drive circuit. The compensation circuit is coupled to the second end of the drive circuit, the first node and the compensation control signal input end, and is configured to perform threshold compensation on the drive circuit according to the compensation control signal from the compensation control signal input end. The storage circuit is coupled to the first power supply voltage terminal and the control terminal of the driving circuit, and is configured to store a voltage difference between the first power supply voltage terminal and the control terminal of the driving circuit. The lighting control circuit is coupled to the lighting control signal input terminal, the first power supply voltage terminal, the first terminal and the second terminal of the driving circuit, the lighting reset circuit and the lighting device, and is configured to be in the middle of the lighting control signal from the lighting control signal input terminal. Under control, the first power supply voltage from the first power supply voltage terminal is applied to the driving circuit, and the driving current generated by the driving circuit is applied to the light emitting device.

In an embodiment of the present disclosure, the data writing circuit includes a data writing transistor. The compensation circuit includes a compensation transistor. The storage circuit includes a storage capacitor. The lighting control circuit includes a first lighting control transistor and a second lighting control transistor. The first pole of the data writing transistor is coupled to the data signal input terminal, the gate of the data writing transistor is coupled to the scan signal input terminal, and the second pole of the data writing transistor is coupled to the first terminal of the driving circuit catch. The first electrode of the compensation transistor is coupled to the second end of the driving circuit, the gate of the compensation transistor is coupled to the compensation control signal input end, and the second electrode of the compensation transistor is coupled to the first node. The first pole of the storage capacitor is coupled to the first power supply voltage terminal, and the second pole of the storage capacitor is coupled to the control terminal of the driving circuit, and is configured to store the voltage between the first power supply voltage terminal and the control terminal of the driving circuit Difference. The first electrode of the first light-emitting control transistor is coupled to the first power supply voltage terminal, the gate of the first light-emitting control transistor is coupled to the light-emitting control signal input end, and the second electrode of the first light-emitting control transistor is coupled to the driving circuit. The first end is coupled. and the first electrode of the second light-emitting control transistor is coupled to the second end of the driving circuit, the gate of the second light-emitting control transistor is coupled to the light-emitting control signal input end, and the second electrode of the second light-emitting control transistor is coupled to the input end of the light-emitting control signal. The first pole of the light emitting device is coupled.

In an embodiment of the present disclosure, the first active semiconductor layer includes an active layer of a data writing transistor, a compensation transistor, a first light emission control transistor, and a second light emission control transistor.

In the embodiment of the present disclosure, the light-emitting reset control signal and the light-emitting control signal are the same signal.

In the embodiment of the present disclosure, the scan signal and the compensation control signal are the same signal.

In an embodiment of the present disclosure, the array substrate further includes a spacer between the first active semiconductor layer and the second active semiconductor layer and insulated from the first active semiconductor layer and the second active semiconductor layer the first conductive layer. The first conductive layer includes a drive reset control signal line, a scan signal line, a gate of a drive transistor, a first electrode of a storage capacitor, and a light emission control signal line, which are sequentially arranged along the column direction. The drive reset control signal line is coupled to the drive reset control signal input terminal, and is configured to provide the drive reset control signal thereto. The scan signal line is coupled to a scan signal input terminal and a compensation control signal input terminal, is configured to provide a scan signal to the scan signal input terminal, and is configured to provide a compensation control signal to the compensation control signal input terminal. The first electrode of the storage capacitor and the gate of the driving transistor are integrally formed. And the light-emitting control signal line is coupled to the light-emitting control signal input terminal, and is configured to provide the light-emitting control signal thereto.

In the embodiment of the present disclosure, the overlapping portion of the orthographic projection of the driving reset control signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the driving reset transistor. The overlapping portion of the orthographic projection of the scanning signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the compensation transistor and the gate of the data writing transistor. And the overlapping part of the orthographic projection of the light-emitting control signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor.

In an embodiment of the present disclosure, the array substrate further includes a second conductive layer located between the first conductive layer and the second active semiconductor layer and insulated from the first conductive layer and the second active semiconductor layer . The second conductive layer includes a voltage regulation control signal line arranged along the column direction, a second pole of the storage capacitor, a first power supply voltage line and a light-emitting reset control signal line. The voltage stabilization control signal line is coupled to the voltage stabilization control signal input terminal, and is configured to provide the voltage stabilization control signal thereto. The first power supply voltage line is coupled to the first power supply voltage terminal and is configured to provide the first power supply voltage thereto. The second pole of the storage capacitor at least partially overlaps the orthographic projection of the first pole of the storage capacitor on the substrate. The second pole of the storage capacitor is integrally formed with the first power supply voltage line. And the light-emitting reset control signal line is coupled to the light-emitting reset control signal input terminal, and is configured to provide the light-emitting reset control signal thereto.

In the embodiment of the present disclosure, the overlapping portion of the orthographic projection of the voltage-stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first gate of the voltage-stabilizing transistor. And the overlapping part of the orthographic projection of the light-emitting control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first control electrode of the light-emitting reset transistor.

In an embodiment of the present disclosure, the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated from the second active semiconductor layer. The third conductive layer includes voltage regulation control signal lines, light emission reset control signal lines, and light emission reset voltage lines arranged along the column direction.

In the embodiment of the present disclosure, the overlapping portion of the orthographic projection of the voltage-stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second gate of the voltage-stabilizing transistor. The overlapping portion of the orthographic projection of the light-emitting control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second control electrode of the light-emitting reset transistor. and the light-emitting reset voltage line is coupled to the second active semiconductor layer through the via hole to form the first electrode of the light-emitting reset transistor.

In an embodiment of the present disclosure, the array substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate and insulated from the third conductive layer, the fourth conductive layer includes a first connection portion, A second connection portion, a third connection portion, a fourth connection portion, a fifth connection portion, a sixth connection portion, a seventh connection portion, and an eighth connection portion. The first connection portion serves as a drive reset voltage line. The first connection portion is coupled to the drain region of the driving reset transistor through a via hole, and forms a first electrode of the driving reset transistor. The second connection portion is coupled to the light-emitting reset voltage line through the via hole. The third connection portion is coupled to the drain region of the data writing transistor through the via hole, and forms the first electrode of the data writing transistor. The fourth connection portion is coupled to the source region of the drive reset transistor and the source region of the compensation transistor through a via hole, and forms a second electrode of the drive reset transistor and a second electrode of the compensation transistor, respectively. The fourth connection portion is coupled to the source region of the voltage-stabilizing transistor through a via hole to form a second electrode of the voltage-stabilizing transistor. The fifth connection portion is coupled to the gate of the driving transistor and the first electrode of the storage capacitor through the via hole, and the fifth connection portion is coupled to the drain region of the voltage-stabilizing transistor through the via hole, forming the first electrode of the voltage-stabilizing transistor. one pole. The sixth connection portion is coupled to the drain region of the first light-emitting control transistor through a via hole, and forms a first electrode of the first light-emitting control transistor. The seventh connection portion is coupled to the source region of the second light-emitting control transistor through a via hole to form a second electrode of the second light-emitting control transistor, and the seventh connection portion is coupled to the source region of the light-emitting reset transistor via a via hole connected to form the second pole of the light-emitting reset transistor. And the eighth connection part is coupled with the source region of the light-emitting reset transistor through the via hole, and forms the first electrode of the light-emitting reset transistor.

In an embodiment of the present disclosure, the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated from the fourth conductive layer. The fifth conductive layer includes data signal lines, first power supply voltage lines, and second power supply voltage lines arranged along the row direction. The data signal line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer through the via hole.

The first power supply voltage line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer through the via hole. and the second power supply voltage line extends along the column direction and is coupled to the seventh connection portion of the fourth conductive layer through the via hole.

According to a second aspect of the present disclosure, a display panel is provided. The display panel includes the array substrate according to any one of the first aspects.

According to a third aspect of the present disclosure, a display device is provided. The display device includes the display panel according to any one of the second aspects.

Further aspects and scope of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the application.

Description of drawings

The drawings described herein are for illustrative purposes only of selected embodiments, and not all possible implementations, and are not intended to limit the scope of the application, wherein:

FIG. 1 shows a schematic block diagram of an array substrate according to the present disclosure;

FIG. 2 shows a schematic block diagram of a sub-pixel according to an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of the pixel circuit in FIG. 2 according to an embodiment of the present disclosure;

FIG. 4 illustrates a timing diagram of signals driving the pixel circuit in FIG. 3 according to an embodiment of the present disclosure;

5-11 illustrate schematic plan views of layers in an array substrate according to an embodiment of the present disclosure;

12 shows a schematic plan layout of a pixel circuit including a stacked active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

FIG. 13 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A1A2 in FIG. 12 according to an embodiment of the present disclosure;

FIG. 14 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A1A2 in FIG. 12 according to an embodiment of the present disclosure;

15 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure;

16 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure;

17 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure;

18 shows a schematic plan layout of a pixel circuit including a stacked blocking layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

FIG. 19 shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 20 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure;

21 shows a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

22 shows a schematic diagram of a blocking layer of an embodiment of the present disclosure;

FIG. 23 shows a plan layout of a pixel circuit of an embodiment of the present disclosure;

FIG. 24 shows a plan layout of a pixel circuit of an embodiment of the present disclosure;

FIG. 25 shows a plan layout of a pixel circuit of an embodiment of the present disclosure;

FIG. 26 shows a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure;

27 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of the disclosed array substrate;

FIG. 28 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 27;

FIG. 29 is a structural layout of an exemplary embodiment of the disclosed array substrate;

Fig. 30 is the structural layout of the light shielding layer in Fig. 29;

Fig. 31 is the structural layout of the first active layer in Fig. 29;

FIG. 32 is a structural layout of the first gate layer in FIG. 29;

FIG. 33 is a structural layout of the second gate layer in FIG. 29;

Fig. 34 is the structural layout of the second active layer in Fig. 29;

FIG. 35 is a structural layout of the third gate layer in FIG. 29;

FIG. 36 is a structural layout of the first source-drain layer in FIG. 29;

Fig. 37 is the structural layout of the light shielding layer and the first active layer in Fig. 29;

FIG. 38 is a structural layout of the light shielding layer, the first active layer, and the first gate layer in FIG. 29;

FIG. 39 is a structural layout of the light-shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 29;

40 is a structural layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 29;

41 is a structural layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 29;

FIG. 42 is a structural layout of an exemplary embodiment of the disclosed array substrate;

FIG. 43 is a structural layout of the second source-drain layer in FIG. 42;

FIG. 44 is a structural layout of an exemplary embodiment of the disclosed array substrate;

FIG. 45 is a structural layout of the second source-drain layer in FIG. 44;

46 is a schematic structural diagram of a second initial signal line in another exemplary embodiment of the disclosed array substrate;

47 is a schematic structural diagram of a second initial signal line in another exemplary embodiment of the disclosed array substrate;

FIG. 48 is a partial cross-sectional view taken along the dotted line B in FIG. 42 .

Corresponding reference numerals indicate corresponding parts or features throughout the various views of the drawings.

Detailed ways

First, it should be noted that unless the context clearly dictates otherwise, the singular forms of words used herein and in the appended claims include the plural and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "comprising" and "including" are to be construed as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be construed as inclusive unless otherwise indicated herein. Where the term "instance" is used herein, particularly when it follows a group of terms, the "instance" is merely exemplary and illustrative and should not be considered exclusive or broad .

In addition, it should also be noted that when introducing elements of the present application and embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements; unless otherwise Where stated, "plurality" means two or more; the terms "comprising", "including", "containing" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements elements; the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be construed to indicate or imply relative importance and formation order.

Further, in the drawings, the thicknesses and regions of various layers are exaggerated for clarity. It will be understood that when a layer, region, or component is referred to as being "on" another part, it means that it is directly on the other part, or other components may also be intervening. Conversely, when a component is referred to as being "directly" on top of another component, it means that no other component is in between.

In a general array substrate, a reset voltage is supplied from the same reset voltage line to reset the light-emitting device and the pixel circuit. The value of the reset voltage is set in consideration of the power consumption level of the pixel circuit, the display effect after compensation, and keeping the reset light-emitting device in an unlit state. In this case, the power consumption of the pixel circuit, the display effect after compensation, and the charging time of the light-emitting device after reset cannot be in an optimal state at the same time, thereby affecting the power consumption, response speed, accuracy, and display of the pixel circuit. Effect.

At least some embodiments of the present disclosure provide an array substrate including two reset voltage lines, a driving reset voltage line and a light emitting reset voltage line. The driving reset voltage line is coupled to the driving reset voltage terminal to provide the driving reset voltage. The light-emitting reset voltage line is coupled to the light-emitting reset voltage terminal to provide the light-emitting reset voltage. The driving reset voltage may be set in consideration of the power consumption level of the pixel circuit and the reset effect. In the case of relatively low power consumption levels, the pixel circuit is reset more thoroughly, thereby improving the display effect. The light-emitting reset voltage line is coupled to the light-emitting reset voltage terminal to provide the light-emitting reset voltage. The light-emitting reset voltage can be set just when the light-emitting device is just not lit, thereby reducing the charging time of the light-emitting device before emitting light, thereby improving the response speed of the pixel circuit to the light-emitting signal, shortening the response time, and increasing the probability Accuracy.

The array substrate provided by the embodiments of the present disclosure is described below in a non-limiting manner with reference to the accompanying drawings. As described below, different features in these specific embodiments can be combined with each other without conflicting with each other to obtain new embodiments. For example, these new embodiments also belong to the protection scope of the present disclosure.

FIG. 1 shows a schematic diagram of an array substrate 10 according to the present disclosure. As shown in FIG. 1 , the array substrate 10 includes a substrate 300 and a plurality of sub-pixels SPX arranged on the substrate 300 and arranged in multiple rows and columns. The substrate may be a glass substrate, a plastic substrate, or the like. The display area of the substrate 300 includes a plurality of pixel units PX, and each pixel unit may include a plurality of sub-pixels SPX, for example, three. The sub-pixels SPX are arranged at intervals along the row direction X and the column direction Y. The row direction X and the column direction Y are perpendicular to each other. At least one of the sub-pixels SPX includes a pixel circuit. The array substrate 10 further includes a driving reset voltage line and a light emitting reset voltage line. The driving reset signal line is coupled to the driving reset voltage terminal, and is configured to provide the driving reset voltage thereto. The light-emitting reset voltage line is coupled to the light-emitting reset voltage terminal and configured to provide the light-emitting reset voltage thereto. The layout of the settings and positions of the voltages of the drive reset signal lines and the light emission reset control signal lines will be described in detail below with reference to circuit diagrams 5-11.

In the embodiment of the present disclosure, each pixel circuit includes: a driving circuit, a voltage regulator circuit, a driving reset circuit, a lighting reset circuit, a data writing circuit, a compensation circuit, a storage circuit, and a lighting control circuit. The pixel circuit will be described in detail below with reference to FIG. 2 .

FIG. 2 shows a schematic block diagram of a sub-pixel according to some embodiments of the present disclosure. As shown in FIG. 2 , the sub-pixel SPX includes a pixel circuit 100 and a light emitting device 200 . The pixel circuit 100 includes: a driving circuit 110 , a voltage regulator circuit 120 , a driving reset circuit 130 , a lighting reset circuit 140 , a data writing circuit 150 , a compensation circuit 160 , a storage circuit 170 and a lighting control circuit 180 .

As shown in FIG. 2 , the driving circuit 110 includes a control terminal G, a first terminal F and a second terminal S. The driving circuit 110 is configured to provide a driving current to the light emitting device 200 under the control of a control signal from the control terminal G.

The voltage-stabilizing circuit 120 is coupled to the control terminal G of the driving circuit 110 , the first node N1 and the voltage-stabilizing control signal input terminal Stv. The voltage-stabilizing circuit 120 is configured to conduct the control terminal G of the driving circuit 110 with the first node N1 under the control of the voltage-stabilizing control signal from the voltage-stabilizing control signal input terminal.

The driving reset circuit 130 is coupled to the driving reset control signal input terminal Rst1 , the first node N1 and the driving reset voltage terminal Vinit1 . The driving reset circuit 130 is configured to provide the driving reset voltage from the driving reset voltage terminal Vinit1 to the voltage regulator circuit 120 under the control of the driving reset control signal from the driving reset control signal input terminal Rst1, so as to control the control terminal of the driving circuit 110. G to reset.

The light-emitting reset circuit 140 is coupled to the light-emitting reset control signal input terminal Rst2, the light-emitting device 200, and the light-emitting reset voltage terminal Vinit2. Further, the light-emitting reset circuit 140 is also coupled to the light-emitting control circuit 180 . The light emitting reset circuit 140 is configured to supply the light emitting reset voltage from the light emitting reset voltage terminal Vinit2 to the light emitting device 200 under the control of the light emitting reset control signal from the light emitting reset control signal input terminal Rst2 to reset the anode of the light emitting device 200 .

The data writing circuit 150 is coupled to the data signal input terminal Data, the scan signal input terminal Gate and the first terminal F of the driving circuit 110 . The data writing circuit 150 is configured to supply the data signal from the data signal input terminal Data to the first terminal F of the driving circuit 110 under the control of the scan signal from the scan signal input terminal Gate.

The compensation circuit 160 is coupled to the second end S of the driving circuit 110 , the first node N1 and the compensation control signal input end Com. The compensation circuit 160 is configured to perform threshold compensation on the driving circuit 110 according to the compensation control signal from the compensation control signal input terminal Com.

In the embodiment of the present disclosure, the scan signal from the scan signal input terminal Gate and the compensation control signal from the compensation control signal input terminal Com may be the same signal.

The storage circuit 170 is coupled to the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 . The storage circuit 170 is configured to store the voltage difference between the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 .

The lighting control circuit 180 is coupled to the lighting control signal input terminal EM, the first power supply voltage terminal VDD, the first terminal F and the second terminal S of the driving circuit 110 , the lighting reset circuit 140 , and the lighting device 200 . The lighting control circuit 180 is configured to apply the first power supply voltage from the first power supply voltage terminal VDD to the driving circuit 110 under the control of the lighting control signal from the lighting control signal input terminal EM, and to apply the driving current generated by the driving circuit 110 applied to the light emitting device 200 .

In some embodiments of the present disclosure, the lighting reset control signal from the lighting reset control signal input terminal Rst2 and the lighting control signal from the lighting control signal input terminal EM may be the same signal.

Additionally or alternatively, in some embodiments of the present disclosure, the light emission reset control signal from the light emission reset control signal input terminal Rst2 and the scan signal from the scan signal input terminal Gate may be the same signal.

The light-emitting device 200 is coupled to the second power supply voltage terminal VSS, the light-emitting reset circuit 140 and the light-emitting control circuit 180 . The light emitting device 200 is configured to emit light under the driving of the driving current generated by the driving circuit 110 . For example, the light emitting device 200 may be a light emitting diode or the like. The light emitting diode may be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or the like.

In the embodiment of the present disclosure, the voltage regulation control signal, the scan signal, the drive reset control signal, the light emission reset control signal, the compensation control signal, the light emission control signal, and the compensation control signal may be square waves, and the value range of the high level may be It is 0~15V, and the value range of the low level is 0~-15V. For example, the high level is 7V, and the low level is -7V. The value range of the data signal may be 0 to 8V, for example, 2 to 5V. The value range of the first power supply voltage Vdd may be 3-6V. The value range of the second power supply voltage Vss may be 0-6V.

FIG. 3 shows a schematic diagram of the pixel circuit 100 in FIG. 2 . As shown in FIG. 3 , the driving circuit 110 includes a driving transistor T1, the voltage-stabilizing circuit 120 includes a voltage-stabilizing transistor T2, the driving reset circuit 130 includes a driving reset transistor T3, the light-emitting reset circuit 140 includes a light-emitting reset transistor T4, and the data writing circuit 150 includes The data is written into the transistor T5, the compensation circuit 160 includes a compensation transistor T6, the storage circuit 170 includes a storage capacitor C, and the light emission control circuit 180 includes a first light emission control transistor T7 and a second light emission control transistor T8.

As shown in FIG. 3 , the first pole of the driving transistor T1 is coupled to the first terminal F of the driving circuit 110 , the second pole of the driving transistor T1 is coupled to the second terminal S of the driving circuit 110 , and the gate of the driving transistor T1 is It is coupled to the control terminal G of the driving circuit 110 .

The first pole of the voltage-stabilizing transistor T2 is coupled to the control terminal G of the driving circuit 110 , the gate of the voltage-stabilizing transistor T2 is coupled to the voltage-stabilizing control signal input terminal Stv, and the second electrode of the voltage-stabilizing transistor T2 is connected to the first node N1 coupled.

The first pole of the drive reset transistor T3 is coupled to the drive reset voltage terminal Vinit1, the gate of the drive reset transistor T3 is coupled to the drive reset control signal input terminal Rst1, and the second pole of the drive reset transistor T3 is coupled to the first node N1 .

The first pole of the light emitting reset transistor T4 is coupled to the light emitting reset voltage terminal Vinit2, the gate of the light emitting reset transistor T4 is coupled to the light emitting reset control signal input terminal Rst2, and the second pole of the light emitting reset transistor T4 is coupled to the anode of the light emitting device 200 catch. Further, the second pole of the light-emitting reset transistor T4 is also coupled to the second pole of the second light-emitting control transistor T8.

The first pole of the data writing transistor T5 is coupled to the data signal input terminal Data, the gate of the data writing transistor T5 is coupled to the scanning signal input terminal Gate, and the second pole of the data writing transistor T5 is coupled to the first pole of the driving circuit 110 . One end F is coupled.

The first electrode of the compensation transistor T6 is coupled to the second end S of the driving circuit 110, the gate of the compensation transistor T6 is coupled to the compensation control signal input end Com, and the second electrode of the compensation transistor T6 is coupled to the first node N1.

The first pole of the storage capacitor C is coupled to the first power supply voltage terminal VDD, and the second pole of the storage capacitor C is coupled to the control terminal G of the driving circuit 110 . The storage capacitor is configured to store the voltage difference between the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 .

The first electrode of the first light-emitting control transistor T7 is coupled to the first power supply voltage terminal VDD, the gate of the first light-emitting control transistor T7 is coupled to the light-emitting control signal input end EM, and the second electrode of the first light-emitting control transistor T7 is coupled to the light-emitting control signal input end EM. The first end F of the driving circuit 110 is coupled.

The first electrode of the second light-emitting control transistor T8 is coupled to the second end S of the driving circuit 110 , the gate of the second light-emitting control transistor T8 is coupled to the light-emitting control signal input end EM, and the second light-emitting control transistor T8 The pole is coupled to the anode of the light emitting device 200 .

In an embodiment of the present disclosure, the active layers of the voltage-stabilizing transistor T2 and the light-emitting reset transistor T4 may include oxide semiconductor materials, such as metal oxide semiconductor materials. Active layers of the driving transistor T1, the driving reset transistor T3, the data writing transistor T5, the compensation transistor T6, the first light emission control transistor T7 and the second light emission control transistor T8 may include silicon semiconductor materials.

In the embodiment of the present disclosure, in the case that the light emission reset control signal and the light emission control signal may be the same signal, the light emission reset transistor T4 and the first light emission control transistor T7 and the second light emission control transistor T8 may be different types of transistors. For example, the light-emission reset transistor T4 may be an N-type transistor, and the first light-emission control transistor T7 and the second light-emission control transistor T8 may be P-type transistors. The stabilizing transistor T2 may be an N-type transistor. The driving transistor T1, the driving reset transistor T3, the data writing transistor T5, and the compensation transistor T6 may be P-type transistors.

In the embodiment of the present disclosure, in the case where the light-emitting reset control signal and the light-emitting control signal may be the same signal, the light-emitting reset transistor T4 and the data writing transistor T5 are transistors of the same type. For example, the light-emitting reset transistor T4 and the data writing transistor T5 may be P-type transistors. The stabilizing transistor T2 may be an N-type transistor. The driving transistor T1, the driving reset transistor T3, the compensation transistor T6, the first light emission control transistor T7 and the second light emission control transistor T8 may be P-type transistors.

In addition, it should be noted that the transistors used in the embodiments of the present disclosure can all be P-type transistors or N-type transistors, and it is only necessary to refer to the respective poles of the transistors of the selected type with reference to the corresponding transistors in the embodiments of the present disclosure. Each pole is connected correspondingly, and the corresponding high voltage or low voltage can be provided at the corresponding voltage terminal. For example, for an N-type transistor, its input is the drain and the output is the source, and its control is the gate; for a P-type transistor, its input is the source and the output is the drain, and its control is the gate pole. For different types of transistors, the level of the control signal at the control terminal is also different. For example, for an N-type transistor, when the control signal is at a high level, the N-type transistor is in an on state; and when the control signal is at a low level, the N-type transistor is in an off state. For a P-type transistor, when the control signal is at a low level, the P-type transistor is in an on state; and when the control signal is at a high level, the P-type transistor is in an off state. The oxide semiconductor may include, for example, Indium Gallium Zinc Oxide (IGZO). The silicon semiconductor material may include low temperature polysilicon (LTPS) or amorphous silicon (eg hydrogenated amorphous silicon). Low temperature polysilicon generally refers to the case where the crystallization temperature of polysilicon obtained by crystallization of amorphous silicon is lower than 600 degrees Celsius.

In addition, it should be noted that, in the embodiments of the present disclosure, the pixel circuit of the sub-pixel may include other numbers of transistors in addition to the 8T1C (ie, eight transistors and one capacitor) structure shown in FIG. 4 . , such as an 8T2C structure, a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in this embodiment of the present disclosure.

FIG. 4 is a timing diagram of signals driving the pixel circuit of FIG. 3 . As shown in FIG. 3 , the working process of the pixel circuit 100 includes three stages, namely a first stage P1 , a second stage P2 and a third stage P3 .

The light-emitting reset control signal and the light-emitting control signal are the same signal, the voltage-stabilizing control signal and the scanning signal are the same signal, the voltage-stabilizing transistor T2 and the light-emitting reset transistor T4 are N-type transistors, the driving transistor T1, the driving reset transistor T3, the data writing Taking the input transistor T5 , the compensation transistor T6 , the first light emission control transistor T7 and the second light emission control transistor T8 as P-type transistors as an example, the working process of the pixel circuit in FIG. 4 will be described with reference to FIG. 3 .

As shown in FIG. 4, in the first stage P1, a low-level drive reset control signal RST, a high-level scan signal GA, a high-level light-emitting control signal EMS, a high-level voltage stabilization control signal STV and Low level data signal DA. As shown in FIG. 4 , the rising edge of the lighting control signal EMS is earlier than the starting point of the first stage P1 , that is, earlier than the rising edge of the voltage regulation control signal STV.

In the first phase P1, the gate of the driving reset transistor T3 receives the low level driving reset control signal RST, and the driving reset transistor T3 is turned on, thereby applying the driving reset voltage VINT1 to the first node N1. The gate of the voltage-stabilizing transistor T2 receives a high-level voltage-stabilizing control signal STV, and the voltage-stabilizing transistor T2 is turned on, thereby applying the driving reset voltage VINT1 at the first node N1 to the gate of the driving transistor T1 to The gate of the driving transistor T1 is reset, so that the driving transistor T1 is ready for the writing of the data of the second stage P2. In the embodiment of the present disclosure, the value of the driving reset voltage VINT1 may be set to be lower, eg, the voltage opposite to the first power supply voltage Vdd is larger, so that the gate of the driving transistor T1 and the The difference between the voltages of the first poles is larger, thereby speeding up the process of data writing and compensation in the second stage. It should be noted that the influence of the driving reset voltage VINT1 on the driving transistor T1 tends to be saturated as the driving reset voltage VINT1 increases in the reverse direction. The process of data writing and compensation will be described in the second stage P2 below. In addition, in the first stage P1, the voltage of one pole of the storage capacitor C is the first power supply voltage Vdd, and the voltage of the other pole is the drive reset voltage VINT1, and the storage capacitor C is charged. In the embodiment of the present disclosure, considering the influence of the driving reset voltage VINT1 on data writing and compensation and circuit energy consumption related to the charging of the storage capacitor C and the hardware limitation of the power supply, the value range of the driving reset voltage VINT1 may be − 1 to -5V, for example, -3V. This can shorten the time required for data writing and compensation while keeping the power consumption of the circuit low, thereby improving the compensation effect during a fixed time period, such as the second stage P2, and thus improving the display effect.

In the first stage P1, the gate of the light-emitting reset transistor T4 receives a high-level light-emitting control signal EMS, and the light-emitting reset transistor T4 is turned on, so that the light-emitting reset voltage VINT2 is applied to the anode of the OLED to reset the anode of the OLED to So that the OLED does not emit light before the third stage P3. In an embodiment of the present disclosure, the value of the light emission reset voltage VINT2 is set such that the OLED is in a state where it is just not emitting light, ie, the OLED is forward biased to a near-on state. Specifically, when the range of the second power supply voltage Vss is 0 to -6V, the value range of the light-emitting reset voltage VINT2 may be -2 to -6V, for example, equal to the second power supply voltage Vss, which is 0 to -6V . This can reduce the charging time of the PN junction before the OLED is turned on, and reduce the response time of the OLED to the light-emitting signal. When the required brightness is consistent, the probability of OLED brightness differences is reduced. Therefore, the uniformity of brightness can be improved, and the low frequency Flicker and the low grayscale Mura can be reduced.

In addition, in the first stage P1, the gate of the data writing transistor T5 receives the high-level scan signal GA, and the data writing transistor T5 is turned off. The gate of the compensation transistor T6 receives the high-level scan signal GA, and the compensation transistor T6 is turned off. The gate of the first light-emitting control transistor T7 receives the high-level light-emitting control signal EMS, and the first light-emitting control transistor T7 is turned off. The gate of the second light-emitting control transistor T8 receives the high-level light-emitting control signal EMS, and the second light-emitting control transistor T8 is turned off.

In the second stage P2, a high-level drive reset control signal RST, a low-level scan signal GA, a high-level light-emitting control signal EMS, a high-level voltage regulation control signal STV and a high-level data signal are input. DA.

In the second stage P2, the gate of the data writing transistor T5 receives the low-level scan signal GA, and the data writing transistor T5 is turned on, thereby writing the high-level data signal DA to the first pole of the driving transistor T1, That is, the first terminal F of the driving circuit 110 . The gate of the compensation transistor T6 receives the low-level scan signal GA, and the compensation transistor T3 is turned on, thereby writing the high-level data signal DA of the first terminal F into the first node N1. The gate of the voltage-stabilizing transistor T2 receives the high-level voltage-stabilizing control signal STV, and the voltage-stabilizing transistor T2 is turned on, thereby writing the high-level data signal DA of the first node N1 into the gate of the driving transistor T1, that is, the driving circuit The control terminal G of 110. Since the data writing transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage-stabilizing transistor T2 are all turned on, the data signal DA passes through the data-writing transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage-stabilizing transistor T2 to the storage capacitor C Charging is performed again, that is, the gate of the driving transistor T1 is charged, that is, the control terminal G is charged, so the voltage of the gate of the driving transistor T1 is gradually increased.

It can be understood that, in the second stage P2, since the data writing transistor T5 is turned on, the voltage of the first terminal F remains at Vda. Meanwhile, according to the characteristics of the driving transistor T1, when the voltage of the control terminal G rises to Vda+Vth, the driving transistor T1 is turned off, and the charging process ends. Here, Vda represents the voltage of the data signal DA, and Vth represents the threshold voltage of the driving transistor T1. Since the driving transistor T1 is described by taking a P-type transistor as an example in this embodiment, the threshold voltage Vth here may be a negative value.

After the second stage P2, the voltage of the gate of the driving transistor T1 is Vda+Vth, that is to say, the voltage information of the data signal DA and the threshold voltage Vth is stored in the storage capacitor C for subsequent use in the third stage P3 , the threshold voltage of the driving transistor T1 is compensated.

In addition, in the second phase P2, the gate of the drive reset transistor T3 receives the drive reset control signal RST of a high level, and the drive reset transistor T3 is turned off. The gate of the light-emitting reset transistor T4 receives a high-level light-emitting reset control signal EMS, and the light-emitting reset transistor T4 is turned off. The gate of the first light-emitting control transistor T7 receives the high-level light-emitting control signal EMS, and the first light-emitting control transistor T7 is turned off; the gate of the second light-emitting control transistor T8 receives the high-level light-emitting control signal EMS, and the second light-emitting control transistor T8 receives the high-level light-emitting control signal EMS. The light emission control transistor T8 is turned off.

In the third stage P3, a high-level drive reset control signal RST, a high-level scan signal GA, a low-level light-emitting control signal EMS, a low-level voltage regulation control signal STV and a low-level data signal are input. DA. As shown in FIG. 4 , in an embodiment of the present disclosure, the low-level lighting control signal EMS may be a low-level active pulse width modulation signal. As shown in Figure 4, the falling edge of the lighting control signal EMS is later than the end point of the second phase P1, that is, later than the falling edge of the voltage regulation control signal STV.

In the third stage P3, the gate of the first light-emitting control transistor T7 receives the light-emitting control signal EMS. According to an embodiment of the present disclosure, the lighting control signal EMS may be pulse width modulated. When the light emission control signal EMS is at a low level, the first light emission control transistor T7 is turned on, so that the first power supply voltage Vdd is applied to the first terminal F. As shown in FIG. The gate of the second light emission control transistor T8 receives the light emission control signal EMS. When the light emission control signal EMS is at a low level, the second light emission control transistor T8 is turned on, thereby applying the driving current generated by the driving transistor T1 to the anode of the OLED.

In addition, in the third stage P3, the gate of the voltage-stabilizing transistor T2 receives the voltage-stabilizing control signal Stv of a low level, and the voltage-stabilizing transistor T2 is turned off. As described above, the active layer of the voltage-stabilizing transistor T2 includes an oxide semiconductor material, and the leakage current thereof is 10-16 to 10-19A. Compared with the single-gate low-temperature polysilicon transistor and the double-gate low-temperature polysilicon transistor, the leakage current is smaller, so that the electrical leakage of the memory circuit can be further reduced to improve the uniformity of brightness.

In addition, in the third stage P3, the gate of the light-emitting reset transistor T4 receives the light-emitting control signal EMS. When the light emission control signal EMS is at a high level, the light emission reset transistor T4 is turned on. A light emission reset voltage is supplied to the anode of the OLED to reset the anode of the OLED. In the case where the light emission control signal EMS is a pulse width modulation signal, this can enable the anode of the OLED to be reset before each light emission of the OLED under the control of the light emission control signal EMS, thereby further improving the uniformity of brightness .

In addition, the gate of the drive reset transistor T3 receives the drive reset control signal RST of a high level, and the drive reset transistor T3 is turned off. The gate of the data writing transistor T5 receives the high-level scan signal GA, and the data writing transistor T5 is turned off. The gate of the compensation transistor T6 receives the high-level scan signal GA, and the compensation transistor T6 is turned off.

It is easy to understand that in the third stage P3, since the first light-emitting control transistor T7 is turned on, the voltage of the first terminal F is the first power supply voltage Vdd, and the voltage of the control terminal G is Vda+Vth, so the driving transistor T1 is also turned on. .

In the third stage P3, the anode and cathode of the OLED are respectively connected to the first power supply voltage Vdd (high voltage) and the second power supply voltage Vss (low voltage), so as to emit light driven by the driving current generated by the driving transistor T1.

Based on the saturation current formula of the driving transistor T1, the driving current ID for driving the OLED to emit light can be obtained according to the following formula:

ID=K(VGS-Vth) ²

=K[(Vda+Vth-Vdd)-Vth] ²

=K(Vda-Vdd) ²

In the above formula, Vth represents the threshold voltage of the driving transistor T1, VGS represents the voltage between the gate and the source of the driving transistor T1, and K is a constant. It can be seen from the above formula that the driving current ID flowing through the OLED is no longer related to the threshold voltage Vth of the driving transistor T1, but is only related to the voltage Vda of the data signal DA, so that the threshold voltage Vth of the driving transistor T1 can be adjusted. The compensation solves the problem of threshold voltage drift of the driving transistor T1 caused by the process and long-term operation, and eliminates its influence on the driving current ID, thereby improving the display effect.

For example, K in the above formula can be expressed as:

K=0.5nCox(W/L),

Wherein, n is the electron mobility of the driving transistor T1, Cox is the gate unit capacitance of the driving transistor T1, W is the channel width of the driving transistor T1, and L is the channel length of the driving transistor T1.

Alternatively, in some embodiments of the present disclosure, the light emission reset control signal RST, the compensation control signal COM, and the scan signal GA may be the same signal. The voltage-stabilizing transistor T2 may be an N-type transistor, while the driving transistor T1, the driving reset transistor T3, the light-emitting reset transistor T4, the data writing transistor T5, the compensation transistor T6, the first light-emitting control transistor T7 and the second light-emitting control transistor T8 are P type transistor. The difference from the working process of the pixel circuit in the above-mentioned embodiment is that, in the first stage P1, the light-emitting reset transistor T4 receives the high-level scanning signal GA, and the light-emitting reset transistor T4 is turned off. The light emission reset voltage VINT2 is not supplied to the anode of the light emitting device OLED, and thus the anode of the light emitting device OLED is not reset. In the second stage P2, the light-emitting reset transistor T4 receives the low-level scan signal GA, and the light-emitting reset transistor T4 is turned on. The light emission reset voltage VINT2 is supplied to the anode of the light emitting device OLED to reset the anode of the light emitting device OLED. The rest of the operation process of the pixel circuit in the first period P1, the second period P2 and the third period P3 is similar to the above-mentioned embodiment, and details are not repeated here.

In addition, it should be noted that the relationship between the drive reset control signal RST, the scan signal GA, the light emission control signal EMS, the voltage regulation control signal STV, and the data signal DA and each stage is only illustrative. The durations of the high level or the low level of the driving reset control signal RST, the scan signal GA, the light emission control signal EMS, the voltage regulation control signal STV, and the data signal DA are only illustrative. For example, each high level duration of the lighting control signal EMS may be the same.

5-11 illustrate schematic plan views of layers in an array substrate according to embodiments of the present disclosure. A pixel circuit as shown in FIG. 3 is taken as an example for description. In the pixel circuit, the light-emitting reset control signal RST and the light-emitting control signal EMS are the same signal, the voltage-stabilizing control signal COM and the scanning signal GA are the same signal, and the voltage-stabilizing transistor T2 and the light-emitting reset transistor T4 are metal oxide transistors.

The following describes the positional relationship of each circuit in the pixel circuit on the substrate with reference to FIGS. 5 to 11 . Those skilled in the art will understand that the scales in FIGS. 5 to 11 are drawing scales in order to more clearly represent the positions of various parts, and should not be regarded as true scales of components. Those skilled in the art can select the size of each component based on actual requirements, which is not specifically limited in the present disclosure.

In an embodiment of the present disclosure, the array substrate includes the first active semiconductor layer 310 on the substrate 300 .

FIG. 5 shows a schematic plan view of the first active semiconductor layer 310 in the array substrate according to an embodiment of the present disclosure. In the exemplary embodiment of the present disclosure, the driving transistor T1, the driving reset transistor T3, the light-emitting reset transistor T4, the data writing transistor T5, the compensation transistor T6, the first light-emitting control transistor T7, and the second light-emitting control transistor in the pixel circuit T8 is a silicon transistor, such as a low temperature polysilicon transistor. In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 may be used to form the above-mentioned driving transistor T1, driving reset transistor T3, light-emitting reset transistor T4, data writing transistor T5, compensation transistor T6, and first light-emitting control transistor Active regions of T7 and the second light emission control transistor T8. In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 includes a channel region pattern and a doping region pattern of the transistor (ie, first and second source/drain regions of the transistor). In the embodiment of the present disclosure, the channel region pattern and the doped region pattern of each transistor are integrally provided.

It should be noted that, in FIG. 5 , a dotted frame is used to denote regions in the first active semiconductor layer 310 for source/drain regions and channel regions of respective transistors.

As shown in FIG. 5 , the first active semiconductor layer 310 sequentially includes a channel region T3-c of the driving reset transistor T3 and a channel region of the data writing transistor T5 along the Y direction (column direction) and the X direction (row direction) in sequence. T5-c, the channel region T6-c of the compensation transistor T6, the channel region T1-c of the driving transistor T1, the channel region T7-c of the first light emission control transistor T7, and the channel of the second light emission control transistor T8 District T8-c.

In an exemplary embodiment of the present disclosure, the first active semiconductor layer for the above-described transistor may include an integrally formed low temperature polysilicon layer. The source region and the drain region of each transistor may be conductive by doping or the like to realize electrical connection of each structure. That is, the first active semiconductor layer of the transistor is an overall pattern formed of p-silicon or n-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie, source region s and drain region d). ) and channel region pattern. The active layers of different transistors are separated by doping structures.

As shown in FIG. 5 , the first active semiconductor layer 310 further includes: a drain region T3-d of the driving reset transistor T3, a drain region T5-d of the data writing transistor T5, and a driving reset transistor along the Y direction and the X direction. The source region of T3 and the source region T3-s/T6-s of the compensation transistor T6, the source region T5-s of the data writing transistor T5, the source region of the driving transistor T1 and the source of the first light-emitting control transistor T7 The region T1-s/T7-s, the drain region of the compensation transistor T6 and the drain region of the driving transistor T1 and the drain region T6-d/T1-d/T8-d of the second light emission control transistor T8, the first light emission The drain region T7-d of the control transistor T7, and the source region T8-s of the second light-emitting control transistor T8.

In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 may be formed of a silicon semiconductor material such as amorphous silicon, polysilicon, or the like. The above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities. For example, the source and drain regions of the first light emission control transistor T7, the data writing transistor T5, the driving transistor T1, the compensation transistor T6, and the second light emission control transistor T8 are all regions doped with P-type impurities.

In an embodiment of the present disclosure, the array substrate further includes a first conductive layer 320 on a side of the first active semiconductor layer away from the substrate.

FIG. 6 is a schematic plan view of the first conductive layer 320 in the array substrate according to an embodiment of the present disclosure. As shown in FIG. 6 , the first conductive layer 320 includes a drive reset control signal line RSTL1 , a scan signal line GAL, a first pole C1 of the capacitor C, and a light emission control signal line EML sequentially arranged along the Y direction. In addition, the first conductive layer 320 further includes a drive reset control signal line RSTL1' for adjacent pixel circuits along the Y direction. The function of the drive reset control signal line RSTL1' of the adjacent pixel circuit to the adjacent pixel circuit is the same as that of the drive reset control signal line RSTL1 to the pixel circuit, and the description thereof will not be repeated below.

In the embodiment of the present disclosure, the lighting control signal line EML and the lighting control signal input terminal EM are configured to provide the lighting control signal input terminal EM with the lighting control signal EMS.

In the embodiment of the present disclosure, the scan signal line GAL is coupled to the scan signal input terminal Gate and the compensation control signal input terminal Com, and is configured to provide the scan signal GA to the scan signal input terminal Gate, and is configured to provide the compensation control signal The signal input terminal Com provides the compensation control signal COM.

In the embodiment of the present disclosure, the first electrode C1 of the capacitor C and the gate electrode T1-g of the driving transistor T1 have an integral structure.

In the embodiment of the present disclosure, the driving reset control signal line RSTL1 is coupled to the driving reset control signal input terminal Rst1 to provide the driving reset control signal RST to the driving reset control signal input terminal Rst1.

In an embodiment of the present disclosure, referring to FIGS. 5 and 6 , the orthographic projection of the reset control signal line RSTL1 on the substrate is driven to overlap the orthographic projection of the portion 311 of the first active semiconductor layer 310 on the substrate. It is the gate T3-g of the drive reset transistor T3 of the pixel circuit. The part where the orthographic projection of the scanning signal line GAL on the substrate overlaps with the orthographic projection of the part 311 of the first active semiconductor layer 310 on the substrate is the gate T6-g of the compensation transistor T6 and the data write in the pixel circuit, respectively. into the gate T5-g of the transistor T5. The part where the orthographic projection of the first electrode C1 of the capacitor C in the pixel circuit on the substrate overlaps with the orthographic projection of the part 311 of the first active semiconductor layer 310 on the substrate is the gate of the driving transistor T1 in the pixel circuit Pole T1-g. The portion where the orthographic projection of the light-emitting control signal line EML on the substrate overlaps with the orthographic projection of the portion 311 of the first active semiconductor layer 310 on the substrate is the gate T7- of the first light-emitting control transistor T7 in the pixel circuit, respectively. g and the gate T8-g of the second light emission control transistor T8.

In the embodiment of the present disclosure, as shown in FIG. 6 , in the Y direction, the gate T3-g of the reset transistor T3, the gate T6-g of the compensation transistor T6 and the gate T5-g of the data writing transistor T5 are driven g is located on the first side of the gate T1-g of the drive transistor T1. The gate T7-g of the first light emission control transistor T7 and the gate T8-g of the first light emission control transistor T8 are located on the second side of the gate T1-g of the driving transistor T1.

It should be noted that the first side and the second side of the gate T1-g of the driving transistor T1 are opposite sides of the gate T1-g of the driving transistor T1 in the Y direction. For example, as shown in FIG. 6, in the XY plane, the first side of the gate T1-g of the driving transistor T1 may be the upper side of the gate T1-g of the driving transistor T1. The second side of the gate T1-g of the driving transistor T1 may be the lower side of the gate T1-g of the driving transistor T1. In the description of the present disclosure, the "lower side" is, for example, the side of the array substrate for bonding ICs. For example, the lower side of the gate T1-g of the driving transistor T1 is the side of the gate T1-g of the driving transistor T1 close to the IC (not shown in the figure). The upper side is the opposite side to the lower side, eg the side of the gate T1-g of the drive transistor T1 away from the IC.

More specifically, the gate T3-g of the drive reset transistor T3 is located on the upper side of the gate T6-g of the compensation transistor T6 and the gate T5-g of the data writing transistor T5. The gate T3-g of the drive reset transistor T3 is aligned with the gate T1-g of the drive transistor T1 in the Y direction.

In the embodiment of the present disclosure, in the X direction, as shown in FIG. 6 , the gate T5-g of the data writing transistor T5 and the gate T7-g of the first light emission control transistor T7 are located at the gate of the driving transistor T1 Third side of T1-g. The gate T6-g of the compensation transistor T6 and the gate T8-g of the second light emission control transistor T8 are located on the fourth side of the gate T1-g of the driving transistor T1.

It should be noted that the third side and the fourth side of the gate T1-g of the driving transistor T1 are opposite sides of the gate T1-g of the driving transistor T1 in the X direction. For example, as shown in FIG. 6, in the XY plane, the third side of the gate T1-g of the driving transistor T1 may be the left side of the gate T1-g of the driving transistor T1. The fourth side of the gate T1-g of the driving transistor T1 may be the right side of the gate T1-g of the driving transistor T1.

More specifically, the gate T7-g of the first light emission control transistor T7 is on the left side of the gate T5-g of the data writing transistor T5. The gate T8-g of the second light emission control transistor T8 is located to the right of the gate T6-g of the compensation transistor T6.

It should be noted that the active regions of the transistor shown in FIG. 6 correspond to respective regions where the first conductive layer 320 and the first active semiconductor layer 310 overlap.

In an embodiment of the present disclosure, the array substrate further includes a second conductive layer located on a side of the first conductive layer away from the substrate and insulated from the first conductive layer.

FIG. 7 shows a schematic plan view of the second conductive layer 330 in the array substrate according to an embodiment of the present disclosure. As shown in FIG. 7 , the second conductive layer 330 includes a voltage regulation control signal line STVL, a second pole C2 of the capacitor, a first power supply voltage line VDL and a light emission reset control signal line RSTL2 arranged along the Y direction. In addition, the second conductive layer 330 further includes a light emission reset control signal line RSTL2' of adjacent pixel circuits along the Y direction. The function of the light emission reset control signal line RSTL2' of the adjacent pixel circuit to the adjacent pixel circuit is the same as that of the light emission reset control signal line RSTL2 to the pixel circuit, and the description thereof will not be repeated below.

In an embodiment of the present disclosure, referring to FIGS. 6 and 7 , the projections of the second pole C2 of the capacitor C and the first pole C1 of the capacitor C on the substrate at least partially overlap.

In the embodiment of the present disclosure, as shown in FIG. 7 , the first power supply voltage line VDL extends in the X direction and is integrally formed with the second pole C2 of the capacitor C. As shown in FIG. The first power supply voltage line is coupled to the first power supply voltage terminal VDD, and is configured to provide the first power supply voltage Vdd thereto. The voltage stabilization control signal line STVL is coupled to the voltage stabilization control signal input terminal Stv, and is configured to provide the voltage stabilization control signal STV thereto. The light-emitting reset control signal line RSTL2 is coupled to the light-emitting reset control signal input terminal Rst2, and is configured to provide the light-emitting reset control signal thereto. In the embodiment of the present disclosure, the light emission reset control signal and the scan signal EMS are the same signal.

In the embodiment of the present disclosure, as shown in FIG. 7 , in the Y direction, the voltage regulation control signal line STVL is located on the first side of the second pole C2 of the capacitor. The first power supply signal line VDL and the light emission reset control signal line RSTL2 are located on the second side of the second pole C2 of the capacitor. Similar to the description above with respect to the first and second sides of the gate T1-g of the drive transistor T1, the first and second sides of the second pole C2 of the capacitor are in the Y direction of the second pole C2 of the capacitor opposite sides. The first side of the second pole C2 of the capacitor is the upper side of the second pole C2 of the capacitor in the Y direction, and the second side of the second pole C2 of the capacitor is the lower side of the second pole C2 of the capacitor in the Y direction.

Specifically, in the Y direction, the voltage stabilization control signal line STVL is located on the upper side of the second pole C2 of the capacitor. The first power supply signal line VDL and the light emission reset control signal line RSTL2 are located on the lower side of the second pole C2 of the capacitor.

In the embodiment of the present disclosure, as shown in FIG. 7 , the voltage stabilization control signal line STVL is provided with the first gate T2 - g1 of the voltage stabilization transistor T2 . The light-emitting reset control signal line RSTL2 is provided with a first gate T4-g1 of the light-emitting reset transistor T4. The specific positions of the first gate T2-g1 of the voltage regulator transistor T2 and the first gate T4-g1 of the light-emitting reset transistor T4 will be described in detail below with reference to FIG. 8 .

Specifically, as shown in FIG. 7 , the first gate T2-g1 of the voltage-stabilizing transistor T2 is on the first side of the first gate T4-g1 of the light-emitting reset transistor T4 in the Y direction. Similar to the above description of the first side of the gate T1-g of the driving transistor T1, the first side of the first gate T4-g1 of the light-emitting reset transistor T4 is the first side of the first gate T4-g1 of the light-emitting reset transistor T4. upper side. That is, the first gate T2-g1 of the voltage-stabilizing transistor T2 is on the upper side of the first gate T4-g1 of the light-emitting reset transistor T4. In the X direction, the first gate T2-g1 of the voltage-stabilizing transistor T2 is at the same position as the first gate T4-g1 of the light-emitting reset transistor T4.

In an embodiment of the present disclosure, the array substrate further includes a second active semiconductor layer located on a side of the second conductive layer away from the substrate and insulated from the second conductive layer.

FIG. 8 shows a schematic plan view of the second active semiconductor layer 340 in the array substrate according to an embodiment of the present disclosure. As shown in FIG. 8 , the second active semiconductor layer 340 sequentially includes a first portion 341 and a second portion 342 in the Y direction, and the first portion 341 of the second active semiconductor layer 340 and the first portion 341 of the second active semiconductor layer 340 Two-part 342 alignment settings. In an exemplary embodiment of the present disclosure, the second active semiconductor layer 340 may be used to form the active layers of the voltage-stabilizing transistor T2 and the light-emitting reset transistor T4 described above. Specifically, the first portion 341 of the second active semiconductor layer 340 may be used to form the active layer of the zener transistor T2. The second portion 342 of the second semiconductor layer 340 may be used to form the active layer of the voltage regulator transistor T7. In an exemplary embodiment of the present disclosure, similar to the first active semiconductor layer 310 , the second active semiconductor layer 340 includes a channel pattern and a doping region pattern of the transistor (ie, the first source/drain regions and the doped region of the transistor). second source/drain region).

In FIG. 8 , dotted boxes are used to illustrate regions in the second active semiconductor layer 340 for source/drain regions and channel regions of respective transistors.

As shown in FIG. 8 , the first part 341 of the second active semiconductor layer 340 sequentially includes the source region T2-s of the voltage-stabilizing transistor T2, the channel region T2-c of the voltage-stabilizing transistor T2 and the voltage-stabilizing transistor T2 along the Y direction. the drain region T2-d. The second portion 342 of the second active semiconductor layer 340 sequentially includes a source region T4-s of the light-emitting reset transistor T4, a channel region T4-c of the light-emitting reset transistor T4, and a drain region T4 of the light-emitting reset transistor T4 in the Y direction -d.

In the embodiment of the present disclosure, referring to FIG. 7 and FIG. 8 , the overlapping part of the orthographic projection of the voltage regulation control signal line STVL on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the voltage regulation The first gate T2-g1 of the transistor T2. The channel region T8-c of the voltage-stabilizing transistor T2 completely overlaps with the projection of the first gate T2-g1 of the voltage-stabilizing transistor T2 on the substrate. The overlapping portion of the orthographic projection of the light emitting control signal line RSTL2 on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the first gate T4 - g1 of the light emitting reset transistor T4 . The channel region T4-c of the light-emitting reset transistor T4 completely overlaps with the projection of the first gate T4-g1 of the light-emitting reset transistor T4 on the substrate.

In an exemplary embodiment of the present disclosure, the second active semiconductor layer 340 may be formed of an oxide semiconductor material, eg, indium gallium zinc oxide IGZO. The above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities. For example, both the source region and the drain region of the voltage regulator transistor T2 and the light-emitting reset transistor T4 are regions doped with N-type impurities.

In an embodiment of the present disclosure, the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated from the second active semiconductor layer.

FIG. 9 shows a schematic plan view of the third conductive layer 350 in the array substrate according to an embodiment of the present disclosure. As shown in FIG. 9 , the third conductive layer 350 includes a voltage regulation control signal line STVL, a light emission reset control signal line RSTL2, and a light emission reset voltage line VINL2. In addition, the third conductive layer 350 further includes a light-emitting reset control signal line RSTL2' and a light-emitting reset voltage line VINL2' of adjacent pixel circuits along the Y direction. The light-emitting reset control signal line RSTL2' and the light-emitting reset voltage line VINL2' of the adjacent pixel circuit have the same effect on the adjacent pixel circuit as the light-emitting reset control signal line RSTL2 and the light-emitting reset voltage line VINL2 have the same effect on the pixel circuit, and will not be repeated below. Repeat it.

Specifically, as shown in FIG. 9 , the voltage stabilization control signal line STVL, the light emission reset control signal line RSTL2, and the light emission reset voltage line VINL2 are sequentially arranged in the Y direction.

In the embodiment of the present disclosure, as shown in FIG. 9 , the voltage stabilization control signal line STVL is provided with the second gate T2 - g2 of the voltage stabilization transistor T2 . The light-emitting reset control signal line RSTL2 is provided with a second gate T4-g2 of the light-emitting reset transistor T4. Specifically, the overlapping portion of the orthographic projection of the voltage stabilization control signal line STVL on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the second gate T2-g2 of the voltage stabilization transistor T2. The overlapping portion of the orthographic projection of the light-emitting reset control signal line RSTL2 on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the second gate T4-g2 of the light-emitting reset transistor T4.

Similar to the first gate T2-g1 of the voltage-stabilizing transistor T2 and the first gate T4-g1 of the light-emitting reset transistor T4 shown in FIG. 7, as shown in FIG. 9, the second gate of the voltage-stabilizing transistor T2 in the Y direction is The gate T2-g2 is on the first side of the second gate T4-g2 of the light-emitting reset transistor T4. The first side of the second gate T4-g2 of the light-emitting reset transistor T4 is the upper side of the second gate T4-g2 of the light-emitting reset transistor T4. That is, the second gate T2-g2 of the voltage-stabilizing transistor T2 is on the upper side of the second gate T4-g2 of the light-emitting reset transistor T4. In the X direction, the second gate T2-g2 of the voltage-stabilizing transistor T2 is at the same position as the second gate T4-g2 of the light-emitting reset transistor T4.

In the embodiment of the present disclosure, referring to FIGS. 7 , 8 and 9 , the second gate T2-g2 of the voltage-stabilizing transistor T2, the channel region T2-c of the voltage-stabilizing transistor T2 and the first gate of the voltage-stabilizing transistor T2 The projection of the gate T2-g1 on the substrate completely overlaps. The projections of the second gate T4-g2 of the light-emitting reset transistor T4, the channel region T4-c of the light-emitting reset transistor T4 and the first gate T4-g1 of the light-emitting reset transistor T4 on the substrate completely overlap.

It should be noted that, in the embodiments of the present disclosure, an insulating layer or a dielectric layer is further provided between adjacent active semiconductor layers and conductive layers or between adjacent conductive layers. Specifically, between the first active semiconductor layer 310 and the first conductive layer 320 , between the first conductive layer 320 and the second conductive layer 330 , and between the second conductive layer 330 and the second active semiconductor layer 340 between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360 (which will be described in detail below with reference to FIG. 12), and between the fourth conductive layer Between the layer 360 and the fifth conductive layer 370 (which will be described in detail below with reference to FIG. 11 ), an insulating layer or a dielectric layer (which will be described in detail below with reference to the cross-sectional view) is respectively provided.

It should be noted that the via holes described below are via holes simultaneously penetrating through insulating layers or dielectric layers provided between adjacent active semiconductor layers and conductive layers or between adjacent conductive layers. Specifically, the via holes penetrate simultaneously between the first active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, and between the second conductive layer 330 and the second conductive layer 330. between the source semiconductor layer 340, between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360, and between the fourth conductive layer 360 and the fifth conductive layer Vias of each insulating layer or dielectric layer between layers 370 .

In the drawings of the present disclosure, white circles are used to indicate regions corresponding to vias. Referring to FIG. 9 , the light-emitting reset voltage line VINL2 is coupled to the second active semiconductor layer 340 through the via hole 3501 to form the first electrode T4-1 of the light-emitting reset transistor T4. Specifically, referring to FIGS. 8 and 9 , the light emitting reset voltage line VINL2 in FIG. 9 overlaps with the projection on the substrate of the drain region T7 - d of the light emitting reset transistor T4 of the second portion 342 in FIG. 8 . The light emitting reset voltage line VINL2 is coupled to the drain region T4 - d of the light emitting reset transistor T4 through the via hole 3501 .

In an embodiment of the present disclosure, the array substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate and insulated from the third conductive layer.

FIG. 10 shows a schematic plan view of the fourth conductive layer 360 in the array substrate according to an embodiment of the present disclosure. As shown in FIG. 10 , the fourth conductive layer 360 includes a first connection part 361 , a second connection part 362 , a third connection part 363 , a fourth connection part 364 , a fifth connection part 365 , a sixth connection part 366 , and a seventh connection part 366 . The connection part 367 and the eighth connection part 368 . In addition, the fourth conductive layer 360 further includes a ninth connection portion 369 for adjacent pixel circuits along the Y direction. The ninth connection part 369 and the via hole 3691 thereon may serve as the first connection part 361 of the adjacent pixel circuit and the via hole 3611 thereon. The specific connection manner and function thereof are similar to the first connection portion 361 in the pixel circuit and the via hole 3611 thereon, which will not be repeated below. For patterning needs, the first connection parts 361 of adjacent pixel circuits and the via holes 3611 thereon are arranged as above.

In the embodiment of the present disclosure, the second connection part 362 , the third connection part 363 , the fourth connection part 364 , the fifth connection part 365 , the sixth connection part 366 , the seventh connection part 367 , and the eighth connection part 368 is provided on the second side of the first connection portion 361 . Similar to the second side of the gate T1 - g of the driving transistor T1 , in the XY coordinate system, the second side of the first connection portion 361 is the lower side of the first connection portion 361 . That is, the second connection part 362, the third connection part 363, the fourth connection part 364, the fifth connection part 365, the sixth connection part 366, the seventh connection part 367, and the eighth connection part 368 are provided at the first connection part the lower side of the portion 361 . The third connection portion 363 and the sixth connection portion 366 are sequentially arranged along the Y direction. The second connection portion 362 , the fourth connection portion 364 , the fifth connection portion 365 , the seventh connection portion 367 , and the eighth connection portion 368 are sequentially arranged along the Y direction. The second connection part 362 , the fourth connection part 364 , the fifth connection part 365 , the seventh connection part 367 , and the eighth connection part 368 are on the third side of the third connection part 363 and the sixth connection part 366 . Similar to the third side of the gate T1-g of the above-mentioned driving transistor T1, in the XY plane, the third side of the third connection part 363 and the sixth connection part 366 is the third connection part 363 and the sixth connection part 366. Right. That is, the second connection part 362 , the fourth connection part 364 , the fifth connection part 365 , the seventh connection part 367 , and the eighth connection part 368 are on the right side of the third connection part 363 and the sixth connection part 366 .

The first connection portion 361 is coupled to the first active semiconductor layer 310 through the via hole 3611 . Specifically, the first connection portion 361 is coupled to the drain region T3-d of the driving reset transistor T3 via the via hole 3611, and forms the first electrode T3-1 of the driving reset transistor T3. The first connection portion 361 serves as the driving reset voltage line VINL1.

The second connection portion 362 is coupled to the third conductive layer 350 through the via hole 3621 . Specifically, the second connection portion 362 is coupled to the light-emitting reset voltage line VINL2 via the via hole 3621 .

The third connection portion 363 is coupled to the first active semiconductor layer 310 through the via hole 3631 . Specifically, the third connection portion 363 is coupled to the drain region T5-d of the data writing transistor T5 through the via hole 3631, forming the first electrode T5-1 of the data writing transistor T5.

The fourth connection portion 364 is coupled to the first active semiconductor layer 310 through the via hole 3641 . Specifically, the fourth connection portion 364 is coupled to the source region of the drive reset transistor T3 and the source region T3-s/T6-s of the compensation transistor T6 through the via hole 3641, forming the second electrode of the drive reset transistor T3 and the compensation The second pole T3-2/T6-2 of the transistor T6. The fourth connection portion 364 is coupled to the second active semiconductor layer 340 through the via hole 3642 . Specifically, the fourth connection portion 364 is coupled to the source region T2-s of the voltage-stabilizing transistor T2 via the via hole 3642 to form the second electrode T2-2 of the voltage-stabilizing transistor T2.

The fifth connection portion 365 is coupled to the third conductive layer 330 through the via hole 3651 . The fifth connection portion 365 is coupled to the second conductive layer 320 through the via hole 3652 . Specifically, the fifth connection portion 365 is coupled to the gate electrode T1 - g of the driving transistor T1 and the first electrode C1 of the capacitor C through the via hole 3652 . The fifth connection portion 365 is coupled to the second active semiconductor layer 340 through the via hole 3653 . Specifically, the fifth connection portion 365 is coupled to the drain region T2-d of the voltage-stabilizing transistor T2 through the via hole 3653, and forms the first electrode T2-1 of the voltage-stabilizing transistor T2.

The sixth connection portion 366 is coupled to the first active semiconductor layer 310 through the via hole 3662 . Specifically, the sixth connection portion 366 is coupled to the drain region T7-d of the first light-emitting control transistor T7 via the via hole 3662, and forms the first electrode T7-1 of the first light-emitting control transistor T7.

The seventh connection portion 367 is coupled to the first active semiconductor layer 310 through the via hole 3671 . Specifically, the seventh connection portion 367 is coupled to the source region T8-s of the second light-emitting control transistor T8 through the via hole 3671, and forms the second electrode T8-2 of the second light-emitting control transistor T8. The seventh connection portion 367 is coupled to the second active semiconductor layer 340 through the via hole 3672 . Specifically, the seventh connection portion 367 is coupled to the source region T4-s of the light-emitting reset transistor T4 through the via hole 3672, and forms the second electrode T4-2 of the light-emitting reset transistor T4.

The eighth connection portion 368 is coupled to the second active semiconductor layer 340 through the via hole 3681 . Specifically, the eighth connection portion 368 is coupled to the source region T4-d of the light-emitting reset transistor T4 through the via hole 3681, and forms the first electrode T4-1 of the light-emitting reset transistor T4. In addition, the eighth connection portion 368 and the via hole 3682 thereon may serve as the second connection portion 362 and the via hole 3621 thereon of the adjacent pixel circuits along the Y direction. The specific connection method and function thereof are similar to the second connection portion 362 in the pixel circuit and the via hole 3621 thereon, and are not repeated here. For patterning needs, the second connection parts 362 of adjacent pixel circuits and the via holes 3621 thereon are arranged as above.

In an embodiment of the present disclosure, the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated from the fourth conductive layer.

FIG. 11 shows a schematic plan view of the fifth conductive layer 370 in the array substrate according to an embodiment of the present disclosure. As shown in FIG. 11 , the fifth conductive layer includes a data signal line DAL, a first power supply voltage line VDL, and a second power supply voltage line VSL arranged along the row direction X. The data signal line DAL extends along the column direction Y, and is coupled to the third connection portion 363 of the fourth conductive layer 360 through the via hole 3711 . The first power supply voltage line VDL extends along the column direction Y, and is coupled to the third connection portion 363 of the fourth conductive layer 360 through the via hole 3721 . The second power supply voltage line VSL extends along the column direction Y, and is coupled to the seventh connection portion 367 of the fourth conductive layer 360 through the via hole 3731 . In an embodiment of the present disclosure, the distance over which the second power supply voltage line VSL extends in the column direction Y is smaller than that of the data signal line DAL and the first power supply voltage line VDL. The second power supply voltage line VSL may be used as a cathode of a light emitting device such as an OLED.

In the embodiment of the present disclosure, the first power supply voltage line VDL has a closed rectangular part 371 . 8 and 11 , the orthographic projection of the second side extending in the Y direction of the rectangular member 371 disposed along the row direction X on the substrate is the same as the orthographic projection on the substrate of the first portion 341 of the second active semiconductor layer 340 on the substrate. Projections overlap. This arrangement can isolate the second active semiconductor layer 340 from the encapsulation layer on the side of the fifth conductive layer 370 away from the substrate and adjacent to the fifth conductive layer 370, thereby preventing the hydrogen element in the encapsulation layer from causing the first The properties of oxide materials in the second active semiconductor layer 340, such as metal oxide materials, are unstable.

In an embodiment of the present disclosure, the orthographic projection of the second power supply voltage line VSL on the substrate overlaps the orthographic projection of the second portion 342 of the second active semiconductor layer 340 on the substrate. This arrangement of the second power supply voltage line VSL has a similar effect to the arrangement of the first power supply voltage line VDL described above. The conductive layer 370 is isolated from the encapsulation layer disposed adjacent to it, so as to prevent the hydrogen element in the encapsulation layer from destabilizing the performance of the oxide material in the second active semiconductor layer 340 .

FIG. 12 shows a pixel circuit including a stacked first active semiconductor layer, a first conductive layer, a second conductive layer, a second active semiconductor layer, a third conductive layer and a fourth conductive layer (thus an array substrate). ) schematic diagram of the floor plan. As shown in FIG. 12 , the plan layout diagram 380 includes a first active semiconductor layer 310 , a first conductive layer 320 , a second conductive layer 330 , a second active semiconductor layer 340 , a third conductive layer 350 , and a fourth conductive layer 360 and the fifth conductive layer 370 . For ease of viewing, FIG. 12 shows the gate T1-g of the driving transistor T1, the gate T2-g of the voltage-stabilizing transistor T2, the gate T3-g of the driving reset transistor T3, and the gate T4-g of the light-emitting reset transistor T4. g, the gate T5-g of the data writing transistor T5, the gate T6-g of the compensation transistor T6, the first plate C1 of the storage capacitor C, the gate T7-g of the first light emission control transistor T7 and the second light emission The gate T8-g of the control transistor T8. FIG. 12 also shows a stub A1A2 passing through the array substrate where the via hole 3651, the gate T6-g of the compensation transistor T6 and the gate T2-g of the voltage regulator transistor T2 are located. A sectional view taken along the section line A1A2 will be described below with reference to FIG. 13 .

FIG. 13 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A1A2 in FIG. 12 according to an embodiment of the present disclosure. As shown in FIG. 13 , and referring to FIGS. 5 to 12 , the array substrate 10 includes: a substrate 300 ; a first buffer layer 101 on the substrate 300 ; and a first active semiconductor layer 310 on the first buffer layer 101 . The cross-sectional view shows the channel region T6 - c of the compensation transistor T6 included in the first active semiconductor layer 310 .

In an embodiment of the present disclosure, as shown in FIG. 13 , the array substrate 10 further includes: a first gate insulating layer 102 covering the first buffer layer 101 and the first active semiconductor layer 310 ; and a first gate insulating layer 102 located on the first gate insulating layer The first conductive layer 320 on the side of the layer 102 remote from the substrate 300 . The cross section shows the scan signal line GAL included in the first conductive layer 320 . As shown in FIG. 13 , the orthographic projection of the scanning signal line GAL on the substrate 300 overlaps with the orthographic projection of the channel region T6 - c of the compensation transistor T6 included in the first active semiconductor layer 310 on the substrate 300 . is the gate T6-g of the compensation transistor T6.

In an embodiment of the present disclosure, as shown in FIG. 13 , the array substrate 10 further includes: a first interlayer insulating layer 103 located on the side of the first conductive layer 320 away from the substrate 300 ; the first interlayer insulating layer 103 The second conductive layer 330 on the side away from the substrate 300 . The cross-sectional view shows the voltage regulation control signal line STVL and one connection part 331 included in the second conductive layer. The voltage stabilization control signal line STVL includes the first gate T2-g1 of the voltage stabilization transistor T2.

In an embodiment of the present disclosure, as shown in FIG. 13 , the array substrate 10 further includes: a second interlayer insulating layer 104 located on the side of the second conductive layer 330 away from the substrate 300 ; covering the second interlayer insulating layer 104 the second buffer layer 105 ; and the second active semiconductor layer 340 located on the side of the second buffer layer 105 away from the substrate 300 . The cross-sectional view shows the orthographic projection of the voltage-stabilizing transistor T2 on the substrate 300 overlapping the orthographic projection of the first gate T2-g1 of the voltage-stabilizing transistor T2 on the voltage-stabilizing control signal line STVL on the substrate 300 Channel region T2-c.

In an embodiment of the present disclosure, as shown in FIG. 13 , the array substrate 10 further includes: a second gate insulating layer 106 covering the second active semiconductor layer 340 and the second buffer layer 105 ; The third conductive layer 350 on the side of 106 away from the substrate 300 . The cross-sectional view shows that the third conductive layer 350 includes the voltage regulation control signal line STVL. As shown in FIG. 13 , the orthographic projection of the voltage stabilization control signal line STVL on the substrate 300 is the same as the orthographic projection of the channel region T2-c of the voltage stabilization transistor T2 included in the second active semiconductor layer 320 on the substrate 300 The overlapping part is the second gate T2-g2 of the voltage regulator transistor T2.

In an embodiment of the present disclosure, as shown in FIG. 13 , the array substrate 10 further includes: a third interlayer insulating layer 107 covering the third conductive layer 350 and the second gate insulating layer 106 ; The fourth conductive layer 360 on the side of the layer 107 remote from the substrate 300 . Referring to FIG. 10 , the cross-sectional view shows the fifth connection portion 365 . The fifth connection portion 365 is coupled to the connection portion 331 on the second conductive layer 330 through the via hole 3651 .

In an embodiment of the present disclosure, as shown in FIG. 13 , the array substrate 10 further includes: a first flat layer 108 covering the fourth conductive layer 360 and the third interlayer insulating layer 107 ; The fifth conductive layer 370 on one side of the bottom 300 . The cross-sectional view shows the first power supply voltage line VDL.

In an embodiment of the present disclosure, as shown in FIG. 13 , the array substrate 10 further includes a second planarization layer 109 covering the fifth conductive layer 370 and the first planarization layer 108 .

FIG. 14 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A1A2 in FIG. 12 according to an embodiment of the present disclosure. In the embodiment of the present disclosure, as shown in FIG. 14 , the array substrate 10 further includes a blocking layer 400 located between the substrate 100 and the first buffer layer 101. On the one hand, when the substrate 300 is a light-transmitting substrate, the blocking layer 400 is configured to at least partially block the light incident from the side of the substrate 300 on which the pixel circuit is not provided to the active semiconductor layer of the transistor of the pixel circuit, in order to prevent photodegradation of the transistor. On the other hand, the blocking layer 400 is configured to block particles released from the substrate from entering the pixel circuit. The released particles can also degrade transistor performance if they enter the active semiconductor layer. In addition, in the case where the particles are charged particles, once embedded in the pixel circuit structure (eg, in the dielectric layer of the embedded circuit structure), it will also interfere with various signal voltages input to the pixel circuit, thereby affecting the display performance. For example, when the substrate 300 is a polyimide substrate, since the polyimide material always contains various impurity ions undesirably, during the thermal exposure process (eg, growth and During sputtering and evaporation of conductive layers such as metals), these impurity ions are released from the substrate 300 into the pixel circuit.

In embodiments of the present disclosure, the blocking layer 400 may not be biased (ie, suspended). In addition, a voltage bias can also be applied to the shielding layer 400 to further improve the shielding effect. According to an embodiment of the present disclosure, the voltage applied to the blocking layer may be a constant voltage. The voltage applied to the blocking layer may be selected from one of the following voltages: a first power supply voltage Vdd (anode voltage of the light emitting device), a second power supply voltage Vss (a cathode voltage of the light emitting device), a driving reset voltage VINT1 or other voltages. According to an embodiment of the present disclosure, the range of the voltage applied to the blocking layer includes one selected from the following ranges: -10V to +10V, -5V to +5V, -3V to +3V, -1V to +1V, or -0.5V～+0.5V. According to an embodiment of the present disclosure, the voltage applied to the blocking layer may be selected from one of the following voltages: -0.3V, -0.2V, 0V, 0.1V, 0.2V, 0.3V, or 10.1V. According to an embodiment of the present disclosure, the voltage applied to the shielding layer may be greater than the second power supply voltage Vss and less than the first power supply voltage Vdd; or, the voltage applied to the shielding layer may be greater than the driving reset voltage VINT1 and less than the first power supply voltage Vdd.

FIG. 15 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure. FIG. 15 shows a configuration of a shielding layer 400a. In this configuration, the blocking layer 400a completely covers the substrate 300 on the region of the array substrate 10 having the pixel unit (ie, the display region). The cross-sectional structure of FIG. 14 corresponds to this configuration. Through the display area of the complete array substrate, the shielding layer can achieve the best protection effect.

16 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure. FIG. 16 shows another configuration of the shielding layer 400b, wherein the shielding layer 400b does not completely cover the substrate 300 on the area of the array substrate 10 having the pixel unit (ie, the display area). In this configuration, the blocking layer 400b includes a first strip 401 extending in the row direction X and spaced apart from each other in the column direction Y and a second strip 402 extending in the column direction Y and spaced apart from each other in the row direction X. The first strip 401 and the second strip 402 have the same width (ie, a dimension perpendicular to the extending direction of the strips). In addition, the orthographic projection of the intersecting portion of the first strip 401 and the second strip 402 on the substrate 300 and the active region 3101 of the driving transistor T1 (ie, the trench of the first active semiconductor layer 310 constituting the driving transistor T1 The orthographic projections of the channel regions T1-c, portions of the source regions T1-s and the drain regions T1-d) on the substrate 300 at least partially overlap. Through this configuration, not only can the active region of the driving transistor T1, which is a key component of the pixel circuit, be fully protected, but also the undesired connection between the shielding layer 400b and the wiring on the array substrate 10 can be reduced while ensuring the continuity of the entire shielding layer 400b. overlap, thereby reducing unwanted parasitic effects such as parasitic capacitance.

17 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure. FIG. 17 shows another configuration of the shielding layer 400c, wherein, similar to the configuration of the shielding layer 400b of FIG. 16, the shielding layer 400c also does not completely cover the area (ie, the display area) of the array substrate 10 having the pixel unit. Substrate 300. In this configuration, the blocking layer 400b has a main body 410 in each subpixel, a first connection portion 420 for connecting the main body 410 in the row direction X, and a second connection portion 430 for connecting the main body 410 in the column direction Y. The dimension Sc1 of the first connection portion 420 along the column direction is smaller than the dimension Sb1 of the main body 410 along the column direction, and the dimension Sc2 of the second connection portion 430 along the row direction is smaller than the dimension Sb2 of the main body 410 along the row direction. It should be understood that in this disclosure, the term "dimension" is intended to mean the largest dimension of a component. With this configuration, undesired overlap between the shielding layer and the wiring in the array substrate can be further reduced, thereby suppressing potential parasitic effects.

In an embodiment of the present disclosure, the dimension Sc1 of the first connection part 420 in the column direction may be the same as the dimension Sc2 of the second connection part 430 in the row direction. In addition, the dimension Sc1 of the first connection part 420 in the column direction may be different from the dimension Sc2 of the second connection part 430 in the row direction. The dimension Sc1 of the first connection part 420 in the column direction may be smaller than the dimension Sc2 of the second connection part 430 in the row direction. The inventor found that the data line DAL of the pixel unit extending along the column direction Y (as shown in FIG. 11 ) is more sensitive to parasitic interference than the gate signal line (driving reset control) in the pixel circuit extending along the row direction X. The signal line RSTL1, the scanning signal line GAL, the light emission control signal line EML) and the like. Therefore, by appropriately reducing the dimension Sc1 of the first connection part 420 along the column direction and increasing the dimension Sc2 of the second connection part 430 along the row direction, the conductivity of the entire shielding layer can be ensured while reducing the influence of parasitic effects. When a voltage bias is applied to the barrier layer, it can be ensured that the bias voltage is uniform across the barrier layer.

18 shows a schematic plan layout of a pixel circuit including a stacked blocking layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. In the plan layout 381 shown in FIG. 18 , the shielding layer 401c has the configuration shown in FIG. 17 . The blocking layer 401c has a main body 411 in each sub-pixel, a first connection part 421 for connecting the main body 411 in the row direction, and a second connection part 431 for connecting the main body 410 in the column direction. The dimension Sc1 of the first connecting portion 421 in the column direction is smaller than the dimension Sb1 of the main body 410 in the column direction, and the dimension Sc2 of the second connecting portion 430 in the row direction is smaller than the dimension Sb2 of the main body 410 in the column direction. In the configuration, the body 411 is shaped and sized to not only at least partially overlap the active region 3101 of the driving transistor T1 in a direction perpendicular to the substrate, but also at least partially overlap the fifth connection portion 365 of the fourth conductive layer 360 . In an embodiment of the present disclosure, at least 10% of the area of the fifth connection portion overlaps with the main body 411 in a direction perpendicular to the substrate. For example, FIG. 18 only shows the case where the body 411 completely overlaps the active region 3101 of the driving transistor T1 and the fifth connection 365 of the fourth conductive layer 360 , which does not at least limit the scope of the present disclosure. Since the fifth connection portion 365 is connected to the gate of the driving transistor T1 , blocking the fifth connection portion 365 can effectively prevent the impact of charged particles on the gate voltage of the driving transistor, and ensure normal display of images.

Furthermore, with the configuration of the shielding layer shown in FIGS. 17 and 18 , the dimension (width) Sc2 in the row direction of the

second connection parts

430 and 431 may vary in the column direction. In an embodiment of the present disclosure, the width of a portion where the second connection portion overlaps the wiring extending in the row direction of the signal having a relatively high frequency may be larger than the width of the second connection portion and the signal having a relatively low frequency in the row direction The width of the portion where the extended wiring overlaps. The wiring extending in the row direction of the signal having a relatively high frequency includes, for example, the light emission control signal line EML, the scanning signal line GAL, and the like. The higher the signal frequency, the more pronounced the parasitic effect. Therefore, with this configuration, the limiting interference of the shielding layer to the high-frequency signal can be effectively reduced. Similarly, the width of the portion where the first connection portion overlaps the wiring extending in the column direction of the signal having a relatively high frequency may be larger than the width of the portion where the first connection portion overlaps the wiring extending in the column direction of the signal having a relatively low frequency. section width.

Furthermore, in an embodiment of the present disclosure, the width of the portion where the second connection portion overlaps the wiring extending in the row direction having the constant signal may be greater than the width of the portion where the second connection portion overlaps the wiring extending in the row direction having no constant signal. section width. The wiring extending in the row direction with a constant signal may include, for example, a light emitting reset voltage line VINL, a first power supply voltage line VDL, and the like. Similarly, the width of the portion where the first connection portion overlaps the wiring extending in the column direction having the constant signal may be greater than the width of the portion where the first connection portion overlaps the wiring extending in the column direction having no constant signal. FIG. 19 shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 19 , the display panel 700 may include the array substrate 20 according to any embodiment of the present disclosure or the array substrate including the pixel circuit 100 according to any embodiment of the present disclosure.

For example, the display panel 700 may further include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., for example, these components may use existing conventional components, which will not be described in detail here.

For example, the display panel 700 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like. In addition, the display panel 700 can be not only a flat panel, but also a curved panel, or even a spherical panel. For example, the display panel 700 may also have a touch function, that is, the display panel 700 may be a touch display panel.

Embodiments of the present disclosure also provide a display device including the display panel according to any embodiment of the present disclosure.

FIG. 20 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 20 , the display device 800 may include the display panel 700 according to any embodiment of the present disclosure.

The display device 800 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

FIG. 21 shows a pixel circuit, which is a 7T1C structure including 7 transistors and 1 capacitor. In the pixel circuit, the active layers of the transistors T1 and T2 include oxide semiconductor materials, and the transistors T1 and T2 may be N-type oxide transistors. The active layers of transistors T3-T7 include silicon semiconductor material, such as low temperature polysilicon.

FIG. 22 shows a shielding layer for the circuit shown in FIG. 21 . FIG. 26 shows the position of the shielding layer 0. In this embodiment, the shielding layer is located between the semiconductor layer of the active layer and the substrate and is at least insulated from the active semiconductor.

FIG. 23 shows the plan layout of each functional layer (semiconductor layer and conductive layer) of the pixel circuit including the light shielding layer. The oxide semiconductors of T1 and T2 are mirrored designs; the shielding layer shields the silicon semiconductor material. As shown in FIG. 23 , the overall plane layout of the pixel circuit including the light shielding layer is also a mirror design; in the embodiment of the present disclosure, the mirror design can also be, for example, the plane layout of the pixel circuit including the light shielding layer shown in FIG. 24 and FIG. 29 . Among them, as shown in Figure 23, Da is the access point of the data signal terminal Data[m] in Figure 21, Vinit_OLED is the access point of the initial signal terminal Vinit_OLED in Figure 21, N1 is the potential point of the node N1 in Figure 21, wherein, N1 is located in the first source-drain layer. N4 is the potential point of the node N4 in FIG. 21 , ELVDD is the potential point of the power supply terminal ELVDD in FIG. 21 , and ELVDD is located in the first source-drain layer. The occlusion layer meets at least one of the following conditions:

1. The main body of the shielding layer is covered with silicon semiconductor material, and the coverage area of the N1 node and the shielding layer is greater than 10%; to stabilize the N1 node;

2. The shielding layer does not overlap with the oxide channel, or the overlapping area is less than 90%, which alleviates the parasitic capacitance on the oxide layer;

3. The overlapping area between the shielding layer and the initialization signal line should be minimized to reduce the load on the initialization signal line. The layout is designed to avoid the arc-shaped line at the T7 position and only overlap the horizontal line. For example, if As shown in FIG. 29, the conductive portion 47 is bent and extended on the orthographic projection of the base substrate to reduce the overlap between the light shielding layer and the second initial signal line Vinit2; and

4. The initialization signal line can be narrowed at the overlapping position with the blocking layer, and the blocking layer can also be narrowed.

FIG. 24 shows a plan layout of a pixel circuit of an embodiment of the present disclosure. The connection lines of the shielding layer along the row and column directions should avoid scanning lines as much as possible to avoid parasitic effects. N1 in FIG. 24 is the potential point of the node N1 in FIG. 21 , wherein N1 is located in the first source-drain layer.

According to an embodiment of the present disclosure, the biasing of the blocking layer can be implemented in the following manner.

1. Extend to the periphery for constant potential connection. It can be electrically connected through a circle of signal lines in the periphery, or it may not be a circle. Signal access can be achieved. You can use gate1, gate2, SD1, SD2, one of the ITO layers or Multi-layered to achieve overlapping. This method is shown in Figure 25;

2. The electrical connection is realized in the AA area, but other signal connection holes need to be avoided;

Embodiment 3: If a VDD or Vint signal is used, a hole can be connected at the overlapping position of the VDD line and the Vint line.

In specific implementation, the SD1 and SD2 layers are source-drain electrode film layers, and the material may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or alloys, or molybdenum/titanium alloys or laminates, etc. , or can be a titanium/aluminum/titanium stack.

In specific implementation, the gate1 and gate2 layers are gate electrode film layers, which can be made of the same material and/or the same layer as the gate of the oxide transistor, for example, the material can be molybdenum, aluminum, copper, titanium, niobium, one of which Or alloys, or molybdenum/titanium alloys or laminates, etc. The potential loaded by the shielding layer can be the same potential loaded by the power supply line VDD (voltage source potential); it can also be the same potential loaded by the initialization signal line; it can also be the same potential loaded by the cathode (cathode potential VSS); it can also be other fixed potentials. Potential, for example, the range of the fixed potential is -10V ~ +10V, another example, the range of the fixed potential is -5V ~ +5V, another example, the range of the fixed potential is -3V ~ +3V, another example, the range of the fixed potential is -1V～+1V, another example, the range of the fixed potential is -0.5V～+0.5V, another example, the range of the fixed potential is 0V, another example, the range of the fixed potential is 0.1V, another example, the range of the fixed potential is The range is 10.1V, another example, the range of the fixed potential is 0.2V, another example, the range of the fixed potential is -0.2V, another example, the range of the fixed potential is 0.3V, another example, the range of the fixed potential is -0.3V .

Specifically, the potential loaded by the light shielding layer may be greater than the potential loaded by the cathode (cathode potential VSS) and less than the potential loaded by the power supply line VDD; or, the potential loaded by the light shielding layer may be greater than the potential loaded by the initialization signal line, and less than the power supply line VDD. loaded potential.

In specific implementation, the shielding layer may be an amorphous silicon material, or a metal material, or an oxide semiconductor material such as IGZO, or a polysilicon material, or a conductive semiconductor material.

As shown in FIG. 27 , it is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of the array substrate of the present disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole is connected to the first pole of the driving transistor T3, the gate is connected to the second gate driving signal terminal G2; the first pole of the fifth transistor T5 is connected to the first pole of the driving transistor T3. A power supply terminal VDD, the second pole is connected to the first pole of the driving transistor DT, the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first pole of the second transistor T2 is connected to the node N, and the second pole is connected to the node N. The pole is connected to the second pole of the driving transistor T3, the gate is connected to the first gate driving signal terminal G1; the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, and the second pole is connected to the first pole of the seventh transistor T7 pole, the gate is connected to the enable signal terminal EM, the second pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the gate is connected to the second reset signal terminal Re2; the first pole of the first transistor T1 is connected to the node N, The diode is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power terminal VDD and the node N. The pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power terminal VSS. The first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type metal oxide transistor has a smaller leakage current, so that the light-emitting stage can be avoided, and the node N passes through the first transistor T1 and the second transistor. T2 leakage. Meanwhile, the driving transistor T3, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be low temperature polysilicon transistors, and the low temperature polysilicon transistors have higher carrier mobility , which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.

As shown in FIG. 28 , it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 27 . Among them, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage T3, and a light-emitting stage t4. In the first reset stage t1 : the first reset signal terminal Re1 outputs a high level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4, the second transistor T2, and the data signal terminal Da output driving The signal is to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, and the seventh The transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6. Light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the driving transistor output current formula I=(μWCox/2L)(Vgs-Vth) ² , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current I=(μWCox/2L)(Vdata+Vth−Vdd−Vth) ² of the driving transistor in the pixel driving circuit of the present disclosure. The pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.

The array substrate may include a base substrate, a light shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a first source-drain layer, which are stacked in sequence. Floor. As shown in FIGS. 29-41 , FIG. 29 is a structural layout of an exemplary embodiment of the disclosed array substrate, FIG. 30 is a structural layout of the light shielding layer in FIG. 29 , and FIG. 31 is a structural layout of the first active layer in FIG. 29 Layout, FIG. 32 is the structural layout of the first gate layer in FIG. 29, FIG. 33 is the structural layout of the second gate layer in FIG. 29, FIG. 34 is the structural layout of the second active layer in FIG. 29, and FIG. 35 is the layout. FIG. 29 is the structural layout of the third gate layer, FIG. 36 is the structural layout of the first source and drain layer in FIG. 29 , FIG. 37 is the structural layout of the light shielding layer and the first active layer in FIG. 29 , and FIG. 38 is the structural layout of FIG. 29 The structure layout of the middle light shielding layer, the first active layer and the first gate layer, Fig. 39 is the structure layout of the light shielding layer, the first active layer, the first gate layer and the second gate layer in Fig. 29, Fig. 40 is the structural layout of the light-shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 29 , and FIG. 41 is the light-shielding layer, the first active layer, the second active layer in FIG. Structural layout of the first gate layer, the second gate layer, the second active layer, and the third gate layer.

As shown in FIGS. 29 , 30 , 37 , 38 , 39 , 40 and 41 , the light shielding layer may include a plurality of repeating units 0 and connecting portions 02 connected between the repeating units 0 . Wherein, the repeating unit 0 may include two light-shielding parts 01 symmetrically arranged along the dotted line A, wherein the dotted line A extends along the second direction Y. As shown in FIG. 30 , the light-shielding portion 01 may include a first light-shielding portion 011 , a second light-shielding portion 012 , a third light-shielding portion 013 , and a fourth light-shielding portion 014 . The second light shielding portion 012 and the third light shielding portion 013 may extend along the second direction Y in the orthographic projection of the base substrate, and the fourth light shielding portion 014 may extend along the first direction X in the orthographic projection of the base substrate. The second light-shielding portion 012 and the third light-shielding portion 013 may be connected to the two sides of the first light-shielding portion 011 in the second direction Y, respectively, and the second light-shielding portion 012 is orthographically projected on the base substrate and the third light-shielding portion 013 is on the backing The orthographic projection of the base substrate on the first direction X may be spaced apart by a preset distance. The fourth light shielding portion 014 may be located on one side of the first light shielding portion in the first direction X. In the same repeating unit 0, two first light-shielding portions 011 adjacent to each other in the first direction X are connected. In the two adjacent repeating units 0 in the first direction X, the two adjacent light-shielding portions 01 are connected by respective fourth light-shielding portions 014 . In the second direction Y, two adjacent shading parts 01 can be connected by connecting parts 02, wherein the connecting parts 02 can respectively connect the second shading parts 012 and the third shading parts 013 of the two shading parts 01, and the connecting parts 02 are in the The orthographic projection of the base substrate extends along the first direction X. The first direction X and the second direction Y may intersect, for example, the first direction X may be a row direction, and the second direction may be a column direction.

As shown in FIGS. 29 , 31 , 37 , 38 , 39 , 40 and 41 , the first active layer may include an active part 54 , an active part 53 , an active part 55 , and an active part 57 . The active part 54 can be used to form the channel region of the fourth transistor T4, the active part 53 can be used to form the channel region of the driving transistor T3, and the active part 55 can be used to form the channel of the fifth transistor T5 region, the active part 57 may be used to form the channel region of the seventh transistor T7. The first active layer may be formed of a polycrystalline silicon semiconductor material.

As shown in FIGS. 29 , 32 , 38 , 39 , 40 and 41 , the first gate layer may include a second gate driving signal line G2 , an enable signal line EM, a second reset signal line Re2 , and a conductive portion 11 . The orthographic projections of the second gate driving signal line G2, the enable signal line EM, and the second reset signal line Re2 on the base substrate may all extend along the first direction X. The second gate driving signal line G2 can be used to provide the second gate driving signal terminal in FIG. 27 , the enable signal line EM can be used to provide the enable signal terminal in FIG. 27 , and the second reset signal line Re2 Can be used to provide the second reset signal terminal in FIG. 27 . The orthographic projection of the second gate driving signal line G2 on the base substrate may cover the orthographic projection of the active portion 54 on the base substrate, and the partial structure of the second gate driving signal line G2 may be used to form the gate of the fourth transistor T4 . The orthographic projection of the enable signal line EM on the base substrate may cover the orthographic projection of the active portion 55 on the base substrate, and a part of the structure of the enable signal line EM may be used to form the gate of the fifth transistor T5. The orthographic projection of the second reset signal line Re2 on the base substrate covers the orthographic projection of the active portion 57 on the base substrate, and a partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the conductive part 11 on the base substrate can cover the orthographic projection of the active part 53 on the base substrate, the conductive part 11 can be used to form the gate of the driving transistor T3, and at the same time, the conductive part 11 can also form a part of the capacitor C. electrode. Wherein, the first active layer can be doped by using the first gate layer as a mask, so that the first active layer covered by the first gate layer forms a semiconductor structure, and the first active layer not covered by the first gate layer forms a semiconductor structure. Parts form conductor structures.

As shown in FIGS. 29 , 33 , 39 , 40 and 41 , the second gate layer may include a first initial signal line Vinit1 , a first reset signal line Re1 , a first gate driving signal line G1 , a conductive portion 21 , and a connecting portion twenty two. The orthographic projections of the first initial signal line Vinit1, the first reset signal line Re1, and the first gate driving signal line G1 on the base substrate may all extend along the first direction. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG. 27 , the first reset signal line Re1 can be used to provide the first reset signal terminal in FIG. 27 , and the first gate driving signal line G1 Can be used to provide the first gate drive signal terminal in FIG. 27 . The conductive portion 21 is used for the other electrode of the capacitor C. As shown in FIG. The conductive parts 21 adjacent to each other in the first direction X may be connected to each other through the connecting parts 22 , and through holes 211 may be formed on the conductive parts 21 .

As shown in FIGS. 29 , 34 , 40 and 41 , the second active layer may include an active portion 6 , and the active portion 6 may include an active portion 61 and an active portion 62 , wherein the active portion 61 may form the first active portion 61 . In the channel region of the transistor T1, the active portion 62 may form the channel region of the second transistor T2. As shown in FIG. 40 , the active part 6 is located on the side of the active part 61 away from the active part 62 and can be connected to the first initial signal line Vinit1 through the via hole 71 to connect the second pole of the first transistor T1 and the first Initial signal line Vinit1. Wherein, the second active layer may be formed of a metal oxide semiconductor material, for example, indium gallium zinc oxide.

As shown in FIGS. 29 , 35 and 41 , the third gate layer may include a gate line 3Re1 , a gate line 3G1 , and a gate line 3Re1 . The orthographic projection of the grid line 3Re1 on the base substrate may extend along the first direction, and the orthographic projection of the grid line 3Re1 on the base substrate at least partially overlaps with the orthographic projection of the first reset signal line Re1 on the base substrate. The gate line 3Re1 may be connected to the first reset signal line Re1 through at least one via hole, and the via hole may be located in a non-display area or a display area of the display panel. The orthographic projection of the gate line 3G1 on the base substrate may extend along the first direction, and the orthographic projection of the gate line 3G1 on the base substrate may at least partially overlap with the orthographic projection of the first gate driving signal line G1 on the base substrate. The gate line 3G1 may be connected to the first gate driving signal line G1 through at least one via hole, and the via hole may be located in a non-display area or a non-display area of the display panel. The second active layer can be formed by conducting conductorization using the third gate layer as a mask, that is, the second active layer covered by the third gate layer forms a semiconductor structure, and the part not covered by the third gate layer forms a semiconductor structure A conductor structure is formed.

As shown in FIGS. 29 and 36 , the first source-drain layer may include a conductive portion 41 , a conductive portion 42 , a conductive portion 43 , a conductive portion 44 , a conductive portion 45 , a conductive portion 46 , a conductive portion 47 , and a second initial signal line Vinit2 , The second initial signal line Vinit2 is connected to the conductive portion 47 for providing the second initial signal terminal in FIG. 27 . The orthographic projection of the second initial signal line Vinit2 on the base substrate may at least partially overlap with the orthographic projection of the first reset signal line Re1 on the base substrate. The conductive portion 41 can be connected to the active portion 6 through the via hole 72, and the first initial signal line Vinit1 can be connected to the via hole 73 to connect the second electrode of the first transistor T1 and the first initial signal line Vinit1. The conductive portion 41 can be further The contact efficiency between the active part 6 and the first initial signal line Vinit1 is increased. The conductive part 42 can be connected to the position of the active part 6 between the active part 61 and the active part 62 through the via hole 74 , and the conductive part 11 can be connected to the conductive part 11 through the via hole 75 to connect the first electrode of the first transistor T1 and the driving part. gate of transistor T3. The via hole 75 may penetrate through the through hole 211 on the conductive portion 21 , and the conductor filled in the via hole 75 is not electrically connected to the conductive portion 21 . The conductive part 43 can be connected to the connection part 22 through the via hole 76 , and the first active layer on the side of the active part 55 can be connected through the via hole 77 to connect the capacitor C and the first electrode of the fifth transistor T5 . The conductive part 44 can be connected to the first active layer between the active part 57 and the active part 56 through the via hole 78 to connect the second electrode of the sixth transistor T6, wherein the conductive part 44 can be used to connect the light emitting unit the anode. The conductive part 45 can be connected to the active part 6 on the side of the active part 62 away from the active part 61 through the via hole 710 , and the first active layer on the side of the active part 53 can be connected through the via hole 711 to connect the second transistor. The second pole of T2 and the second pole of the driving transistor T3. The conductive part 46 can be connected to the connection part 22 through the via hole 712 , and the conductive part 46 can also be connected to the power line for providing the first power signal terminal VDD in FIG. 27 . The conductive part 47 may be connected to the first active layer on one side of the active part 57 through the via hole 79 to connect the second initial signal line Vinit2 and the second electrode of the seventh transistor T7.

In this exemplary embodiment, as shown in FIGS. 29 and 39 , the orthographic projection of the fourth light shielding portion 014 on the base substrate at least partially overlaps with the orthographic projection of the connecting portion 22 on the base substrate. This arrangement can minimize the shielding effect of the fourth light shielding portion 014 on light, and increase the light transmittance of the array substrate.

In this exemplary embodiment, as shown in FIGS. 29 and 39 , the orthographic projection of the connection portion 02 on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate at least partially overlap. Similarly, this setting can be minimized as much as possible. The shielding effect of the small connecting portion 02 on light increases the light transmittance of the array substrate. In addition, since the first reset signal line Re1 is located in the second gate layer, and the first reset signal line Re1 has a large distance from the light shielding layer, the capacitive coupling effect of the connecting portion 02 on the first reset signal line Re1 is small. Compared with disposing the connecting portion 02 directly under the gate line in the first gate layer, this arrangement can reduce the capacitive coupling effect of the connecting portion 02 on the gate line.

As shown in FIGS. 29 , 33 and 39 , the second gate layer may further include a raised portion 23 , the raised portion 23 is connected to the first initial signal line Vinit1 , the raised portion 23 includes a side 231 , and the first initial signal line Vinit1 includes a side edge 232 connected to the side edge 231 , and the included angle between the orthographic projection of the side edge 231 on the base substrate and the side edge 232 on the base substrate is less than 180°. The orthographic projection of the protruding portion 23 on the base substrate and the orthographic projection of the second light shielding portion 012 on the base substrate at least partially overlap. The raised portion 23 can reduce the resistance of the first initial signal line Vinit1. In addition, the orthographic projection of the base substrate of the raised portion 23 and the orthographic projection of the second light shielding portion 012 on the base substrate at least partially overlap, so that the raised portion can be reduced as much as possible. 23. The shading effect on the array substrate. It should be understood that, in other exemplary embodiments, protruding portions with similar structures may also be provided on gates extending in other row directions. On the basis of not affecting the transmittance of the array substrate, the protruding portions may Reduce the resistance of the gate lines.

In this exemplary embodiment, the light-shielding layer may be a conductor structure, for example, the light-shielding layer may be located on a metal light-shielding layer, and the light-shielding layer may be connected to a stable voltage source, and the stable voltage source may be the first power signal terminal VDD, the first power supply signal terminal VDD in FIG. Any one of the power supply signal terminal VSS, the first initial signal terminal Vinit1, and the second initial signal terminal Vinti2. Wherein, the light shielding layer can be connected to the above-mentioned stable power supply in the non-display area or the display area of the array substrate. In addition, the above-mentioned stable voltage source can also be provided by other power sources. As shown in FIG. 29 , the orthographic projection of the conductive portion 42 on the base substrate and the orthographic projection of the third light-shielding portion 013 on the base substrate at least partially overlap. Since the third light-shielding portion 013 is connected to a stable power supply, the third light-shielding portion 013 is opposite to the conductive portion. 42 has a voltage stabilization effect. At the same time, since the conductive portion 42 is connected to the gate of the driving transistor T3 (the conductive portion 11 ), that is, the third light shielding portion 013 has a voltage-stabilizing effect on the gate of the driving transistor T3, this setting can reduce the voltage of the gate of the driving transistor T3 during the light-emitting stage. voltage fluctuations.

As shown in FIG. 29 , the orthographic projection of the first light-shielding portion 011 on the base substrate can cover the orthographic projection of the active portion 53 on the base substrate, and the first light-shielding portion 011 can shield the active portion 53 from light, thereby reducing the active portion 53 . The section 53 changes the output characteristics of the drive transistor T3 due to illumination. In addition, the orthographic projection of the first light shielding portion 011 on the base substrate can also cover the orthographic projection of the gate of the driving transistor T3 (conducting portion 11 ) on the base substrate, so that the first light shielding portion 011 can stabilize the gate of the driving transistor T3 Therefore, the voltage fluctuation of the gate of the driving transistor T3 in the light-emitting stage is reduced. As shown in FIG. 29 , the orthographic projection of the first light-shielding portion 011 on the base substrate may at least partially overlap with the orthographic projection of the conductive portion 42 on the base substrate, so that the first light-shielding portion 011 can further stabilize the gate of the driving transistor T3 pressure. The area of the driving transistor gate (conductive portion 11) and the conductive portion 42 covered by the light shielding layer may be greater than 50% of the total area of the conductive portion 42 of the conductive portion 11, for example, 60%-70%; 80%-90%, or between Value range, or cover all, etc.

In addition, the array substrate may further include a second source/drain layer and an anode layer, the second source/drain layer may be located on the side of the first source/drain layer away from the base substrate, and the anode layer may be located at the side of the second source/drain layer away from the base substrate side. The second source-drain layer may include data signal lines for providing the data signal terminals in FIG. 27 and power lines for providing the first power signal terminals. The orthographic projections of the data signal lines and the power lines on the base substrate may both extend along the second direction Y. The anode layer may form the anode of the light emitting cell.

In this exemplary embodiment, the array may basically further include a second source-drain layer, as shown in FIGS. 42 and 43 , FIG. 42 is a structural layout of an exemplary embodiment of an array substrate of the disclosure, and FIG. 43 is the The structural layout of the second source-drain layer. The second source and drain layer may include a data line Da and a power supply line VDD, and the orthographic projection of the data line Da and the power supply line VDD on the base substrate may extend along the second direction Y. The data line Da can be used to provide the data signal terminal in FIG. 27 , and the power line VDD can be used to provide the first power signal terminal in FIG. 27 . As shown in FIG. 42 , the power line VDD can be connected to the connection part 22 through the via hole 713 to connect the first power signal terminal and the capacitor C. As shown in FIG. The data line may be connected to the first active layer on one side of the active part 54 through the via hole 714 to connect the first electrode of the fourth transistor T4 and the data signal terminal. Wherein, the power supply line VDD may include an extension portion 91 and an extension portion 92 distributed along its extending direction, wherein the size of the extension portion 91 projected on the first direction X of the base substrate may be larger than that of the extension portion 92 on the normal projection of the base substrate. The dimension projected in the first direction X. The extension portion 91 can cover the channel regions of the first transistor and the second transistor by orthographic projection on the base substrate. On the one hand, this arrangement can shield and shield the transistors through the power line VDD; on the other hand, this arrangement can reduce the resistance of the power line VDD.

As shown in FIGS. 44 and 45 , FIG. 44 is a structural layout of an exemplary embodiment of the disclosed array substrate, and FIG. 45 is a structural layout of the second source and drain layers in FIG. 44 . The difference between the second source-drain layer shown in FIG. 45 and the second source-drain layer shown in FIG. 43 is that the extension part 91 not only covers the channel regions of the first transistor and the second transistor, but also covers the sixth transistor. T6 and the channel region of the drive transistor T3.

As shown in FIGS. 46 and 47 , both are schematic structural diagrams of the second initial signal line in another exemplary embodiment of the array substrate of the present disclosure. In other exemplary embodiments, the second initial signal line Vinit2 may be a parallel grid line or a broken line, which may be designed according to the voltage drop of the initialization signal line.

As shown in FIG. 48 , it is a partial cross-sectional view taken along the dotted line B in FIG. 42 . The array substrate may further include a first insulating layer 82, a second insulating layer 83, a third insulating layer 84, a fourth insulating layer 85, a sixth insulating layer 86, a dielectric layer 87, a passivation layer 88, and a first planarization layer 89. Among them, the base substrate 81, the light shielding layer, the first insulating layer 82, the first active layer, the second insulating layer 83, the first gate layer, the third insulating layer 84, the second gate layer, and the fourth insulating layer 85. The second active layer, the fifth insulating layer 86, the third gate layer, the dielectric layer 87, the first source and drain layers, the passivation layer 88, the first flat layer 89, and the second source and drain layers are stacked in sequence . The first insulating layer 82 includes at least one of a silicon oxide layer and a silicon nitride layer, and the thickness of the first insulating layer 82 may be 2500-3500 angstroms. The second insulating layer 83 may be a silicon oxide layer, and the thickness of the second insulating layer 83 may be 1000-2000 angstroms. The third insulating layer 84 may be an interlayer insulating layer or an interlayer dielectric layer, the third insulating layer 84 may be a silicon nitride layer, and the thickness may be 1000-2000 angstroms. The fourth insulating layer 85 may include a silicon oxide layer and a silicon nitride layer, wherein the thickness of the silicon oxide layer may be 3000-4000 angstroms, and the thickness of the silicon nitride may be 500-1000 angstroms. The fifth insulating layer 86 may be a silicon oxide layer, and the thickness may be 1000-1700 angstroms. The dielectric layer 87 may include a silicon oxide layer and a silicon nitride layer, the thickness of the silicon oxide layer may be 1500-2500 Å, and the thickness of the silicon nitride layer may be 2500-3500 Å. The side of the second source-drain layer away from the base substrate can also be provided with a second flat layer, the anode layer is located on the side of the second flat layer away from the base substrate, and the side of the anode layer away from the base substrate can also be provided with a light-emitting layer The unit layer, the light-emitting unit layer may include an electron injection layer, an organic light-emitting layer, a hole injection layer, and the like.

The display panels and display devices provided by the embodiments of the present disclosure have the same or similar beneficial effects as the array substrates provided by the foregoing embodiments of the present disclosure. Since the array substrates have been described in detail in the foregoing embodiments, they will not be repeated here.

The foregoing description of the embodiments has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit this application. Individual elements or features of a particular embodiment are generally not limited to the particular embodiment, but, where appropriate, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described . The same can also be changed in many ways. Such changes are not to be considered a departure from this application, and all such modifications are included within the scope of this application.

Claims

An array substrate, comprising:

substrate;

A plurality of sub-pixels arranged on the substrate and arranged in multiple rows and columns, at least one of the plurality of sub-pixels includes a pixel circuit, and each of the pixel circuits includes: a driving circuit, a voltage regulator circuit, a driving reset circuit and light-emitting reset circuit, wherein,

The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current to the light emitting device,

The voltage-stabilizing circuit is coupled to the control terminal, the first node and the voltage-stabilizing control signal input terminal of the driving circuit, and is configured to be under the control of the voltage-stabilizing control signal from the voltage-stabilizing control signal input terminal turning on the control terminal of the driving circuit with the first node,

The drive reset circuit is coupled to the drive reset control signal input terminal, the first node and the drive reset voltage terminal, and is configured to reset the circuit from the drive reset under the control of the drive reset control signal from the drive reset control signal input terminal the driving reset voltage of the voltage terminal is provided to the voltage regulator circuit to reset the control terminal of the driving circuit, and

The light-emitting reset circuit is coupled to the light-emitting reset control signal input terminal, the light-emitting device and the light-emitting reset voltage terminal, and is configured to convert the light-emitting reset voltage from the light-emitting reset voltage under the control of the light-emitting reset control signal from the light-emitting reset control signal input terminal The light-emitting reset voltage of the terminal is provided to the light-emitting device to reset the light-emitting device;

a drive reset voltage line coupled to the drive reset voltage terminal and configured to provide the drive reset voltage thereto; and

A light-emitting reset voltage line is coupled to the light-emitting reset voltage terminal and configured to provide the light-emitting reset voltage thereto.
The array substrate according to claim 1, wherein the driving circuit comprises a driving transistor, the voltage regulator circuit comprises a voltage regulator transistor, the driving reset circuit comprises a driving reset transistor, the light emitting reset circuit comprises a light emitting reset transistor,

Wherein, the first pole of the driving transistor is coupled to the first terminal of the driving circuit, the gate of the driving transistor is coupled to the control terminal of the driving circuit, and the first terminal of the driving transistor is coupled to the control terminal of the driving circuit. A diode is coupled to the first end of the driving circuit;

The first electrode of the voltage stabilizer transistor is coupled to the control terminal of the driving circuit, the second electrode of the voltage stabilizer transistor is coupled to the first node, and the gate of the voltage stabilizer transistor is coupled to the first node. coupled with the voltage stabilization control signal input end;

Wherein, the first pole of the drive reset transistor is coupled to the drive reset voltage terminal, the gate of the drive reset transistor is coupled to the drive reset control signal input terminal, and the second pole of the drive reset transistor coupled to the first node;

The first pole of the light-emitting reset transistor is coupled to the light-emitting reset voltage terminal, the gate of the light-emitting reset transistor is coupled to the light-emitting reset control signal input terminal, and the second pole of the light-emitting reset transistor is coupled to the light-emitting reset control signal input terminal. coupled to the first end of the light emitting device;

Wherein, the active layer of the voltage stabilizing transistor includes oxide semiconductor material, and the active layers of the driving transistor and the driving reset transistor include silicon semiconductor material.
The array substrate of claim 2, wherein the active layer of the light emitting reset transistor comprises the oxide semiconductor material.
The array substrate according to claim 3, further comprising:

a first active semiconductor layer on the substrate, comprising the silicon semiconductor material; and

A second active semiconductor layer located on the side of the first active semiconductor layer away from the substrate and insulated from the first active semiconductor layer includes the oxide semiconductor material.
The array substrate according to claim 4,

Wherein, the first active semiconductor layer includes the active layer of the driving transistor and the active layer of the driving reset transistor,

Wherein, the second active semiconductor layer includes a first part and a second part arranged along the column direction, the first part of the second active semiconductor includes the active layer of the voltage regulator transistor, the second The second portion of the active semiconductor includes an active layer of the light emitting reset transistor.
6. The array substrate of claim 5, wherein the first portion of the second active semiconductor and the second portion of the second active semiconductor are aligned in a column direction.
The array substrate according to claim 6, wherein the pixel circuit further comprises a data writing circuit, a compensation circuit, a storage circuit and a light emission control circuit, wherein,

The data writing circuit is coupled to a data signal input terminal, a scan signal input terminal, and the first terminal of the driving circuit, and is configured to write data from the scan signal input terminal under the control of the scan signal from the scan signal input terminal. The data signal of the data signal input terminal is provided to the first terminal of the driving circuit;

The compensation circuit is coupled to the second terminal of the driving circuit, the first node and the compensation control signal input terminal, and is configured to control the driving circuit according to the compensation control signal from the compensation control signal input terminal The circuit performs threshold compensation;

the storage circuit is coupled to a first power supply voltage terminal and the control terminal of the driving circuit, and is configured to store a voltage difference between the first power supply voltage terminal and the control terminal of the driving circuit; as well as

The lighting control circuit is coupled to the lighting control signal input terminal, the first power supply voltage terminal, the first terminal and the second terminal of the driving circuit, the lighting reset circuit, and the lighting device, and is is configured to apply a first power supply voltage from the first power supply voltage terminal to the driving circuit under the control of a lighting control signal from the lighting control signal input terminal, and apply a driving current generated by the driving circuit to the driving circuit the light-emitting device.
The array substrate according to claim 7, wherein the data writing circuit comprises a data writing transistor, the compensation circuit comprises a compensation transistor, the storage circuit comprises a storage capacitor, and the light emission control circuit comprises a first light emission control circuit transistor and a second light emission control transistor,

The first pole of the data writing transistor is coupled to the data signal input terminal, the gate of the data writing transistor is coupled to the scan signal input terminal, and the second pole of the data writing transistor is coupled to the scan signal input terminal. the pole is coupled to the first end of the drive circuit;

The first electrode of the compensation transistor is coupled to the second end of the driving circuit, the gate of the compensation transistor is coupled to the compensation control signal input end, and the second electrode of the compensation transistor is coupled to the input end of the compensation control signal. coupled to the first node;

Wherein, the first pole of the storage capacitor is coupled to the first power supply voltage terminal, the second pole of the storage capacitor is coupled to the control terminal of the driving circuit, and is configured to store the first power supply the voltage difference between the voltage terminal and the control terminal of the drive circuit;

The first electrode of the first light-emitting control transistor is coupled to the first power supply voltage terminal, the gate of the first light-emitting control transistor is coupled to the light-emitting control signal input end, and the first light-emitting control transistor is the second electrode of the control transistor is coupled to the first end of the driving circuit; and

The first electrode of the second light-emitting control transistor is coupled to the second end of the driving circuit, the gate of the second light-emitting control transistor is coupled to the light-emitting control signal input end, and the The second electrode of the second light-emitting control transistor is coupled to the first electrode of the light-emitting device.
9. The array substrate of claim 8, wherein the first active semiconductor layer comprises a combination of the data writing transistor, the compensation transistor, the first light emission control transistor and the second light emission control transistor source layer.
9. The array substrate of claim 9, wherein the light emission reset control signal and the light emission control signal are the same signal.
The array substrate of claim 9, wherein the scan signal and the compensation control signal are the same signal.
11. The array substrate of claim 11, further comprising between the first active semiconductor layer and the second active semiconductor layer and connected to the first active semiconductor layer and the second active semiconductor layer A first conductive layer insulated and isolated by the semiconductor layer, the first conductive layer includes a drive reset control signal line, a scan signal line, a gate electrode of the drive transistor, a first electrode of the storage capacitor, And the light-emitting control signal line,

Wherein, the drive reset control signal line is coupled to the drive reset control signal input terminal, and is configured to provide the drive reset control signal to it;

The scan signal line is coupled to the scan signal input terminal and the compensation control signal input terminal, is configured to provide the scan signal to the scan signal input terminal, and is configured to provide the compensation control signal to the scan signal input terminal. The signal input terminal provides the compensation control signal;

Wherein, the first pole of the storage capacitor and the gate of the driving transistor are integral structures; and

Wherein, the light-emitting control signal line and the light-emitting control signal input end are configured to provide the light-emitting control signal to the light-emitting control signal input end.
The array substrate according to claim 12,

Wherein, the overlapping portion of the orthographic projection of the driving reset control signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the driving reset transistor;

Wherein, the overlapping part of the orthographic projection of the scanning signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the compensation transistor and the data the gate of the write transistor; and

Wherein, the overlapping part of the orthographic projection of the light-emitting control signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the first light-emitting control transistor and the gate of the second light emission control transistor.
14. The array substrate of claim 13, further comprising between the first conductive layer and the second active semiconductor layer and insulated from the first conductive layer and the second active semiconductor layer The second conductive layer includes a voltage regulation control signal line arranged along the column direction, a second pole of the storage capacitor, a first power supply voltage line and a light-emitting reset control signal line,

Wherein, the voltage stabilization control signal line is coupled to the voltage stabilization control signal input terminal, and is configured to provide the voltage stabilization control signal to it;

wherein, the first power supply voltage line is coupled to the first power supply voltage terminal, and is configured to provide the first power supply voltage thereto;

Wherein, the second pole of the storage capacitor and the orthographic projection of the first pole of the storage capacitor on the substrate at least partially overlap;

wherein, the second pole of the storage capacitor is integrally formed with the first power supply voltage line; and

Wherein, the light-emitting reset control signal line is coupled to the light-emitting reset control signal input terminal, and is configured to provide the light-emitting reset control signal thereto.
The array substrate according to claim 14,

Wherein, the overlapping part of the orthographic projection of the voltage-stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first gate of the voltage-stabilizing transistor extremely; and

Wherein, the overlapping part of the orthographic projection of the light-emitting control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first gate of the light-emitting reset transistor .
16. The array substrate according to claim 15, further comprising a third conductive layer on a side of the second active semiconductor layer away from the substrate and insulated from the second active semiconductor layer, the first conductive layer The three conductive layers include the voltage regulation control signal line, the light emission reset control signal line, and the light emission reset voltage line arranged along the column direction.
The array substrate according to claim 16,

Wherein, the overlapping portion of the orthographic projection of the voltage-stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second gate of the voltage-stabilizing transistor pole;

Wherein, the overlapping part of the orthographic projection of the light-emitting reset control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second gate of the light-emitting reset transistor extremely; and

Wherein, the light-emitting reset voltage line is coupled to the second active semiconductor layer through a via hole to form a first electrode of the light-emitting reset transistor.
The array substrate according to claim 17, further comprising a fourth conductive layer located on a side of the third conductive layer away from the substrate and insulated from the third conductive layer, the fourth conductive layer comprising: a first connection part, a second connection part, a third connection part, a fourth connection part, a fifth connection part, a sixth connection part, a seventh connection part, and an eighth connection part,

Wherein, the first connection part is used as the driving reset voltage line;

Wherein, the first connection portion is coupled to the drain region of the drive reset transistor through a via hole, forming a first pole of the drive reset transistor;

wherein, the second connection portion is coupled to the light-emitting reset voltage line through a via hole;

Wherein, the third connection portion is coupled to the drain region of the data writing transistor through a via hole to form a first electrode of the data writing transistor;

Wherein, the fourth connection part is coupled to the source region of the driving reset transistor and the source region of the compensation transistor through a via hole, and forms the second electrode of the driving reset transistor and the source region of the compensation transistor, respectively. the second pole, the fourth connection part is coupled to the source region of the voltage regulator transistor through the via hole, and forms the second pole of the voltage regulator transistor;

Wherein, the fifth connection part is coupled to the gate of the driving transistor and the first electrode of the storage capacitor through a via hole, and the fifth connection part is connected to the drain region of the voltage regulator transistor via a via hole coupled to form the first pole of the voltage regulator transistor;

Wherein, the sixth connection portion is coupled to the drain region of the first light-emitting control transistor through a via hole, forming a first electrode of the first light-emitting control transistor;

Wherein, the seventh connection part is coupled to the source region of the second light-emitting control transistor through a via hole to form a second electrode of the second light-emitting control transistor, and the seventh connection part is connected to the source region of the second light-emitting control transistor via a via hole. the source region of the light-emitting reset transistor is coupled to form the second electrode of the light-emitting reset transistor; and

Wherein, the eighth connection part is coupled to the source region of the light-emitting reset transistor through a via hole, and forms a first electrode of the light-emitting reset transistor.
The array substrate according to claim 18, further comprising a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated from the fourth conductive layer, the fifth conductive layer comprising data signal lines, the first power supply voltage lines, and the second power supply voltage lines arranged in the row direction,

Wherein, the data signal line extends along the column direction, and is coupled with the third connection portion of the fourth conductive layer through a via hole;

wherein, the first power supply voltage line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer through a via hole; and

Wherein, the second power supply voltage line extends along the column direction, and is coupled to the seventh connection portion of the fourth conductive layer through a via hole.
A display panel comprising the array substrate according to any one of claims 1 to 19.
A display device comprising the display panel of claim 20.