JPWO2021205531A1 - - Google Patents

Info

Publication number
JPWO2021205531A1
JPWO2021205531A1 JP2022513733A JP2022513733A JPWO2021205531A1 JP WO2021205531 A1 JPWO2021205531 A1 JP WO2021205531A1 JP 2022513733 A JP2022513733 A JP 2022513733A JP 2022513733 A JP2022513733 A JP 2022513733A JP WO2021205531 A1 JPWO2021205531 A1 JP WO2021205531A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022513733A
Other versions
JP7444244B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021205531A1 publication Critical patent/JPWO2021205531A1/ja
Application granted granted Critical
Publication of JP7444244B2 publication Critical patent/JP7444244B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003—Changing the DC level
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
JP2022513733A 2020-04-07 2020-04-07 トラック・アンド・ホールド回路 Active JP7444244B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/015636 WO2021205531A1 (ja) 2020-04-07 2020-04-07 トラック・アンド・ホールド回路

Publications (2)

Publication Number Publication Date
JPWO2021205531A1 true JPWO2021205531A1 (ja) 2021-10-14
JP7444244B2 JP7444244B2 (ja) 2024-03-06

Family

ID=78022598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022513733A Active JP7444244B2 (ja) 2020-04-07 2020-04-07 トラック・アンド・ホールド回路

Country Status (3)

Country Link
US (1) US11824551B2 (ja)
JP (1) JP7444244B2 (ja)
WO (1) WO2021205531A1 (ja)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07294616A (ja) * 1994-04-27 1995-11-10 Hioki Ee Corp サンプリングクロック調整用の波形表示方法
US20050190089A1 (en) * 2004-02-27 2005-09-01 Dieter Draxelmayr Circuit arrangement for the delay adjustment of analog-to-digital converters operating in a temporally offset manner
JP2008011132A (ja) * 2006-06-29 2008-01-17 Nec Electronics Corp ９０度移相器
US20150333755A1 (en) * 2014-05-13 2015-11-19 Mediatek Inc. Sampling circuit for sampling signal input and related control method
US20170005640A1 (en) * 2015-07-03 2017-01-05 Rohde & Schwarz Gmbh & Co. Kg Delay line system, high frequency sampler, analog-to-digital converter and oscilloscope

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252251A (ja) * 1996-03-15 1997-09-22 Tera Tec:Kk 多相クロック信号発生回路およびアナログ・ディジタル変換器
JP2845819B2 (ja) * 1996-06-27 1999-01-13 日本電気アイシーマイコンシステム株式会社 サンプルホールド回路
JP5365635B2 (ja) * 2008-09-17 2013-12-11 日本電気株式会社 サンプルホールド回路およびその制御方法
EP2270985B1 (en) 2009-01-26 2012-10-03 Fujitsu Semiconductor Limited Sampling
US8487795B1 (en) 2012-04-18 2013-07-16 Lsi Corporation Time-interleaved track-and-hold circuit using distributed global sine-wave clock
JP2019161324A (ja) 2018-03-08 2019-09-19 日本電信電話株式会社 トラックアンドホールド回路
JP6830079B2 (ja) * 2018-03-30 2021-02-17 日本電信電話株式会社 トラック・アンド・ホールド回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07294616A (ja) * 1994-04-27 1995-11-10 Hioki Ee Corp サンプリングクロック調整用の波形表示方法
US20050190089A1 (en) * 2004-02-27 2005-09-01 Dieter Draxelmayr Circuit arrangement for the delay adjustment of analog-to-digital converters operating in a temporally offset manner
JP2008011132A (ja) * 2006-06-29 2008-01-17 Nec Electronics Corp ９０度移相器
US20150333755A1 (en) * 2014-05-13 2015-11-19 Mediatek Inc. Sampling circuit for sampling signal input and related control method
US20170005640A1 (en) * 2015-07-03 2017-01-05 Rohde & Schwarz Gmbh & Co. Kg Delay line system, high frequency sampler, analog-to-digital converter and oscilloscope

Also Published As

Publication number Publication date
WO2021205531A1 (ja) 2021-10-14
JP7444244B2 (ja) 2024-03-06
US11824551B2 (en) 2023-11-21
US20230155600A1 (en) 2023-05-18

Similar Documents

Publication Publication Date Title
BR112023005462A2 (ja)
BR112023012656A2 (ja)
BR112021014123A2 (ja)
BR112022024743A2 (ja)
BR102021018859A2 (ja)
BR112022009896A2 (ja)
BR102020022030A2 (ja)
BR112023011738A2 (ja)
BR112023016292A2 (ja)
BR112023011539A2 (ja)
BR112023011610A2 (ja)
BR112023008976A2 (ja)
BR112023009656A2 (ja)
BR112023006729A2 (ja)
BR102021020147A2 (ja)
BR102021018926A2 (ja)
BR102021018167A2 (ja)
BR102021014044A2 (ja)
BR102021014056A2 (ja)
BR102021013929A2 (ja)
BR112021017747A2 (ja)
BR102021012571A2 (ja)
BR102021012230A2 (ja)
BR102021012107A2 (ja)
BR102021012003A2 (ja)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220729

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230822

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231023

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240123

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240205

R150 Certificate of patent or registration of utility model

Ref document number: 7444244

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150