JPWO2021166906A1 - - Google Patents

Info

Publication number
JPWO2021166906A1
JPWO2021166906A1 JP2022501905A JP2022501905A JPWO2021166906A1 JP WO2021166906 A1 JPWO2021166906 A1 JP WO2021166906A1 JP 2022501905 A JP2022501905 A JP 2022501905A JP 2022501905 A JP2022501905 A JP 2022501905A JP WO2021166906 A1 JPWO2021166906 A1 JP WO2021166906A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022501905A
Other versions
JPWO2021166906A5 (ja
JP7332783B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Publication of JPWO2021166906A1 publication Critical patent/JPWO2021166906A1/ja
Publication of JPWO2021166906A5 publication Critical patent/JPWO2021166906A5/ja
Application granted granted Critical
Publication of JP7332783B2 publication Critical patent/JP7332783B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2022501905A 2020-02-21 2021-02-16 ＳｅｒＤｅｓインターフェース回路および制御装置 Active JP7332783B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020027946 2020-02-21
JP2020027946 2020-02-21
PCT/JP2021/005703 WO2021166906A1 (ja) 2020-02-21 2021-02-16 ＳｅｒＤｅｓインターフェース回路および制御装置

Publications (3)

Publication Number Publication Date
JPWO2021166906A1 true JPWO2021166906A1 (ja) 2021-08-26
JPWO2021166906A5 JPWO2021166906A5 (ja) 2022-10-19
JP7332783B2 JP7332783B2 (ja) 2023-08-23

Family

ID=77392267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022501905A Active JP7332783B2 (ja) 2020-02-21 2021-02-16 ＳｅｒＤｅｓインターフェース回路および制御装置

Country Status (5)

Country Link
US (1) US20230066398A1 (ja)
JP (1) JP7332783B2 (ja)
CN (1) CN115136497A (ja)
DE (1) DE112021001161T5 (ja)
WO (1) WO2021166906A1 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010535453A (ja) * 2007-08-02 2010-11-18 フェアチャイルド セミコンダクター コーポレイション シリアルストリームを介してｌｃｄ、カメラ、キーパッド、及びｇｐｉｏデータをインタリーブ、及び、直列化／非直列化する方法、及び回路
JP2018533791A (ja) * 2015-11-12 2018-11-15 クアルコム，インコーポレイテッド 高速シリアルバスを介した低速および高速パラレルビットストリームの通信

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100663362B1 (ko) * 2005-05-24 2007-01-02 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 라이트 및 리드방법
DE102006050362A1 (de) * 2006-10-25 2008-05-08 Qimonda Ag Synchronisationsvorrichtung und Verfahren zur Datensynchronisation
JP5883101B1 (ja) 2014-09-29 2016-03-09 ファナック株式会社 データ再生回路
US10366039B2 (en) * 2017-04-13 2019-07-30 Nxp B.V. USB link bridge

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010535453A (ja) * 2007-08-02 2010-11-18 フェアチャイルド セミコンダクター コーポレイション シリアルストリームを介してｌｃｄ、カメラ、キーパッド、及びｇｐｉｏデータをインタリーブ、及び、直列化／非直列化する方法、及び回路
JP2018533791A (ja) * 2015-11-12 2018-11-15 クアルコム，インコーポレイテッド 高速シリアルバスを介した低速および高速パラレルビットストリームの通信

Also Published As

Publication number Publication date
CN115136497A (zh) 2022-09-30
DE112021001161T5 (de) 2023-02-09
JP7332783B2 (ja) 2023-08-23
WO2021166906A1 (ja) 2021-08-26
US20230066398A1 (en) 2023-03-02

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