JPWO2021161496A1 - - Google Patents
Info
- Publication number
- JPWO2021161496A1 JPWO2021161496A1 JP2022500169A JP2022500169A JPWO2021161496A1 JP WO2021161496 A1 JPWO2021161496 A1 JP WO2021161496A1 JP 2022500169 A JP2022500169 A JP 2022500169A JP 2022500169 A JP2022500169 A JP 2022500169A JP WO2021161496 A1 JPWO2021161496 A1 JP WO2021161496A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/045—Combinations of networks
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/0464—Convolutional networks [CNN, ConvNet]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- Biophysics (AREA)
- Biomedical Technology (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Molecular Biology (AREA)
- Artificial Intelligence (AREA)
- Mathematical Physics (AREA)
- General Health & Medical Sciences (AREA)
- Evolutionary Computation (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- Neurology (AREA)
- Image Analysis (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2020/005733 WO2021161496A1 (ja) | 2020-02-14 | 2020-02-14 | 情報処理回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2021161496A1 true JPWO2021161496A1 (https=) | 2021-08-19 |
| JPWO2021161496A5 JPWO2021161496A5 (https=) | 2022-09-20 |
| JP7364026B2 JP7364026B2 (ja) | 2023-10-18 |
Family
ID=77292818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022500169A Active JP7364026B2 (ja) | 2020-02-14 | 2020-02-14 | 情報処理回路 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20230075457A1 (https=) |
| JP (1) | JP7364026B2 (https=) |
| WO (1) | WO2021161496A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7456501B2 (ja) * | 2020-05-26 | 2024-03-27 | 日本電気株式会社 | 情報処理回路および情報処理回路の設計方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019091440A (ja) * | 2017-11-15 | 2019-06-13 | パロ アルト リサーチ センター インコーポレイテッド | 敵対的ネットワークを使用した準教師あり条件付き生成モデリングのためのシステム及び方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6658033B2 (ja) * | 2016-02-05 | 2020-03-04 | 富士通株式会社 | 演算処理回路、および情報処理装置 |
| US11681923B2 (en) * | 2019-04-19 | 2023-06-20 | Samsung Electronics Co., Ltd. | Multi-model structures for classification and intent determination |
| US11568238B2 (en) * | 2019-06-28 | 2023-01-31 | Amazon Technologies, Inc. | Dynamic processing element array expansion |
-
2020
- 2020-02-14 JP JP2022500169A patent/JP7364026B2/ja active Active
- 2020-02-14 WO PCT/JP2020/005733 patent/WO2021161496A1/ja not_active Ceased
- 2020-02-14 US US17/796,329 patent/US20230075457A1/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019091440A (ja) * | 2017-11-15 | 2019-06-13 | パロ アルト リサーチ センター インコーポレイテッド | 敵対的ネットワークを使用した準教師あり条件付き生成モデリングのためのシステム及び方法 |
Non-Patent Citations (1)
| Title |
|---|
| ALHAMALI, ABDULRAHMAN ET AL.: "FPGA-Accelerated Hadoop Cluster for Deep Learning Computations", 2015 IEEE INTERNATIONAL CONFERENCE ON DATA MINING WORKSHOP, JPN6020015328, 4 February 2016 (2016-02-04), US, pages 565 - 574, ISSN: 0005100747 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021161496A1 (ja) | 2021-08-19 |
| JP7364026B2 (ja) | 2023-10-18 |
| US20230075457A1 (en) | 2023-03-09 |
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