JP7364026B2 - 情報処理回路 - Google Patents

情報処理回路 Download PDF

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Publication number
JP7364026B2
JP7364026B2 JP2022500169A JP2022500169A JP7364026B2 JP 7364026 B2 JP7364026 B2 JP 7364026B2 JP 2022500169 A JP2022500169 A JP 2022500169A JP 2022500169 A JP2022500169 A JP 2022500169A JP 7364026 B2 JP7364026 B2 JP 7364026B2
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information processing
processing circuit
circuit
fusion
calculation result
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Japanese (ja)
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JPWO2021161496A5 (https=
JPWO2021161496A1 (https=
Inventor
勝彦 高橋
崇 竹中
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NEC Corp
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NEC Corp
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/045Combinations of networks
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/0464Convolutional networks [CNN, ConvNet]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Biophysics (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Molecular Biology (AREA)
  • Artificial Intelligence (AREA)
  • Mathematical Physics (AREA)
  • General Health & Medical Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Neurology (AREA)
  • Image Analysis (AREA)
JP2022500169A 2020-02-14 2020-02-14 情報処理回路 Active JP7364026B2 (ja)

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PCT/JP2020/005733 WO2021161496A1 (ja) 2020-02-14 2020-02-14 情報処理回路

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JPWO2021161496A1 JPWO2021161496A1 (https=) 2021-08-19
JPWO2021161496A5 JPWO2021161496A5 (https=) 2022-09-20
JP7364026B2 true JP7364026B2 (ja) 2023-10-18

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JP (1) JP7364026B2 (https=)
WO (1) WO2021161496A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7456501B2 (ja) * 2020-05-26 2024-03-27 日本電気株式会社 情報処理回路および情報処理回路の設計方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019091440A (ja) 2017-11-15 2019-06-13 パロ アルト リサーチ センター インコーポレイテッド 敵対的ネットワークを使用した準教師あり条件付き生成モデリングのためのシステム及び方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6658033B2 (ja) * 2016-02-05 2020-03-04 富士通株式会社 演算処理回路、および情報処理装置
US11681923B2 (en) * 2019-04-19 2023-06-20 Samsung Electronics Co., Ltd. Multi-model structures for classification and intent determination
US11568238B2 (en) * 2019-06-28 2023-01-31 Amazon Technologies, Inc. Dynamic processing element array expansion

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019091440A (ja) 2017-11-15 2019-06-13 パロ アルト リサーチ センター インコーポレイテッド 敵対的ネットワークを使用した準教師あり条件付き生成モデリングのためのシステム及び方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ALHAMALI, Abdulrahman et al.,FPGA-Accelerated Hadoop Cluster for Deep Learning Computations,2015 IEEE International Conference on Data Mining Workshop,米国,IEEE [online],2016年02月04日,pp.565-574,Retrieved from the Internet: <URL: http://ieeexplore.ieee.org/abstract/document/7395718>

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JPWO2021161496A1 (https=) 2021-08-19
US20230075457A1 (en) 2023-03-09

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