JPWO2021146416A5 - - Google Patents
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- JPWO2021146416A5 JPWO2021146416A5 JP2022543053A JP2022543053A JPWO2021146416A5 JP WO2021146416 A5 JPWO2021146416 A5 JP WO2021146416A5 JP 2022543053 A JP2022543053 A JP 2022543053A JP 2022543053 A JP2022543053 A JP 2022543053A JP WO2021146416 A5 JPWO2021146416 A5 JP WO2021146416A5
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Claims (19)
第１の供給電圧と第２の供給電圧との間に結合される第１のトランジスタと、
前記第１の供給電圧と前記第２の供給電圧との間に結合される第２のトランジスタと、
を含み、
前記第１のトランジスタと前記第２のトランジスタとのゲート・ソース間電圧の差に比例する第１の電流を提供し、
前記第１の供給電圧における差と前記第１のトランジスタと前記第２のトランジスタとのゲート・ソース間電圧の差とに比例する第２の電流を提供し、
前記第１の供給電圧が閾値を交差することに応答して状態を変化させる電圧値を判定するために前記第１の電流を前記第２の電流と比較し、
前記第１の供給電圧が前記閾値を交差することに応答して前記第２の電流をクランプする、
ように構成される、電圧管理装置。 A voltage supervisor,
a first transistor coupled between a first supply voltage and a second supply voltage;
a second transistor coupled between the first supply voltage and the second supply voltage;
including;
providing a first current proportional to a difference in gate - source voltage between the first transistor and the second transistor;
providing a second current proportional to a difference in the first supply voltage and a difference in gate - to-source voltages of the first transistor and the second transistor;
comparing the first current to the second current to determine a voltage value that changes state in response to the first supply voltage crossing a threshold;
clamping the second current in response to the first supply voltage crossing the threshold;
A voltage management device configured as follows.
前記閾値を交差する前記第１の供給電圧に応答して前記第２の電流が前記第１の電流よりも大きい、電圧管理装置。 The voltage management device according to claim 1,
A voltage management device , wherein the second current is greater than the first current in response to the first supply voltage crossing the threshold.
前記第１のトランジスタと前記第２のトランジスタとが、前記第１のトランジスタと前記第２のトランジスタとのゲート・ソース間電圧の差の温度係数を低減するようなサイズとされる、電圧管理装置。 The voltage management device according to claim 1,
A voltage management device, wherein the first transistor and the second transistor are sized to reduce a temperature coefficient of a difference in gate - source voltage between the first transistor and the second transistor. .
前記第１のトランジスタのゲートが、前記第２のトランジスタのゲートに結合される、電圧管理装置。 The voltage management device according to claim 1,
A voltage management device, wherein a gate of the first transistor is coupled to a gate of the second transistor.
前記第２のトランジスタのドレインが電流ミラーに結合され、前記第２のトランジスタのソースが抵抗器に結合される、電圧管理装置。 The voltage management device according to claim 1,
A voltage management device, wherein a drain of the second transistor is coupled to a current mirror and a source of the second transistor is coupled to a resistor.
前記第１の供給電圧と抵抗器とに結合される第３のトランジスタであって、前記第２の電流を提供するように構成される、前記第３のトランジスタを更に含む、電圧管理装置。 The voltage management device according to claim 1,
A voltage management device further comprising a third transistor coupled to the first supply voltage and a resistor and configured to provide the second current.
前記第３のトランジスタが、前記第１の供給電圧が前記閾値を交差することに応答して前記第２の電流をクランプするように更に構成される、電圧管理装置。 The voltage management device according to claim 6 ,
The voltage management apparatus, wherein the third transistor is further configured to clamp the second current in response to the first supply voltage crossing the threshold.
電流ミラーを用いて前記第１の電流を提供するように更に構成される、電圧管理装置。 The voltage management device according to claim 1,
A voltage management device further configured to provide the first current using a current mirror.
第１及び第２の抵抗器であって、前記第１の抵抗器が前記第２のトランジスタに結合され、前記第１及び第２の抵抗器が前記閾値を判定するようなサイズとされる、前記第１及び第２の抵抗器を更に含む、電圧管理装置。 The voltage management device according to claim 1,
first and second resistors, the first resistor coupled to the second transistor, and sized such that the first and second resistors determine the threshold; A voltage management device further comprising the first and second resistors .
電流ミラーを有する基準電流生成器であって、前記電流ミラーが、第１のトランジスタと第２のトランジスタとのゲート・ソース間電圧の差に比例する第１の電流を提供するように構成される、前記基準電流ミラーと、
前記電流ミラーに接続されるゲートと、電力供給に結合されるように適合されるソースと、第１の抵抗器に結合されるドレインとを有する第３トランジスタであって、供給電圧における差と前記第１のトランジスタと前記第２のトランジスタとのゲート・ソース電圧の差とに比例する第２の電流を提供するように構成される、前記第３トランジスタと、
前記第３のトランジスタのゲートに結合されるゲートと、前記電力供給に結合されるように適合されるソースと、閾値を上回る前記供給電圧を示すドレイン電圧を有するドレインとを有する第４のトランジスタと、
前記第１の抵抗器の第２の端子に結合されるソースと、前記第１のトランジスタのゲートと前記第２のトランジスタのゲートとに結合されるゲートとを有する第５のトランジスタと、
を含む、電圧管理装置。 A voltage management device,
a reference current generator having a current mirror configured to provide a first current proportional to a difference in gate - to-source voltage of a first transistor and a second transistor; , the reference current mirror;
a third transistor having a gate connected to the current mirror, a source adapted to be coupled to a power supply, and a drain coupled to the first resistor; the third transistor configured to provide a second current proportional to a gate - source voltage difference between the first transistor and the second transistor;
a fourth transistor having a gate coupled to the gate of the third transistor, a source adapted to be coupled to the power supply, and a drain having a drain voltage indicative of the supply voltage above a threshold; ,
a fifth transistor having a source coupled to a second terminal of the first resistor and a gate coupled to a gate of the first transistor and a gate of the second transistor;
Voltage management equipment, including.
前記第３のトランジスタが、前記供給電圧が前記閾値を交差することに応答して前記第２の電流をクランプするように構成される、電圧管理装置。 The voltage management device according to claim 10 ,
A voltage management device, wherein the third transistor is configured to clamp the second current in response to the supply voltage crossing the threshold.
前記閾値が、前記第１の抵抗器の値と前記第２のトランジスタのソースに結合される第２の抵抗器の値とに少なくとも部分的に基づく、電圧管理装置。 The voltage management device according to claim 10 ,
A voltage management apparatus, wherein the threshold is based at least in part on a value of the first resistor and a second resistor coupled to a source of the second transistor.
前記第１のトランジスタと前記第２のトランジスタとが、前記第１のトランジスタと前記第２のトランジスタとのゲート・ソース間電圧の差の温度係数を低減するようなサイズとされる、電圧管理装置。 The voltage management device according to claim 10 ,
A voltage management device, wherein the first transistor and the second transistor are sized to reduce a temperature coefficient of a difference in gate - source voltage between the first transistor and the second transistor. .
基準電流生成器であって、
電流ミラーと、
制御端子を有する第１のトランジスタと、
前記第１のトランジスタの制御端子に結合される制御端子と、第１の電流端子とを有する第２のトランジスタと、
前記第２のトランジスタの第１の電流端子に結合される第１の抵抗器と、
を含む、前記基準電流生成器と、
前記第１の電流ミラーに結合される制御端子と、電力供給に結合されるように適合される第１の電流端子と、第２の抵抗器に結合される第２の電流端子とを有する第３のトランジスタと、
前記第３のトランジスタの制御端子に結合される制御端子と、前記電力供給に結合されるように適合される第１の電流端子と、第２の電流端子とを有する第４のトランジスタと、
前記第４のトランジスタの第２の電流端子に結合される第２の電流端子と、前記第２のトランジスタの制御端子に結合される制御端子と、第６のトランジスタに結合される第１の電流端子とを有する第５のトランジスタと、
を含む、システム。 A system,
A reference current generator,
current mirror;
a first transistor having a control terminal ;
a second transistor having a control terminal coupled to a control terminal of the first transistor and a first current terminal ;
a first resistor coupled to a first current terminal of the second transistor;
the reference current generator,
a control terminal coupled to the first current mirror; a first current terminal adapted to be coupled to a power supply; and a second current terminal coupled to a second resistor. 3 transistors and
a fourth transistor having a control terminal coupled to a control terminal of the third transistor, a first current terminal adapted to be coupled to the power supply , and a second current terminal ;
a second current terminal coupled to a second current terminal of the fourth transistor; a control terminal coupled to a control terminal of the second transistor; and a first current coupled to a sixth transistor. a fifth transistor having a terminal;
system, including.
前記第５のトランジスタの第１の電流端子に結合される第２の電流ミラーを更に含む、システム。 15. The system according to claim 14 ,
The system further includes a second current mirror coupled to the first current terminal of the fifth transistor.
前記第１のトランジスタの閾値電圧が前記第２のトランジスタの閾値電圧よりも大きい、システム。 15. The system according to claim 14 ,
The system wherein the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.
前記第１のトランジスタが、約５００ミリボルト未満の閾値電圧を有するｎチャネルトランジスタである、システム。 15. The system according to claim 14 ,
The system wherein the first transistor is an n-channel transistor having a threshold voltage of less than about 500 millivolts.
前記第２のトランジスタが、ｎチャネルネイティブトランジスタである、システム。 15. The system according to claim 14 ,
The system wherein the second transistor is an n-channel native transistor.
前記第１のトランジスタの第２の電流端子が前記第１の電流ミラーに結合され、前記第２のトランジスタの第２の電流端子が前記第１の電流ミラーに結合される、システム。 15. The system according to claim 14 ,
A second current terminal of the first transistor is coupled to the first current mirror, and a second current terminal of the second transistor is coupled to the first current mirror.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IN202041001565 | 2020-01-14 | ||
| IN202041001565 | 2020-01-14 | ||
| US17/148,196 | 2021-01-13 | ||
| US17/148,196 US11892864B2 (en) | 2020-01-14 | 2021-01-13 | Voltage supervisor with low quiescent current |
| PCT/US2021/013427 WO2021146416A1 (en) | 2020-01-14 | 2021-01-14 | Voltage supervisor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2023529041A JP2023529041A (en) | 2023-07-07 |
| JPWO2021146416A5 true JPWO2021146416A5 (en) | 2024-01-22 |
Family
ID=76763232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022543053A Pending JP2023529041A (en) | 2020-01-14 | 2021-01-14 | Voltage management device |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US11892864B2 (en) |
| EP (1) | EP4090980A4 (en) |
| JP (1) | JP2023529041A (en) |
| CN (1) | CN115023619A (en) |
| WO (1) | WO2021146416A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11630472B2 (en) * | 2020-12-15 | 2023-04-18 | Texas Instruments Incorporated | Mitigation of transient effects for wide load ranges |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3142542B2 (en) | 1990-06-13 | 2001-03-07 | 沖電気工業株式会社 | Voltage measurement circuit |
| KR100434176B1 (en) | 2001-11-30 | 2004-06-04 | 주식회사 하이닉스반도체 | Supply voltage level detector |
| US6972703B1 (en) * | 2004-12-16 | 2005-12-06 | Faraday Technology Corp. | Voltage detection circuit |
| US8076959B2 (en) * | 2009-10-28 | 2011-12-13 | O2 Micro, Inc | Circuits and methods for voltage detection |
| WO2013042285A1 (en) | 2011-09-22 | 2013-03-28 | パナソニック株式会社 | Voltage detecting circuit and voltage regulator apparatus provided with same |
| US10107841B2 (en) * | 2015-07-24 | 2018-10-23 | Texas Instruments Incorporated | Methods and apparatus for peak-voltage measurement of AC signals |
| US9601995B1 (en) * | 2016-05-03 | 2017-03-21 | Texas Instruments Incorporated | Low power radio frequency envelope detector |
| US10014851B2 (en) * | 2016-11-02 | 2018-07-03 | Texas Instruments Incorporated | Current sensing and control for a transistor power switch |
| US11208977B2 (en) | 2017-03-01 | 2021-12-28 | Hitachi Astemo, Ltd. | Ignition control device and reference voltage adjustment method of ignition control device |
| JP2018186457A (en) * | 2017-04-27 | 2018-11-22 | 富士通株式会社 | Amplifier circuit and optical module |
| US10707867B2 (en) * | 2017-10-27 | 2020-07-07 | Texas Instruments Incorporated | Bus driver with rise/fall time control |
| DE102018110292B4 (en) * | 2018-04-27 | 2019-12-19 | Infineon Technologies Ag | Rectifier device with clamp circuit |
| FR3096466B1 (en) * | 2019-05-20 | 2021-10-22 | St Microelectronics Rousset | Device comprising a starting circuit |
-
2021
- 2021-01-13 US US17/148,196 patent/US11892864B2/en active Active
- 2021-01-14 EP EP21741873.0A patent/EP4090980A4/en active Pending
- 2021-01-14 JP JP2022543053A patent/JP2023529041A/en active Pending
- 2021-01-14 WO PCT/US2021/013427 patent/WO2021146416A1/en unknown
- 2021-01-14 CN CN202180010848.0A patent/CN115023619A/en active Pending
-
2024
- 2024-01-04 US US18/403,965 patent/US20240134407A1/en active Pending
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