JPWO2020255656A5 - - Google Patents
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- Publication number
- JPWO2020255656A5 JPWO2020255656A5 JP2021527512A JP2021527512A JPWO2020255656A5 JP WO2020255656 A5 JPWO2020255656 A5 JP WO2020255656A5 JP 2021527512 A JP2021527512 A JP 2021527512A JP 2021527512 A JP2021527512 A JP 2021527512A JP WO2020255656 A5 JPWO2020255656 A5 JP WO2020255656A5
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- dimensional structure
- transistors
- node
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 40
- 230000000295 complement effect Effects 0.000 claims 2
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019115211 | 2019-06-21 | ||
| JP2019115211 | 2019-06-21 | ||
| PCT/JP2020/020978 WO2020255656A1 (ja) | 2019-06-21 | 2020-05-27 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2020255656A1 JPWO2020255656A1 (enExample) | 2020-12-24 |
| JPWO2020255656A5 true JPWO2020255656A5 (enExample) | 2022-03-16 |
| JP7590656B2 JP7590656B2 (ja) | 2024-11-27 |
Family
ID=74037253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021527512A Active JP7590656B2 (ja) | 2019-06-21 | 2020-05-27 | 半導体記憶装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12213298B2 (enExample) |
| JP (1) | JP7590656B2 (enExample) |
| WO (1) | WO2020255656A1 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7590655B2 (ja) * | 2019-06-21 | 2024-11-27 | 株式会社ソシオネクスト | 半導体記憶装置 |
| CN116250077B (zh) * | 2020-11-24 | 2025-08-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及半导体结构的形成方法 |
| US20240105617A1 (en) * | 2022-09-23 | 2024-03-28 | Apple Inc. | Vertical Transistors With Backside Power Delivery |
| WO2025062483A1 (ja) * | 2023-09-19 | 2025-03-27 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2665644B2 (ja) * | 1992-08-11 | 1997-10-22 | 三菱電機株式会社 | 半導体記憶装置 |
| US8625334B2 (en) * | 2011-12-16 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell |
| JP5726770B2 (ja) | 2012-01-12 | 2015-06-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP2014222740A (ja) | 2013-05-14 | 2014-11-27 | 株式会社東芝 | 半導体記憶装置 |
| US20160011584A1 (en) * | 2013-05-15 | 2016-01-14 | Mitsubishi Electric Corporation | Numerical-control machining-program creation device |
| WO2014184933A1 (ja) | 2013-05-16 | 2014-11-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Ｓｇｔを有する半導体装置の製造方法 |
| WO2020051144A1 (en) * | 2018-09-05 | 2020-03-12 | Tokyo Electron Limited | Architecture design and processes for manufacturing monolithically integrated 3d cmos logic and memory |
-
2020
- 2020-05-27 JP JP2021527512A patent/JP7590656B2/ja active Active
- 2020-05-27 WO PCT/JP2020/020978 patent/WO2020255656A1/ja not_active Ceased
-
2021
- 2021-12-20 US US17/556,910 patent/US12213298B2/en active Active
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