JPWO2020230665A1 - - Google Patents

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Publication number
JPWO2020230665A1
JPWO2020230665A1 JP2021519379A JP2021519379A JPWO2020230665A1 JP WO2020230665 A1 JPWO2020230665 A1 JP WO2020230665A1 JP 2021519379 A JP2021519379 A JP 2021519379A JP 2021519379 A JP2021519379 A JP 2021519379A JP WO2020230665 A1 JPWO2020230665 A1 JP WO2020230665A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021519379A
Other languages
Japanese (ja)
Other versions
JPWO2020230665A5 (https=
JP7560746B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2020230665A1 publication Critical patent/JPWO2020230665A1/ja
Publication of JPWO2020230665A5 publication Critical patent/JPWO2020230665A5/ja
Application granted granted Critical
Publication of JP7560746B2 publication Critical patent/JP7560746B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/27ROM only
    • H10B20/30ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/34Source electrode or drain electrode programmed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/27ROM only
    • H10B20/50ROM only having transistors on different levels, e.g. 3D ROM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
JP2021519379A 2019-05-13 2020-05-01 半導体記憶装置 Active JP7560746B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019090697 2019-05-13
JP2019090697 2019-05-13
PCT/JP2020/018392 WO2020230665A1 (ja) 2019-05-13 2020-05-01 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPWO2020230665A1 true JPWO2020230665A1 (https=) 2020-11-19
JPWO2020230665A5 JPWO2020230665A5 (https=) 2022-02-10
JP7560746B2 JP7560746B2 (ja) 2024-10-03

Family

ID=73290170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021519379A Active JP7560746B2 (ja) 2019-05-13 2020-05-01 半導体記憶装置

Country Status (3)

Country Link
US (3) US11881273B2 (https=)
JP (1) JP7560746B2 (https=)
WO (1) WO2020230665A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020230665A1 (ja) * 2019-05-13 2020-11-19 株式会社ソシオネクスト 半導体記憶装置
WO2023157724A1 (ja) * 2022-02-16 2023-08-24 株式会社ソシオネクスト 半導体記憶装置
WO2024018875A1 (ja) * 2022-07-21 2024-01-25 株式会社ソシオネクスト 半導体記憶装置
WO2026004616A1 (ja) * 2024-06-27 2026-01-02 株式会社ソシオネクスト 半導体記憶装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7715246B1 (en) * 2008-06-27 2010-05-11 Juhan Kim Mask ROM with light bit line architecture
JP2011258898A (ja) * 2010-06-11 2011-12-22 Toshiba Corp 半導体装置およびその製造方法
US20160329313A1 (en) * 2014-06-23 2016-11-10 Synopsys, Inc. Cells having transistors and interconnects including nanowires or 2d material strips
JP2018026565A (ja) * 2016-08-10 2018-02-15 東京エレクトロン株式会社 半導体素子のための拡張領域
US20180151576A1 (en) * 2016-11-28 2018-05-31 Samsung Electronics Co., Ltd. Semiconductor devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10335813B4 (de) * 2003-08-05 2009-02-12 Infineon Technologies Ag IC-Chip mit Nanowires
US8654592B2 (en) * 2007-06-12 2014-02-18 Micron Technology, Inc. Memory devices with isolation structures
JP4907563B2 (ja) * 2008-01-16 2012-03-28 パナソニック株式会社 半導体記憶装置
WO2020230665A1 (ja) * 2019-05-13 2020-11-19 株式会社ソシオネクスト 半導体記憶装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7715246B1 (en) * 2008-06-27 2010-05-11 Juhan Kim Mask ROM with light bit line architecture
JP2011258898A (ja) * 2010-06-11 2011-12-22 Toshiba Corp 半導体装置およびその製造方法
US20160329313A1 (en) * 2014-06-23 2016-11-10 Synopsys, Inc. Cells having transistors and interconnects including nanowires or 2d material strips
JP2018026565A (ja) * 2016-08-10 2018-02-15 東京エレクトロン株式会社 半導体素子のための拡張領域
US20180151576A1 (en) * 2016-11-28 2018-05-31 Samsung Electronics Co., Ltd. Semiconductor devices

Also Published As

Publication number Publication date
US12277980B2 (en) 2025-04-15
US20220130478A1 (en) 2022-04-28
US20250239316A1 (en) 2025-07-24
WO2020230665A1 (ja) 2020-11-19
US20240112746A1 (en) 2024-04-04
US11881273B2 (en) 2024-01-23
JP7560746B2 (ja) 2024-10-03

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