JPWO2020170970A1 - Fluorescent substrate, light emitting substrate, lighting device, manufacturing method of phosphor substrate and manufacturing method of light emitting substrate - Google Patents

Fluorescent substrate, light emitting substrate, lighting device, manufacturing method of phosphor substrate and manufacturing method of light emitting substrate Download PDF

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JPWO2020170970A1
JPWO2020170970A1 JP2021501942A JP2021501942A JPWO2020170970A1 JP WO2020170970 A1 JPWO2020170970 A1 JP WO2020170970A1 JP 2021501942 A JP2021501942 A JP 2021501942A JP 2021501942 A JP2021501942 A JP 2021501942A JP WO2020170970 A1 JPWO2020170970 A1 JP WO2020170970A1
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正宏 小西
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Denka Co Ltd
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Denki Kagaku Kogyo KK
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50Wavelength conversion elements
    • H01L33/505Wavelength conversion elements characterised by the shape, e.g. plate or foil
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21SNON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S2/00Systems of lighting devices, not provided for in main groups F21S4/00 - F21S10/00 or F21S19/00, e.g. of modular construction
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21SNON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S2/00Systems of lighting devices, not provided for in main groups F21S4/00 - F21S10/00 or F21S19/00, e.g. of modular construction
    • F21S2/005Systems of lighting devices, not provided for in main groups F21S4/00 - F21S10/00 or F21S19/00, e.g. of modular construction of modular construction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2115/00Light-generating elements of semiconductor light sources
    • F21Y2115/10Light-emitting diodes [LED]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
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    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0066Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

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Abstract

本発明の蛍光体基板は、一面に少なくとも1つの電子部品が搭載される回路基板であって、絶縁基板と、前記絶縁基板の一面に配置され、前記絶縁基板の厚み方向外側に向く平面を有し、前記平面の一部を前記少なくとも1つの電子部品と接合する少なくとも1つの接合面として接合される回路パターン層と、少なくとも前記平面における前記少なくとも1つの接合面以外の部分とされる少なくとも1つの非接合面に配置され、前記少なくとも1つの発光素子の発光を励起光としたときの発光ピーク波長が可視光領域にある蛍光体を含む蛍光体層と、を備え、前記蛍光体層は、積層構造とされている。The phosphor substrate of the present invention is a circuit substrate on which at least one electronic component is mounted on one surface, and has an insulating substrate and a flat surface arranged on one surface of the insulating substrate and facing outward in the thickness direction of the insulating substrate. A circuit pattern layer joined as at least one joining surface for joining a part of the plane to the at least one electronic component, and at least one portion other than the at least one joining surface in the plane. A phosphor layer including a phosphor having a emission peak wavelength in the visible light region when the emission of the at least one light emitting element is used as excitation light, which is arranged on a non-bonded surface, is provided, and the phosphor layer is laminated. It is said to be a structure.

Description

本発明は、蛍光体基板、発光基板、照明装置、蛍光体基板の製造方法及び発光基板の製造方法に関する。 The present invention relates to a phosphor substrate, a light emitting substrate, a lighting device, a method for manufacturing a phosphor substrate, and a method for manufacturing a light emitting substrate.

特許文献1には、発光素子(LED素子)が搭載された基板を備えるLED照明器具が開示されている。このLED照明器具は、基板の表面に反射材を設けて、発光効率を向上させている。また、特許文献1に開示されている構成の場合、反射材を利用してLED照明器具が発光する光を発光素子が発光する光と異なる発光色の光に調整することができない。 Patent Document 1 discloses an LED lighting fixture including a substrate on which a light emitting element (LED element) is mounted. In this LED lighting fixture, a reflective material is provided on the surface of the substrate to improve the luminous efficiency. Further, in the case of the configuration disclosed in Patent Document 1, it is not possible to adjust the light emitted by the LED lighting fixture to the light having a different emission color from the light emitted by the light emitting element by using the reflective material.

中国特許公開106163113号公報Chinese Patent Publication No. 106163113

ところで、本願の発明者は、基板上に蛍光体層を備えることにより、発光素子が発光する光と異なる発光色の光に調整できることを見出した。また、特許文献1の発光素子が搭載された基板にはそもそも蛍光体層が備えられていないことから、特許文献1には蛍光体層を備える蛍光体基板、発光基板及びその製造方法について一切の開示がない。 By the way, the inventor of the present application has found that by providing a phosphor layer on a substrate, it is possible to adjust the light to emit light having a different emission color from the light emitted by the light emitting element. Further, since the substrate on which the light emitting element of Patent Document 1 is mounted is not provided with the phosphor layer in the first place, Patent Document 1 describes the phosphor substrate provided with the phosphor layer, the light emitting substrate, and the manufacturing method thereof. There is no disclosure.

本発明は、多層構造の蛍光体層を備える蛍光体基板の提供を目的とする。 An object of the present invention is to provide a fluorescent material substrate provided with a fluorescent material layer having a multilayer structure.

本発明の第1態様の蛍光体基板は、一面に少なくとも1つの発光素子が搭載される蛍光体基板であって、絶縁基板と、前記絶縁基板の一面に配置され、前記絶縁基板の厚み方向外側に向く平面を有し、前記平面の一部を前記少なくとも1つの電子部品と接合する少なくとも1つの接合面として接合される回路パターン層と、少なくとも前記平面における前記少なくとも1つの接合面以外の部分とされる少なくとも1つの非接合面に配置され、前記少なくとも1つの発光素子の発光を励起光としたときの発光ピーク波長が可視光領域にある蛍光体を含む蛍光体層と、を備え、前記蛍光体層は、積層構造とされている。 The fluorescent substrate of the first aspect of the present invention is a fluorescent substrate on which at least one light emitting element is mounted on one surface, and is arranged on one surface of the insulating substrate and the insulating substrate, and is outside in the thickness direction of the insulating substrate. A circuit pattern layer having a plane facing toward the surface and being joined as at least one joining surface for joining a part of the plane to the at least one electronic component, and at least a portion of the plane other than the at least one joining surface. The fluorescence is provided with a phosphor layer including a phosphor which is arranged on at least one non-junction surface and whose emission peak wavelength is in the visible light region when the emission of the at least one light emitting element is used as excitation light. The body layer has a laminated structure.

本発明の第2態様の蛍光体基板は、第1態様の蛍光体基板であって、前記少なくとも1つの発光素子は、複数の発光素子とされ、前記少なくとも1つの接合面は、複数の接合面とされ、前記少なくとも1つの非接合面は、複数の非接合面とされ、前記複数の発光素子は、前記絶縁基板の一面に並べられ、それぞれ、前記複数の接合面に接合されて搭載される。 The phosphor substrate of the second aspect of the present invention is the phosphor substrate of the first aspect, and the at least one light emitting element is a plurality of light emitting elements, and the at least one bonding surface is a plurality of bonding surfaces. The at least one non-bonded surface is regarded as a plurality of non-bonded surfaces, and the plurality of light emitting elements are arranged on one surface of the insulating substrate, and each of the plurality of non-bonded surfaces is bonded and mounted on the plurality of bonded surfaces. ..

本発明の第3態様の蛍光体基板は、第1態様の蛍光体基板であって、前記回路パターン層には、前記少なくとも1つの接合面と前記平面における前記少なくとも1つの接合面以外の部分とされる少なくとも1つの非接合面とを隔てる少なくとも1つの溝が形成されている。 The fluorescent substrate of the third aspect of the present invention is the fluorescent substrate of the first aspect, and the circuit pattern layer includes a portion other than the at least one bonding surface and the at least one bonding surface on the plane. At least one groove is formed that separates the at least one non-bonded surface.

本発明の第4態様の蛍光体基板は、第3態様の蛍光体基板であって、前記少なくとも1つの発光素子は、複数の発光素子とされ、前記少なくとも1つの接合面は、複数の接合面とされ、前記少なくとも1つの非接合面は、複数の非接合面とされ、前記少なくとも1つの溝は、複数の溝とされ、前記複数の発光素子は、前記絶縁基板の一面に並べられ、それぞれ、前記複数の接合面に接合されて搭載される。 The phosphor substrate of the fourth aspect of the present invention is the phosphor substrate of the third aspect, and the at least one light emitting element is a plurality of light emitting elements, and the at least one bonding surface is a plurality of bonding surfaces. The at least one non-junction surface is a plurality of non-junction surfaces, the at least one groove is a plurality of grooves, and the plurality of light emitting elements are arranged on one surface of the insulating substrate, respectively. , It is joined and mounted on the plurality of joint surfaces.

本発明の第1態様の発光基板は、第1〜第4態様のいずれか一態様の蛍光体基板と、前記少なくとも1つの接合面に接合されている少なくとも1つの発光素子と、を備える。 The light emitting substrate of the first aspect of the present invention includes a phosphor substrate of any one of the first to fourth aspects and at least one light emitting element bonded to the at least one bonding surface.

本発明の第2態様の発光基板は、第1態様の発光基板であって、前記蛍光体層における前記厚み方向外側に向く面の前記厚み方向の位置は、前記少なくとも1つの発光素子における前記厚み方向外側に向く面の位置よりも前記厚み方向内側に位置している。 The light emitting substrate of the second aspect of the present invention is the light emitting substrate of the first aspect, and the position in the thickness direction of the surface of the phosphor layer facing outward in the thickness direction is the thickness of the at least one light emitting element. It is located inside the thickness direction with respect to the position of the surface facing outward in the direction.

本発明の第3態様の発光基板は、第1態様の発光基板であって、前記蛍光体層における前記厚み方向外側に向く面の前記厚み方向の位置は、前記少なくとも1つの発光素子の厚み方向の中央の位置又は当該位置よりも前記厚み方向内側に位置している。 The light emitting substrate of the third aspect of the present invention is the light emitting substrate of the first aspect, and the position in the thickness direction of the surface of the phosphor layer facing outward in the thickness direction is the thickness direction of the at least one light emitting element. It is located at the center of the above or inside the thickness direction from the position.

本発明の照明装置は、第1〜第3態様のいずれか一態様の発光基板と、前記発光素子を発光させるための電力を供給する電源と、を備える。 The lighting device of the present invention includes a light emitting substrate according to any one of the first to third aspects, and a power source for supplying electric power for causing the light emitting element to emit light.

本発明の第1態様の蛍光体基板の製造方法は、絶縁基板、回路パターン層、及び、少なくとも1つの発光素子の発光を励起光としたときの発光ピーク波長が可視光領域にある蛍光体を含む蛍光体層を備える蛍光体基板の製造方法であって、前記絶縁基板の一面に、配線パターン層を形成するパターン層形成工程と、前記配線パターン層の一部に前記蛍光体層を形成する蛍光体層形成工程と、を含み、前記蛍光体層形成工程では、前記蛍光体層の厚みよりも薄い蛍光体パターンを積層させて、前記蛍光体層を形成する。 In the method for manufacturing a fluorescent substance substrate according to the first aspect of the present invention, a fluorescent substance having a emission peak wavelength in the visible light region when the emission light of an insulating substrate, a circuit pattern layer, and at least one light emitting element is used as excitation light is used. A method for manufacturing a fluorescent substrate including a fluorescent layer, which comprises a pattern layer forming step of forming a wiring pattern layer on one surface of the insulating substrate, and forming the fluorescent layer on a part of the wiring pattern layer. In the fluorescent layer forming step, which includes a fluorescent layer forming step, a fluorescent material pattern thinner than the thickness of the fluorescent layer is laminated to form the fluorescent layer.

本発明の第2態様の蛍光体基板の製造方法は、第1態様の蛍光体基板の製造方法であって、前記蛍光体層形成工程では、転写により、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンをn回積層させて前記蛍光体層を形成する。 The method for manufacturing a fluorescent substrate according to the second aspect of the present invention is the method for manufacturing a fluorescent substrate according to the first aspect, and in the fluorescent layer forming step, 1 / n (n) of the fluorescent layer is transferred by transfer. The phosphor layer having a thickness of ≧ 2) is laminated n times to form the phosphor layer.

本発明の第3態様の蛍光体基板の製造方法は、第1態様の蛍光体基板の製造方法であって、前記蛍光体層形成工程では、液体を吐出する吐出部を前記絶縁基板に相対的に移動させながら、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、前記吐出部に前記蛍光体を含む液体を吐出させて、前記蛍光体層を形成する。 The method for manufacturing a fluorescent substrate according to a third aspect of the present invention is the method for manufacturing a fluorescent substrate according to the first aspect, and in the phosphor layer forming step, a discharge portion for discharging a liquid is relative to the insulating substrate. The liquid containing the fluorescent substance is discharged to the ejection portion so that the fluorescent substance patterns having a thickness of 1 / n (n ≧ 2) of the fluorescent substance layer are laminated n times while being moved to the fluorescent substance. Form a layer.

本発明の第4態様の蛍光体基板の製造方法は、第1態様の蛍光体基板の製造方法であって、前記蛍光体層形成工程では、液滴を吐出する吐出部を前記絶縁基板に相対的に移動させながら、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、前記吐出部に前記蛍光体を含む液体を液滴として吐出させて、前記蛍光体層を形成する。 The method for manufacturing a fluorescent substrate according to the fourth aspect of the present invention is the method for manufacturing a fluorescent substrate according to the first aspect, and in the fluorescent layer forming step, the ejection portion for ejecting droplets is relative to the insulating substrate. The liquid containing the fluorescent substance is ejected as droplets to the ejection portion so that the fluorescent substance patterns having a thickness of 1 / n (n ≧ 2) of the fluorescent substance layer are laminated n times. , The fluorescent layer is formed.

本発明の第5態様の蛍光体基板の製造方法は、第1態様の蛍光体基板の製造方法であって、前記蛍光体層形成工程では、印刷により、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンをn回積層させて前記蛍光体層を形成する。 The method for manufacturing a fluorescent substrate according to a fifth aspect of the present invention is the method for manufacturing a fluorescent substrate according to the first aspect, and in the fluorescent layer forming step, 1 / n (n) of the fluorescent layer is printed by printing. The phosphor layer having a thickness of ≧ 2) is laminated n times to form the phosphor layer.

本発明の第6態様の蛍光体基板の製造方法は、第5態様の蛍光体基板の製造方法であって、前記印刷は、スクリーン印刷とされる。 The method for manufacturing a phosphor substrate according to a sixth aspect of the present invention is the method for manufacturing a phosphor substrate according to a fifth aspect, and the printing is screen printing.

本発明の第7態様の蛍光体基板の製造方法は、第1〜第6態様のいずれか一態様の蛍光体基板の製造方法であって、前記蛍光体層形成工程では、前記蛍光体層の厚みよりも薄い蛍光体パターンを積層させて、前記蛍光体層の厚みの半分以下の厚みの前記蛍光体層を形成する。 The method for manufacturing a fluorescent substrate according to the seventh aspect of the present invention is the method for manufacturing a fluorescent substrate according to any one of the first to sixth aspects, and in the fluorescent layer forming step, the fluorescent layer is formed. The fluorescent material patterns thinner than the thickness are laminated to form the fluorescent material layer having a thickness of half or less of the thickness of the fluorescent material layer.

本発明の第8態様の蛍光体基板の製造方法は、第1〜第7態様のいずれか一態様の蛍光体基板の製造方法であって、前記パターン層形成工程の後、かつ、前記蛍光体層形成工程の前に行われる工程であって、前記回路パターン層における前記絶縁基板の厚み方向外側に向く平面に少なくとも1つの溝を形成する溝形成工程と、前記蛍光体層形成工程の前に行われる工程であって、前記平面における前記少なくとも1つの溝を挟んで一方の部分に少なくとも一つの発光素子を接合させるためのはんだを配置するはんだ配置工程とを含む。 The method for producing a phosphor substrate according to the eighth aspect of the present invention is the method for producing a phosphor substrate according to any one of the first to seventh aspects, after the pattern layer forming step and the phosphor. A step performed before the layer forming step, in which at least one groove is formed in a plane of the circuit pattern layer facing outward in the thickness direction of the insulating substrate, and before the phosphor layer forming step. The step to be performed includes a solder arranging step of arranging solder for joining the at least one light emitting element to one portion of the at least one groove on the plane.

本発明の第1態様の発光基板の製造方法は、第1〜第8態様のいずれか一態様の蛍光体基板の製造方法と、前記配線パターン層の一部に前記少なくとも1つの発光素子を接合する接合工程と、を含む。 The method for manufacturing a light emitting substrate according to the first aspect of the present invention is the method for manufacturing a phosphor substrate according to any one of the first to eighth aspects, and the at least one light emitting element is bonded to a part of the wiring pattern layer. The joining process and the joining process are included.

本発明の第2態様の発光基板の製造方法は、第8態様の蛍光体基板の製造方法と、前記回路パターン層の一部であって、前記平面における前記少なくとも1つの溝を挟んで他方の部分に前記少なくとも1つの発光素子を接合する接合工程と、を含む。 The method for manufacturing a light emitting substrate according to a second aspect of the present invention is the method for manufacturing a phosphor substrate according to an eighth aspect, which is a part of the circuit pattern layer and the other with the at least one groove in the plane interposed therebetween. A joining step of joining the at least one light emitting element to the portion is included.

本発明の第3態様の発光基板の製造方法は、第1又は第2態様の発光基板の製造方法であって、前記接合工程は、前記蛍光体層形成工程の後に行われる。 The method for manufacturing a light emitting substrate according to the third aspect of the present invention is the method for manufacturing a light emitting substrate according to the first or second aspect, and the bonding step is performed after the phosphor layer forming step.

本発明の第4態様の発光基板の製造方法は、第1又は第2態様の発光基板の製造方法であって、前記接合工程では、前記はんだにフラックスを塗布してから前記はんだを溶融させて前記他方の部分に前記少なくとも1つの発光素子を接合させる。 The method for manufacturing a light emitting substrate according to a fourth aspect of the present invention is the method for manufacturing a light emitting board according to the first or second aspect, and in the joining step, flux is applied to the solder and then the solder is melted. The at least one light emitting element is bonded to the other portion.

本発明は、多層構造の蛍光体層を備える発光基板を提供することができる。 The present invention can provide a light emitting substrate including a phosphor layer having a multilayer structure.

本実施形態の発光基板の平面図である。It is a top view of the light emitting substrate of this embodiment. 本実施形態の発光基板の底面図である。It is a bottom view of the light emitting substrate of this embodiment. 図1Aの1C−1C切断線により切断した発光基板の部分断面図である。It is a partial cross-sectional view of the light emitting substrate cut by the 1C-1C cutting line of FIG. 1A. 本実施形態の蛍光体基板(蛍光体層を省略)の平面図である。It is a top view of the fluorescent substance substrate (the fluorescent substance layer is omitted) of this embodiment. 本実施形態の蛍光体基板の平面図である。It is a top view of the phosphor substrate of this embodiment. 本実施形態の発光基板の製造方法における第1工程の説明図である。It is explanatory drawing of the 1st step in the manufacturing method of the light emitting substrate of this embodiment. 本実施形態の発光基板の製造方法における第2工程の説明図である。It is explanatory drawing of the 2nd step in the manufacturing method of the light emitting substrate of this embodiment. 本実施形態の発光基板の製造方法における第3工程の説明図である。It is explanatory drawing of the 3rd process in the manufacturing method of the light emitting substrate of this embodiment. 本実施形態の発光基板の製造方法における第3工程(前半)の説明図である。It is explanatory drawing of the 3rd step (the first half) in the manufacturing method of the light emitting substrate of this embodiment. 本実施形態の発光基板の製造方法における第3工程(後半)の説明図である。It is explanatory drawing of the 3rd step (the latter half) in the manufacturing method of the light emitting substrate of this embodiment. 本実施形態の発光基板の製造方法における第4工程の説明図である。It is explanatory drawing of the 4th process in the manufacturing method of the light emitting substrate of this embodiment. 本実施形態の発光基板の発光動作を説明するための図である。It is a figure for demonstrating the light emitting operation of the light emitting substrate of this embodiment. 比較形態の発光基板の発光動作を説明するための図である。It is a figure for demonstrating the light emitting operation of the light emitting substrate of a comparative form. 第1変形例の発光基板の製造方法における第3工程の説明図である。It is explanatory drawing of the 3rd process in the manufacturing method of the light emitting substrate of 1st modification. 第2変形例の発光基板の製造方法における第3工程の説明図である。It is explanatory drawing of the 3rd step in the manufacturing method of the light emitting substrate of the 2nd modification. 第3変形例の発光基板の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the light emitting substrate of the 3rd modification.

≪概要≫
以下、本実施形態の発光基板10(実装基板の一例)の構成及び機能について図1A〜図1Cを参照しながら説明する。次いで、本実施形態の発光基板10の製造方法について図3A〜図3Fを参照しながら説明する。次いで、本実施形態の発光基板10の発光動作について図4を参照しながら説明する。次いで、本実施形態の効果について図4等を参照しながら説明する。なお、以下の説明において参照するすべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。
≪Overview≫
Hereinafter, the configuration and function of the light emitting board 10 (an example of the mounting board) of the present embodiment will be described with reference to FIGS. 1A to 1C. Next, the method of manufacturing the light emitting substrate 10 of the present embodiment will be described with reference to FIGS. 3A to 3F. Next, the light emitting operation of the light emitting substrate 10 of the present embodiment will be described with reference to FIG. Next, the effect of this embodiment will be described with reference to FIG. 4 and the like. In all the drawings referred to in the following description, similar components are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

≪本実施形態の発光基板の構成及び機能≫
図1Aは本実施形態の発光基板10の平面図(表面31から見た図)、図1Bは本実施形態の発光基板10の底面図(裏面33から見た図)である。図1Cは、図1Aの1C−1C切断線により切断した発光基板10の部分断面図である。
本実施形態の発光基板10は、表面31及び裏面33から見て、一例として矩形とされている。また、本実施形態の発光基板10は、複数の発光素子20(電子部品の一例)と、蛍光体基板30と、コネクタ、ドライバIC等の電子部品(図示省略)とを備えている。すなわち、本実施形態の発光基板10は、蛍光体基板30に、複数の発光素子20及び上記電子部品が搭載されたものとされている。
本実施形態の発光基板10は、リード線の直付けにより又はコネクタを介して外部電源(図示省略)から給電されると、発光する機能を有する。そのため、本実施形態の発光基板10は、例えば照明装置(図示省略)等における主要な光学部品として利用される。
<< Configuration and function of the light emitting substrate of this embodiment >>
1A is a plan view of the light emitting substrate 10 of the present embodiment (viewed from the front surface 31), and FIG. 1B is a bottom view of the light emitting substrate 10 of the present embodiment (viewed from the back surface 33). FIG. 1C is a partial cross-sectional view of a light emitting substrate 10 cut by the 1C-1C cutting line of FIG. 1A.
The light emitting substrate 10 of the present embodiment is rectangular as an example when viewed from the front surface 31 and the back surface 33. Further, the light emitting substrate 10 of the present embodiment includes a plurality of light emitting elements 20 (an example of electronic components), a phosphor substrate 30, and electronic components such as a connector and a driver IC (not shown). That is, in the light emitting substrate 10 of the present embodiment, a plurality of light emitting elements 20 and the above electronic components are mounted on the phosphor substrate 30.
The light emitting substrate 10 of the present embodiment has a function of emitting light when power is supplied from an external power source (not shown) by directly attaching a lead wire or via a connector. Therefore, the light emitting substrate 10 of the present embodiment is used as a main optical component in, for example, a lighting device (not shown).

<複数の発光素子>
複数の発光素子20は、それぞれ、一例として、フリップチップLED22(以下、LED22という。)が組み込まれたCSP(Chip Scale Package)とされている(図1C参照)。CSPとして、図1Cに示すように、LED22の底面を除く全周囲(5面)が蛍光体封止層24により覆われていることが好ましい。蛍光体封止層24には蛍光体が含まれ、LED22の光は蛍光体封止層24の蛍光体により色変換されて外部に出射する。複数の発光素子20は、図1Aに示されるように、蛍光体基板30の表面31(一面の一例)に、表面31の全体に亘って規則的に並べられた状態で、蛍光体基板30に搭載されている。なお、本実施形態の各発光素子20が発光する光の相関色温度は、一例として3,018Kとされている。また、複数の発光素子20は、発光動作時に、ヒートシンク(図示省略)や冷却ファン(図示省略)を用いることで、蛍光体基板30を一例として常温から50℃〜100℃に収まるように放熱(冷却)されるようになっている。
ここで、本明細書で数値範囲に使用する「〜」の意味について補足すると、例えば「50℃〜100℃」は「50℃以上100℃以下」を意味する。そして、本明細書で数値範囲に使用する「〜」は、「『〜』の前の記載部分以上『〜』の後の記載部分以下」を意味する。
<Multiple light emitting elements>
As an example, each of the plurality of light emitting elements 20 is a CSP (Chip Scale Package) in which a flip chip LED 22 (hereinafter referred to as LED 22) is incorporated (see FIG. 1C). As a CSP, as shown in FIG. 1C, it is preferable that the entire circumference (five surfaces) except the bottom surface of the LED 22 is covered with the fluorescent material encapsulating layer 24. The phosphor-sealed layer 24 contains a phosphor, and the light of the LED 22 is color-converted by the phosphor of the phosphor-sealed layer 24 and emitted to the outside. As shown in FIG. 1A, the plurality of light emitting elements 20 are regularly arranged on the surface 31 (an example of one surface) of the phosphor substrate 30 over the entire surface 31 on the phosphor substrate 30. It is installed. The correlated color temperature of the light emitted by each light emitting element 20 of the present embodiment is set to 3,018K as an example. Further, the plurality of light emitting elements 20 use a heat sink (not shown) and a cooling fan (not shown) during the light emitting operation to dissipate heat so as to be within 50 ° C. to 100 ° C. from room temperature, taking the phosphor substrate 30 as an example. It is designed to be cooled).
Here, supplementing the meaning of "-" used in the numerical range in the present specification, for example, "50 ° C to 100 ° C" means "50 ° C or more and 100 ° C or less". And, "~" used in the numerical range in this specification means "more than the description part before" ~ "and less than the description part after" ~ "".

<蛍光体基板>
図2Aは、本実施形態の蛍光体基板30の図であって、蛍光体層36を省略して図示した平面図(表面31から見た図)である。図2Bは、本実施形態の蛍光体基板30の平面図(表面31から見た図)である。なお、本実施形態の蛍光体基板30の底面図は、発光基板10を裏面33から見た図と同じである。また、本実施形態の蛍光体基板30の部分断面図は、図1Cの部分断面図から発光素子20を除いた場合の図と同じである。すなわち、本実施形態の蛍光体基板30は、表面31及び裏面33から見て、一例として矩形とされている。
<Fluorescent substrate>
FIG. 2A is a view of the phosphor substrate 30 of the present embodiment, and is a plan view (viewed from the surface 31) showing the phosphor layer 36 omitted. FIG. 2B is a plan view (viewed from the surface 31) of the phosphor substrate 30 of the present embodiment. The bottom view of the phosphor substrate 30 of the present embodiment is the same as the view of the light emitting substrate 10 from the back surface 33. Further, the partial cross-sectional view of the phosphor substrate 30 of the present embodiment is the same as the view when the light emitting element 20 is removed from the partial cross-sectional view of FIG. 1C. That is, the phosphor substrate 30 of the present embodiment is rectangular as an example when viewed from the front surface 31 and the back surface 33.

本実施形態の蛍光体基板30は、絶縁層32(絶縁基板の一例)と、回路パターン層34と、蛍光体層36と、裏面パターン層38とを備えている(図1B、図1C、図2A及び図2B参照)。なお、図2Aでは蛍光体層36が省略されているが、蛍光体層36は、図2Bに示されるように、一例として、絶縁層32及び回路パターン層34の表面31における、後述する複数の電極対34A以外の部分に配置されている。 The phosphor substrate 30 of the present embodiment includes an insulating layer 32 (an example of an insulating substrate), a circuit pattern layer 34, a phosphor layer 36, and a back surface pattern layer 38 (FIGS. 1B, 1C, and FIG. 2A and FIG. 2B). Although the fluorescent material layer 36 is omitted in FIG. 2A, as shown in FIG. 2B, the fluorescent material layer 36 is, as an example, a plurality of described later on the surface 31 of the insulating layer 32 and the circuit pattern layer 34. It is arranged in a portion other than the electrode pair 34A.

また、蛍光体基板30には、図1B及び図2Aに示されるように、四つ角付近の4箇所及び中央付近の2箇所の6箇所に貫通孔39が形成されている。6箇所の貫通孔39は、蛍光体基板30及び発光基板10の製造時に位置決め孔として利用されるようになっている。あわせて、6箇所の貫通孔39は、(発光)灯具筐体への熱引き効果確保(基板反り及び浮き防止)のための取り付け用のネジ穴として利用される。なお、本実施形態の蛍光体基板30は、後述するように、絶縁板の両面に銅箔層が設けられた両面板(以下、マザーボードMBという。図3A参照)を加工(エッチング等)して製造されるが、マザーボードMBは一例として利昌工業株式会社製のCS−3305Aが用いられる。 Further, as shown in FIGS. 1B and 2A, the phosphor substrate 30 is formed with through holes 39 at four locations near the four corners and two locations near the center. The six through holes 39 are used as positioning holes during the manufacture of the phosphor substrate 30 and the light emitting substrate 10. In addition, the six through holes 39 are used as mounting screw holes for ensuring the heat-drawing effect (preventing warping and floating of the substrate) of the (light emitting) lamp housing. As described later, the phosphor substrate 30 of the present embodiment is processed (etched or the like) from a double-sided plate (hereinafter referred to as a motherboard MB; see FIG. 3A) in which copper foil layers are provided on both sides of the insulating plate. Although it is manufactured, CS-3305A manufactured by Risho Kogyo Co., Ltd. is used as an example of the motherboard MB.

〔絶縁層〕
以下、本実施形態の絶縁層32の主な特徴について説明する。
形状は、前述のとおり、一例として表面31及び裏面33から見て矩形である。
材質は、一例としてビスマレイミド樹脂及びガラスクロスを含む絶縁材である。また、当該絶縁材にはハロゲン及びリンは含まれていない(ハロゲンフリー、リンフリー)。
厚みは、一例として100μm〜200μmである。
縦方向及び横方向の熱膨張係数(CTE)は、それぞれ、一例として、50℃〜100℃の範囲において10ppm/℃以下である。また、別の見方をすると、縦方向及び横方向の熱膨張係数(CTE)は、それぞれ、一例として、6ppm/Kである。この値は、本実施形態の発光素子20の場合とほぼ同等(90%〜110%、すなわち±10%以内)である。
ガラス転移温度は、一例として、300℃よりも高い。
貯蔵弾性率は、一例として、100℃〜300℃の範囲において、1.0×1010Paよりも大きく1.0×1011Paよりも小さい。
縦方向及び横方向の曲げ弾性率は、一例として、それぞれ、常態において35GPa及び34GPaである。
縦方向及び横方向の熱間曲げ弾性率は、一例として、250℃において19GPaである。
吸水率は、一例として、23℃の温度環境で24時間放置した場合に0.13%である。
比誘電率は、一例として、1MHz常態において4.6である。
誘電正接は、一例として、1MHz常態において、0.010である。
[Insulation layer]
Hereinafter, the main features of the insulating layer 32 of the present embodiment will be described.
As described above, the shape is rectangular when viewed from the front surface 31 and the back surface 33 as an example.
The material is, for example, an insulating material containing a bismaleimide resin and a glass cloth. In addition, the insulating material does not contain halogen and phosphorus (halogen-free, phosphorus-free).
The thickness is, for example, 100 μm to 200 μm.
The coefficient of thermal expansion (CTE) in the vertical direction and the horizontal direction is, for example, 10 ppm / ° C. or less in the range of 50 ° C. to 100 ° C., respectively. From another point of view, the coefficient of thermal expansion (CTE) in the vertical direction and the horizontal direction is 6 ppm / K, respectively, as an example. This value is substantially the same as that of the light emitting device 20 of the present embodiment (90% to 110%, that is, within ± 10%).
The glass transition temperature is, for example, higher than 300 ° C.
As an example, the storage elastic modulus is larger than 1.0 × 10 10 Pa and smaller than 1.0 × 10 11 Pa in the range of 100 ° C to 300 ° C.
The flexural modulus in the longitudinal direction and the lateral direction is, for example, 35 GPa and 34 GPa in the normal state, respectively.
The hot bending modulus in the longitudinal and lateral directions is, for example, 19 GPa at 250 ° C.
As an example, the water absorption rate is 0.13% when left in a temperature environment of 23 ° C. for 24 hours.
The relative permittivity is, for example, 4.6 under the normal condition of 1 MHz.
The dielectric loss tangent is, for example, 0.010 in the 1 MHz normal state.

〔回路パターン層〕
本実施形態の回路パターン層34は、絶縁層32の表面31側に設けられた金属層とされている。本実施形態の回路パターン層34は一例として銅箔層(Cu製の層)とされている。別言すれば、本実施形態の回路パターン層34は、少なくともその表面(絶縁層32の厚み方向外側に向く面)が銅を含んで形成された平面とされている。
[Circuit pattern layer]
The circuit pattern layer 34 of the present embodiment is a metal layer provided on the surface 31 side of the insulating layer 32. The circuit pattern layer 34 of the present embodiment is, for example, a copper foil layer (a layer made of Cu). In other words, the circuit pattern layer 34 of the present embodiment is a flat surface formed by at least its surface (a surface of the insulating layer 32 facing outward in the thickness direction) containing copper.

回路パターン層34は、絶縁層32に設けられたパターンとされ、コネクタ(図示省略)が接合される端子(図示省略)と導通している。そして、回路パターン層34は、コネクタを介して外部電源(図示省略)から給電された電力を、発光基板10の構成時の複数の発光素子20に供給するようになっている。そのため、回路パターン層34の一部は、複数の発光素子20がそれぞれ接合される複数の電極対34Aとされている。すなわち、本実施形態の発光基板10の回路パターン層34は、絶縁層32に配置され、各発光素子20に接続されている。また、別の見方をすると、本実施形態の蛍光体基板30の回路パターン層34は、絶縁層32に配置され、各電極対34Aで各発光素子20に接続される。ここで、本明細書では、各電極対34Aの表面を接合面34A1という。また、各接合面34A1は、図1C、図2A、図4等に示されるように、回路パターン層の表面(平面)における各溝34Eを挟んで一方側の面とされている。 The circuit pattern layer 34 has a pattern provided on the insulating layer 32, and is electrically connected to a terminal (not shown) to which a connector (not shown) is joined. The circuit pattern layer 34 is adapted to supply electric power supplied from an external power source (not shown) via a connector to a plurality of light emitting elements 20 at the time of configuring the light emitting board 10. Therefore, a part of the circuit pattern layer 34 is a plurality of electrode pairs 34A to which the plurality of light emitting elements 20 are bonded. That is, the circuit pattern layer 34 of the light emitting substrate 10 of the present embodiment is arranged in the insulating layer 32 and connected to each light emitting element 20. From another point of view, the circuit pattern layer 34 of the phosphor substrate 30 of the present embodiment is arranged on the insulating layer 32 and is connected to each light emitting element 20 by each electrode pair 34A. Here, in the present specification, the surface of each electrode pair 34A is referred to as a bonding surface 34A1. Further, as shown in FIGS. 1C, 2A, 4 and the like, each joint surface 34A1 is a surface on one side of each groove 34E on the surface (plane surface) of the circuit pattern layer.

また、前述のとおり、本実施形態の発光基板10における複数の発光素子20は表面31の全体に亘って規則的に並べられていることから、複数の電極対34Aも表面31の全体に亘って規則的に並べられている(図2A参照)。回路パターン層34における複数の電極対34A以外の部分を、配線部分34Bという。ここで、配線部分34Bは各発光素子20に接合される部分ではないことから、本明細書において配線部分34Bの表面を非接合面34B1という。別言すると、各非接合面34B1は、図1C、図2A、図4等に示されるように、回路パターン層の表面(平面)における各溝34Eを挟んで各接合面34A1の反対側の面とされている。すなわち、本実施形態の回路パターン層34には、複数の接合面34A1と、複数の非接合面34B1とを隔てる複数の溝34Eが形成されている。
なお、絶縁層32の表面31における回路パターン層34が配置されている領域(回路パターン層34の専有面積)は、一例として、絶縁層32の表面31の60%以上の領域(面積)とされている(図2A参照)。また、本実施形態では、各接合面34A1と各非接合面34B1とは、絶縁層32の厚み方向における同じ位置に位置している(図1C、図3F等参照)。
Further, as described above, since the plurality of light emitting elements 20 in the light emitting substrate 10 of the present embodiment are regularly arranged over the entire surface 31, the plurality of electrode pairs 34A also cover the entire surface 31. They are arranged regularly (see FIG. 2A). The portion of the circuit pattern layer 34 other than the plurality of electrode pairs 34A is referred to as a wiring portion 34B. Here, since the wiring portion 34B is not a portion joined to each light emitting element 20, the surface of the wiring portion 34B is referred to as a non-joining surface 34B1 in the present specification. In other words, as shown in FIGS. 1C, 2A, 4 and the like, each non-joining surface 34B1 is a surface opposite to each joining surface 34A1 with each groove 34E on the surface (planar surface) of the circuit pattern layer interposed therebetween. It is said that. That is, the circuit pattern layer 34 of the present embodiment is formed with a plurality of grooves 34E that separate the plurality of bonding surfaces 34A1 and the plurality of non-bonding surfaces 34B1.
The region (occupied area of the circuit pattern layer 34) on the surface 31 of the insulating layer 32 where the circuit pattern layer 34 is arranged is, for example, a region (area) of 60% or more of the surface 31 of the insulating layer 32. (See Fig. 2A). Further, in the present embodiment, each joint surface 34A1 and each non-joint surface 34B1 are located at the same position in the thickness direction of the insulating layer 32 (see FIGS. 1C, 3F, etc.).

〔蛍光体層〕
本実施形態の蛍光体層36は、図2Bに示されるように、一例として、絶縁層32及び回路パターン層34の表面31における、複数の電極対34A及び溝34E以外の部分に配置されている。すなわち、蛍光体層36は、回路パターン層34における複数の電極対34A及び溝34E以外の領域に配置されている。別言すると、蛍光体層36の少なくとも一部は、表面31における、複数の溝34E及び各溝34Eに隣接する各接合面34A1の周囲に配置されている(図1C及び図2B参照)。さらに、別の見方をすると、蛍光体層36の少なくとも一部は、表面31側から見て、各接合面34A1の周りを全周に亘って囲むように配置されている。そして、本実施形態では、絶縁層32の表面31における蛍光体層36が配置されている領域は、一例として、絶縁層32の表面31における80%以上の領域とされている。
なお、蛍光体層36における絶縁層32の厚み方向外側の面は、回路パターン層34の接合面34A1よりも当該厚み方向外側に位置している(図1C参照)。また、本実施形態の蛍光体層36は、各非接合面34B1における溝34Eとの境界において、発光素子20に対向する対向面36Aを有する(図1C参照)。また、本実施形態では、一例として、蛍光体層36における絶縁層32の厚み方向外側の面(外側に向く面)の前記厚み方向の位置は、各発光素子20の前記厚み方向の中央の位置に位置している(図1C参照)。ただし、蛍光体層36における絶縁層32の厚み方向外側の面の前記厚み方向の位置は、各発光素子20の前記厚み方向の中央よりも前記厚み方向内側の位置に位置していることが好ましい。以上の理由は、各発光素子20による発光効果を確保するためである。
[Fluorescent layer]
As shown in FIG. 2B, the phosphor layer 36 of the present embodiment is arranged in a portion other than the plurality of electrode pairs 34A and the groove 34E on the surface 31 of the insulating layer 32 and the circuit pattern layer 34, as an example. .. That is, the phosphor layer 36 is arranged in a region other than the plurality of electrode pairs 34A and the groove 34E in the circuit pattern layer 34. In other words, at least a portion of the phosphor layer 36 is arranged around the plurality of grooves 34E and each junction surface 34A1 adjacent to each groove 34E on the surface 31 (see FIGS. 1C and 2B). Further, from another viewpoint, at least a part of the phosphor layer 36 is arranged so as to surround each joint surface 34A1 over the entire circumference when viewed from the surface 31 side. In the present embodiment, the region where the phosphor layer 36 is arranged on the surface 31 of the insulating layer 32 is, for example, 80% or more of the region on the surface 31 of the insulating layer 32.
The surface of the phosphor layer 36 on the outer side in the thickness direction of the insulating layer 32 is located on the outer side in the thickness direction of the bonding surface 34A1 of the circuit pattern layer 34 (see FIG. 1C). Further, the phosphor layer 36 of the present embodiment has a facing surface 36A facing the light emitting element 20 at the boundary with the groove 34E in each non-bonding surface 34B1 (see FIG. 1C). Further, in the present embodiment, as an example, the position of the outer surface (outward facing surface) of the insulating layer 32 in the thickness direction of the phosphor layer 36 in the thickness direction is the central position in the thickness direction of each light emitting element 20. It is located in (see FIG. 1C). However, it is preferable that the position of the outer surface of the insulating layer 32 in the thickness direction of the phosphor layer 36 in the thickness direction is located inside the thickness direction of each light emitting element 20 with respect to the center in the thickness direction. .. The above reason is to secure the light emitting effect by each light emitting element 20.

本実施形態の蛍光体層36は、一例として、後述する蛍光体とバインダーとを含む、絶縁層とされている。蛍光体層36に含まれる蛍光体は、バインダーに分散された状態で保持されている微粒子とされ、各発光素子20のLED22の発光を励起光として励起する性質を有する。具体的には、本実施形態の蛍光体は、発光素子20のLED22の発光を励起光としたときの発光ピーク波長が可視光領域にある性質を有する。なお、バインダーは、例えば、エポキシ系、アクリレート系、シリコーン系等で、ソルダーレジストに含まれるバインダーと同等の絶縁性を有するものであればよい。 As an example, the phosphor layer 36 of the present embodiment is an insulating layer containing a fluorescent substance and a binder, which will be described later. The phosphor contained in the phosphor layer 36 is fine particles held in a state of being dispersed in a binder, and has a property of exciting the light emitted by the LED 22 of each light emitting element 20 as excitation light. Specifically, the phosphor of the present embodiment has a property that the emission peak wavelength in the visible light region when the emission of the LED 22 of the light emitting element 20 is used as excitation light. The binder may be, for example, epoxy-based, acrylate-based, silicone-based, or the like, and may have an insulating property equivalent to that of the binder contained in the solder resist.

(蛍光体の具体例)
ここで、本実施形態の蛍光体層36に含まれる蛍光体は、一例として、Euを含有するα型サイアロン蛍光体、Euを含有するβ型サイアロン蛍光体、Euを含有するCASN蛍光体及びEuを含有するSCASN蛍光体からなる群から選ばれる少なくとも一種以上の蛍光体とされている。なお、前述の蛍光体は、本実施形態の一例であり、YAG、LuAG、BOSその他の可視光励起の蛍光体のように、前述の蛍光体以外の蛍光体であってもよい。
(Specific example of fluorescent substance)
Here, the fluorescent material contained in the fluorescent material layer 36 of the present embodiment is, for example, an α-type sialone phosphor containing Eu, a β-type sialon fluorescent material containing Eu, a CASN fluorescent material containing Eu, and Eu. It is considered to be at least one kind of phosphor selected from the group consisting of SCASSN phosphors containing. The above-mentioned fluorescent material is an example of the present embodiment, and may be a fluorescent material other than the above-mentioned fluorescent material, such as YAG, LuAG, BOS and other visible light-excited fluorescent materials.

Euを含有するα型サイアロン蛍光体は、一般式:MEuSi12−(m+n)Al(m+n)16−nで表される。上記一般式中、MはLi、Mg、Ca、Y及びランタニド元素(ただし、LaとCeを除く)からなる群から選ばれる、少なくともCaを含む1種以上の元素であり、Mの価数をaとしたとき、ax+2y=mであり、xが0<x≦1.5であり、0.3≦m<4.5、0<n<2.25である。Α-sialon phosphor containing Eu, the general formula: represented by M x Eu y Si 12- (m + n) Al (m + n) O n N 16-n. In the above general formula, M is one or more elements containing at least Ca selected from the group consisting of Li, Mg, Ca, Y and lanthanide elements (excluding La and Ce), and has a valence of M. When a is set, ax + 2y = m, x is 0 <x ≦ 1.5, 0.3 ≦ m <4.5, and 0 <n <2.25.

Euを含有するβ型サイアロン蛍光体は、一般式:Si6−zAl8−z(z=0.005〜1)で表されるβ型サイアロンに発光中心として二価のユーロピウム(Eu2+)を固溶した蛍光体である。The β-type sialone phosphor containing Eu is a β-type sialon represented by the general formula: Si 6-z Al z O z N 8-z (z = 0.005-1) and has a divalent europium as a light emitting center. It is a phosphor in which (Eu 2+) is dissolved.

また、窒化物蛍光体として、Euを含有するCASN蛍光体、Euを含有するSCASN蛍光体等が挙げられる。 Further, examples of the nitride phosphor include a CASN phosphor containing Eu, a SCASN phosphor containing Eu, and the like.

Euを含有するCASN蛍光体(窒化物蛍光体の一例)は、例えば、式CaAlSiN:Eu2+で表され、Eu2+を付活剤とし、アルカリ土類ケイ窒化物からなる結晶を母体とする赤色蛍光体をいう。なお、本明細書におけるEuを含有するCASN蛍光体の定義では、Euを含有するSCASN蛍光体が除かれる。The CASN phosphor (an example of a nitride phosphor) containing Eu is represented by, for example, the formula CaAlSiN 3 : Eu 2+ , using Eu 2+ as an activator and a crystal made of an alkaline earth silicate as a base. Refers to a red phosphor. In addition, in the definition of the CASN fluorescent substance containing Eu in this specification, the SCASN fluorescent substance containing Eu is excluded.

Euを含有するSCASN蛍光体(窒化物蛍光体の一例)は、例えば、式(Sr,Ca)AlSiN:Eu2+で表され、Eu2+を付活剤とし、アルカリ土類ケイ窒化物からなる結晶を母体とする赤色蛍光体をいう。The SCASN fluorophore containing Eu (an example of a nitride fluorophore) is represented by, for example, the formula (Sr, Ca) AlSiN 3 : Eu 2+ , with Eu 2+ as an activator, and is composed of an alkaline earth silicate nitride. A red fluorophore whose parent is a crystal.

〔裏面パターン層〕
本実施形態の裏面パターン層38は、絶縁層32の裏面33側に設けられた金属層とされている。本実施形態の裏面パターン層38は一例として銅箔層(Cu製の層)とされている。
裏面パターン層38は、図1Bに示されるように、絶縁層32の長手方向に沿って直線状に並べられている複数の矩形部分の塊が短手方向において位相をずらしたよう隣接して並べられている層とされている。
なお、裏面パターン層38は、一例として、独立フローティング層とされている。また、裏面パターン層38は、絶縁層32(蛍光体基板30)の厚み方向において、一例として、表面31に配置されている回路パターン層34の80%以上の領域と重なっている。
[Back side pattern layer]
The back surface pattern layer 38 of the present embodiment is a metal layer provided on the back surface 33 side of the insulating layer 32. The back surface pattern layer 38 of the present embodiment is, for example, a copper foil layer (a layer made of Cu).
As shown in FIG. 1B, the back surface pattern layer 38 is arranged adjacent to each other so that a plurality of rectangular blocks arranged linearly along the longitudinal direction of the insulating layer 32 are out of phase in the lateral direction. It is said to be the layer that is being used.
The back surface pattern layer 38 is, for example, an independent floating layer. Further, the back surface pattern layer 38 overlaps with a region of 80% or more of the circuit pattern layer 34 arranged on the front surface 31 as an example in the thickness direction of the insulating layer 32 (fluorescent material substrate 30).

以上が、本実施形態の発光基板10及び蛍光体基板30の構成についての説明である。 The above is a description of the configuration of the light emitting substrate 10 and the phosphor substrate 30 of the present embodiment.

≪本実施形態の発光基板の製造方法≫
次に、本実施形態の発光基板10の製造方法について図3A〜図3Fを参照しながら説明する。本実施形態の発光基板10の製造方法は第1工程、第2工程、第3工程、第4工程及び第5工程を含んでおり、各工程はこれらの記載順で行われる。
<< Manufacturing method of light emitting substrate of this embodiment >>
Next, the manufacturing method of the light emitting substrate 10 of the present embodiment will be described with reference to FIGS. 3A to 3F. The method for manufacturing the light emitting substrate 10 of the present embodiment includes a first step, a second step, a third step, a fourth step, and a fifth step, and each step is performed in the order described.

<第1工程>
図3Aは、第1工程の開始時及び終了時を示す図である。第1工程は、マザーボードMBの表面31に厚み方向から見て回路パターン層34と同じパターン34C(導電性パターン層の一例)を、裏面33に裏面パターン層38を形成する工程である。本工程は、例えばマスクパターン(図示省略)を用いたエッチングにより行われる。なお、本工程は、パターン層形成工程の一例である。
<First step>
FIG. 3A is a diagram showing the start time and the end time of the first step. The first step is a step of forming the same pattern 34C (an example of the conductive pattern layer) as the circuit pattern layer 34 on the front surface 31 of the motherboard MB and the back surface pattern layer 38 on the back surface 33. This step is performed by etching using, for example, a mask pattern (not shown). This step is an example of a pattern layer forming step.

<第2工程>
図3Bは、第2工程の開始時及び終了時を示す図である。第2工程は、パターン34Cの表面に複数の溝34Eを形成する工程である。本工程は、例えばマスクパターン(図示省略)を用いたエッチングにより行われる。本工程が終了すると、回路パターン層34が形成される。すなわち、本工程が終了すると、各溝34Eを挟んで両側にそれぞれ接合面34A1及び非接合面34B1が形成される。なお、本工程は、溝形成工程の一例である。
<Second step>
FIG. 3B is a diagram showing the start time and the end time of the second step. The second step is a step of forming a plurality of grooves 34E on the surface of the pattern 34C. This step is performed by etching using, for example, a mask pattern (not shown). When this step is completed, the circuit pattern layer 34 is formed. That is, when this step is completed, the joining surface 34A1 and the non-joining surface 34B1 are formed on both sides of each groove 34E. This step is an example of a groove forming step.

<第3工程>
図3Cは、第3工程の開始時及び終了時を示す図である。第3工程は、回路パターン層34の各接合面34A1にはんだSPを配置する(別言すると、はんだSPを塗布する)工程である。本工程は、一例として印刷により行われる。なお、本工程は、はんだ配置工程の一例である。
<Third step>
FIG. 3C is a diagram showing the start time and the end time of the third step. The third step is a step of arranging the solder SP on each joint surface 34A1 of the circuit pattern layer 34 (in other words, applying the solder SP). This step is performed by printing as an example. This step is an example of a solder placement step.

<第4工程>
図3Dは、第4工程の開始時及び1層目塗布時を示す図である。図3Eは、第4工程の2層目塗布時及び3層目塗布時を示す図である。第4工程は、回路パターン層34における各非接合面34B1の全域に蛍光体層36を形成する工程である。本工程は、例えば、転写により、蛍光体層36の1/3の厚みの蛍光体パターン361、362、363を3回積層させて蛍光体層36を配置する。本工程では、一例として、蛍光体層36における絶縁層32の厚み方向外側に向く面の前記厚み方向の位置が、回路パターン層34に接合される各発光素子20の前記厚み方向の中央の位置に位置するように、蛍光体層36を塗布する。別言すると、本工程では、蛍光体層36の厚みが各発光素子20の厚みの半分以下となるように、蛍光体層36を塗布する。ただし、前述した理由により、蛍光体層36の厚みは、各発光素子20の厚みの半分以下であることが好ましい。なお、本工程は、蛍光体層配置工程の一例である。
<Fourth step>
FIG. 3D is a diagram showing the start of the fourth step and the time of coating the first layer. FIG. 3E is a diagram showing the time of coating the second layer and the time of coating the third layer in the fourth step. The fourth step is a step of forming the phosphor layer 36 over the entire area of each non-bonded surface 34B1 in the circuit pattern layer 34. In this step, for example, the fluorescent material patterns 361, 362, and 363 having a thickness of 1/3 of the fluorescent material layer 36 are laminated three times by transfer to arrange the fluorescent material layer 36. In this step, as an example, the position in the thickness direction of the surface of the insulating layer 32 facing outward in the thickness direction of the phosphor layer 36 is the center position in the thickness direction of each light emitting element 20 bonded to the circuit pattern layer 34. The phosphor layer 36 is applied so as to be located at. In other words, in this step, the phosphor layer 36 is applied so that the thickness of the phosphor layer 36 is less than half the thickness of each light emitting element 20. However, for the reasons described above, the thickness of the phosphor layer 36 is preferably half or less of the thickness of each light emitting element 20. This step is an example of a phosphor layer arrangement step.

<第5工程>
図3Fは、第5工程の開始時及び終了時を示す図である。第5工程は、蛍光体基板30に複数の発光素子20を搭載する工程である。本工程は、第3工程においてはんだSPが配置された各接合面34A1に複数の発光素子20の各電極を位置合わせした状態ではんだSPを溶かす。その後、はんだSPが冷却されて固化すると、各電極対34A(各接合面34A1)に各発光素子20が接合される。すなわち、本工程は、一例としてリフロー工程により行われる。なお、本工程では、各接合面34A1のはんだSPにフラックスを塗布してから各電極対34Aに各発光素子20を接合させる。このようにすることで、第4工程の前に第3工程を行う本実施形態の場合に、フラックスは各発光素子20にはんだSPを粘着させるように作用する。本工程は、接合工程の一例である。
<Fifth step>
FIG. 3F is a diagram showing the start time and the end time of the fifth step. The fifth step is a step of mounting a plurality of light emitting elements 20 on the phosphor substrate 30. In this step, the solder SP is melted in a state where the electrodes of the plurality of light emitting elements 20 are aligned with each joint surface 34A1 on which the solder SP is arranged in the third step. After that, when the solder SP is cooled and solidified, each light emitting element 20 is bonded to each electrode pair 34A (each bonding surface 34A1). That is, this step is performed by a reflow step as an example. In this step, flux is applied to the solder SP of each bonding surface 34A1 and then each light emitting element 20 is bonded to each electrode pair 34A. By doing so, in the case of the present embodiment in which the third step is performed before the fourth step, the flux acts to adhere the solder SP to each light emitting element 20. This step is an example of a joining step.

以上が、本実施形態の発光基板10の製造方法についての説明である。 The above is the description of the manufacturing method of the light emitting substrate 10 of this embodiment.

≪本実施形態の発光基板の発光動作≫
次に、本実施形態の発光基板10の発光動作について図4を参照しながら説明する。ここで、図4は、本実施形態の発光基板10の発光動作を説明するための図である。
<< Light emitting operation of the light emitting substrate of this embodiment >>
Next, the light emitting operation of the light emitting substrate 10 of the present embodiment will be described with reference to FIG. Here, FIG. 4 is a diagram for explaining the light emitting operation of the light emitting substrate 10 of the present embodiment.

まず、複数の発光素子20を作動させる作動スイッチ(図示省略)がオンになると、コネクタ(図示省略)を介して外部電源(図示省略)から回路パターン層34への給電が開始され、複数の発光素子20は光Lを放射状に発散出射し、その光Lの一部は蛍光体基板30の表面31に到達する。以下、放射された光Lの進行方向に分けて光Lの挙動について説明する。 First, when the operation switch (not shown) for operating the plurality of light emitting elements 20 is turned on, the power supply to the circuit pattern layer 34 is started from the external power supply (not shown) via the connector (not shown), and the plurality of light emitting elements are emitted. The element 20 radiates and emits light L, and a part of the light L reaches the surface 31 of the phosphor substrate 30. Hereinafter, the behavior of the light L will be described separately according to the traveling direction of the emitted light L.

各発光素子20から出射された光Lの一部は、蛍光体層36に入射することなく外部に出射される。この場合、光Lの波長は、各発光素子20から出射された際の光Lの波長と同じままである。 A part of the light L emitted from each light emitting element 20 is emitted to the outside without being incident on the phosphor layer 36. In this case, the wavelength of the light L remains the same as the wavelength of the light L when emitted from each light emitting element 20.

また、各発光素子20から出射された光Lの一部分の中のLED22自身の光は、蛍光体層36に入射する。ここで、前述の「光Lの一部分の中のLED22自身の光」とは、出射された光Lのうち各発光素子20(CSP自身)の蛍光体(蛍光体封止層24)により色変換されていない光、すなわち、LED22自身の光(一例として青色(波長が470nm近傍)の光)を意味する。そして、LED22自身の光Lが蛍光体層36に分散されている蛍光体に衝突すると、蛍光体が励起して励起光を発する。ここで、蛍光体が励起する理由は、蛍光体層36に分散されている蛍光体が青色の光に励起ピークを持つ蛍光体(可視光励起蛍光体)を使用しているためである。これに伴い、光Lのエネルギーの一部は蛍光体の励起に使われることで、光Lのエネルギーの一部が失われる。その結果、光Lの波長が変換される(波長変換がなされる)。例えば、蛍光体層36の蛍光体の種類によっては(例えば、蛍光体に赤色系CASNを用いた場合には)光Lの波長が長くなる(例えば650nm等)。また、蛍光体層36での励起光はそのまま蛍光体層36から出射するものもあるが、一部の励起光は下側の回路パターン層34に向かう。そして、一部の励起光は回路パターン層34での反射により外部に出射する。以上のように、蛍光体層36の蛍光体による励起光の波長が600nm以上の場合、回路パターン層34がCuでも反射効果が望める。なお、蛍光体層36の蛍光体の種類によっては光Lの波長が前述の例と異なるが、いずれの場合であっても光Lの波長変換がなされることになる。例えば、励起光の波長が600nm未満の場合、回路パターン層34又はその表面を例えばAg(鍍金)とすれば反射効果が望める。また、蛍光体層36の下側(絶縁層32側)に白色の反射層が設けられてもよい。反射層は、例えば、酸化チタンフィラー等の白色塗料により設けられる。 Further, the light of the LED 22 itself in a part of the light L emitted from each light emitting element 20 is incident on the phosphor layer 36. Here, the above-mentioned "light of the LED 22 itself in a part of the light L" is color-converted by the phosphor (fluorescent material sealing layer 24) of each light emitting element 20 (CSP itself) in the emitted light L. It means the light that is not emitted, that is, the light of the LED 22 itself (for example, the light of blue color (wavelength near 470 nm)). Then, when the light L of the LED 22 itself collides with the phosphor dispersed in the phosphor layer 36, the phosphor excites and emits excitation light. Here, the reason why the phosphor is excited is that the phosphor dispersed in the phosphor layer 36 uses a phosphor (visible light excited phosphor) having an excitation peak in blue light. Along with this, a part of the energy of the light L is used for exciting the phosphor, so that a part of the energy of the light L is lost. As a result, the wavelength of the light L is converted (wavelength conversion is performed). For example, depending on the type of phosphor in the phosphor layer 36 (for example, when a red CASN is used as the phosphor), the wavelength of light L becomes longer (for example, 650 nm). Further, the excitation light in the phosphor layer 36 may be emitted from the phosphor layer 36 as it is, but some of the excitation light goes to the lower circuit pattern layer 34. Then, a part of the excitation light is emitted to the outside by reflection at the circuit pattern layer 34. As described above, when the wavelength of the excitation light by the phosphor of the phosphor layer 36 is 600 nm or more, the reflection effect can be expected even if the circuit pattern layer 34 is Cu. The wavelength of the light L differs from the above example depending on the type of the phosphor of the phosphor layer 36, but in any case, the wavelength conversion of the light L is performed. For example, when the wavelength of the excitation light is less than 600 nm, the reflection effect can be expected if the circuit pattern layer 34 or its surface is made of, for example, Ag (plating). Further, a white reflective layer may be provided on the lower side (insulating layer 32 side) of the phosphor layer 36. The reflective layer is provided with, for example, a white paint such as a titanium oxide filler.

以上のとおり、各発光素子20が出射した光L(各発光素子20が放射状に出射した光L)は、それぞれ、上記のような複数の光路を経由して上記励起光とともに外部に照射される。そのため、蛍光体層36に含まれる蛍光体の発光波長と、発光素子20(CSP)におけるLED22を封止した(又は覆う)蛍光体(蛍光体封止層24)の発光波長とが異なる場合、本実施形態の発光基板10は、各発光素子20が出射した際の光Lの束を、各発光素子20が出射した際の光Lの波長と異なる波長の光Lを含む光Lの束として上記励起光とともに照射する。例えば、本実施形態の発光基板10は、各発光素子20が出射した際の光Lの束を、各発光素子20が出射した際の光Lの波長よりも長い波長の光Lを含む光Lの束として上記励起光とともに照射する。
これに対して、蛍光体層36に含まれる蛍光体の発光波長と、発光素子20(CSP)におけるLED22を封止した(又は覆う)蛍光体(蛍光体封止層24)の発光波長とが同じ場合(同じ相関色温度の場合)、本実施形態の発光基板10は、各発光素子20が出射した際の光Lの束を、各発光素子20が出射した際の光Lの波長と同じ波長の光Lを含む光Lの束として上記励起光とともに照射する。
As described above, the light L emitted by each light emitting element 20 (the light L emitted radially by each light emitting element 20) is irradiated to the outside together with the excitation light via the plurality of optical paths as described above. .. Therefore, when the emission wavelength of the phosphor contained in the phosphor layer 36 and the emission wavelength of the phosphor (fluorescent encapsulation layer 24) that seals (or covers) the LED 22 in the light emitting element 20 (CSP) are different. In the light emitting substrate 10 of the present embodiment, the bundle of light L when each light emitting element 20 emits is used as a bundle of light L containing light L having a wavelength different from the wavelength of light L when each light emitting element 20 emits. Irradiate with the above excitation light. For example, the light emitting substrate 10 of the present embodiment contains light L having a wavelength longer than the wavelength of light L when each light emitting element 20 emits a bundle of light L when each light emitting element 20 emits light L. It is irradiated with the above-mentioned excitation light as a bundle of.
On the other hand, the emission wavelength of the phosphor contained in the phosphor layer 36 and the emission wavelength of the phosphor (fluorescent encapsulation layer 24) that seals (or covers) the LED 22 in the light emitting element 20 (CSP). In the same case (in the case of the same correlated color temperature), in the light emitting substrate 10 of the present embodiment, the bundle of light L when each light emitting element 20 emits is the same as the wavelength of light L when each light emitting element 20 emits. It is irradiated with the above-mentioned excitation light as a bundle of light L including light L having a wavelength.

以上が、本実施形態の発光基板10の発光動作についての説明である。 The above is a description of the light emitting operation of the light emitting substrate 10 of the present embodiment.

≪本実施形態の効果≫
次に、本実施形態の効果について図面を参照しながら説明する。
<< Effect of this embodiment >>
Next, the effect of this embodiment will be described with reference to the drawings.

<第1の効果>
第1の効果については、本実施形態を以下に説明する比較形態(図5参照)と比較して説明する。ここで、比較形態の説明において、本実施形態と同じ構成要素等を用いる場合は、その構成要素等に本実施形態の場合と同じ名称、符号等を用いることとする。図5は、比較形態の発光基板10Aの発光動作を説明するための図である。比較形態の発光基板10A(複数の発光素子20を搭載する基板30A)は、蛍光体層36を備えていない点以外は、本実施形態の発光基板10(蛍光体基板30)と同じ構成とされている。
<First effect>
The first effect will be described in comparison with the comparative embodiment (see FIG. 5) described below in this embodiment. Here, in the description of the comparative embodiment, when the same components and the like as in the present embodiment are used, the same names, codes and the like as in the case of the present embodiment are used for the components and the like. FIG. 5 is a diagram for explaining the light emitting operation of the light emitting substrate 10A in the comparative form. The light emitting substrate 10A of the comparative embodiment (the substrate 30A on which the plurality of light emitting elements 20 are mounted) has the same configuration as the light emitting substrate 10 (fluorescent substrate 30) of the present embodiment except that the phosphor layer 36 is not provided. ing.

比較形態の発光基板10Aの場合、各発光素子20から出射され、基板30Aの表面31に入射した光Lは、波長が変換されることなく反射又は散乱する。そのため、比較形態の基板30Aの場合、発光素子20が搭載された場合に発光素子20が発光する光と異なる発光色の光に調整することができない。すなわち、比較形態の発光基板10Aの場合、発光素子20が発光する光と異なる発光色の光に調整することができない。 In the case of the light emitting substrate 10A of the comparative form, the light L emitted from each light emitting element 20 and incident on the surface 31 of the substrate 30A is reflected or scattered without converting the wavelength. Therefore, in the case of the substrate 30A in the comparative form, it is not possible to adjust the light to a light emission color different from the light emitted by the light emitting element 20 when the light emitting element 20 is mounted. That is, in the case of the light emitting substrate 10A in the comparative form, it is not possible to adjust the light to a light emission color different from the light emitted by the light emitting element 20.

これに対して、本実施形態の場合、絶縁層32の厚み方向から見て、絶縁層32の表面31であって、各発光素子20との各接合面34A1の周囲には蛍光体層36が配置されている。そのため、各発光素子20から半球状に放射された光Lの一部は、蛍光体層36に入射して、蛍光体層36により波長変換されて、外部に照射される。この場合、各発光素子20から放射状に出射された光Lの一部は、蛍光体層36に入射して、蛍光体層36に含まれる蛍光体を励起させ、励起光を発生させる。 On the other hand, in the case of the present embodiment, when viewed from the thickness direction of the insulating layer 32, the phosphor layer 36 is formed on the surface 31 of the insulating layer 32 and around each bonding surface 34A1 with each light emitting element 20. Have been placed. Therefore, a part of the light L radiated hemispherically from each light emitting element 20 is incident on the phosphor layer 36, is wavelength-converted by the phosphor layer 36, and is irradiated to the outside. In this case, a part of the light L radially emitted from each light emitting element 20 is incident on the phosphor layer 36 to excite the phosphor contained in the phosphor layer 36 and generate the excitation light.

したがって、本実施形態の蛍光体基板30によれば、発光素子20が搭載された場合に、蛍光体基板30から発光される光Lを発光素子20が発光する光Lと異なる発光色の光に調整することができる。これに伴い、本実施形態の発光基板10によれば、蛍光体基板30から発光される光Lを発光素子20が発光する光Lと異なる発光色の光Lに調整することができる。
なお、蛍光体層36に含まれる蛍光体の発光波長と、発光素子20(CSP)におけるLED22を封止した(又は覆う)蛍光体(蛍光体封止層24)の発光波長とが同じ場合(同じ相関色温度の場合)、本実施形態の発光基板10は、各発光素子20が出射した際の光Lの束を、各発光素子20が出射した際の光Lの波長と同じ波長の光Lを含む光Lの束として上記励起光とともに照射する。この場合、搭載される発光素子20の色度ばらつきを蛍光体層36により緩和する効果も発現できる。
Therefore, according to the phosphor substrate 30 of the present embodiment, when the light emitting element 20 is mounted, the light L emitted from the phosphor substrate 30 is converted into light having a different emission color from the light L emitted by the light emitting element 20. Can be adjusted. Along with this, according to the light emitting substrate 10 of the present embodiment, the light L emitted from the phosphor substrate 30 can be adjusted to the light L having a light emitting color different from the light L emitted by the light emitting element 20.
When the emission wavelength of the phosphor contained in the phosphor layer 36 and the emission wavelength of the phosphor (fluorescent encapsulation layer 24) that seals (or covers) the LED 22 in the light emitting element 20 (CSP) are the same ( (In the case of the same correlated color temperature), the light emitting substrate 10 of the present embodiment has a bundle of light L when each light emitting element 20 emits light having the same wavelength as the wavelength of light L when each light emitting element 20 emits. It is irradiated with the above-mentioned excitation light as a bundle of light L containing L. In this case, the effect of alleviating the variation in chromaticity of the mounted light emitting element 20 by the phosphor layer 36 can also be exhibited.

<第2の効果>
比較形態の場合、図5に示されるように、各発光素子20の配置間隔に起因して外部に照射される光Lに斑が発生する。ここで、光Lの斑が大きいほど、グレアが大きいという。
これに対して、本実施形態の場合、図2Bに示されるように、各接合面34A1の周囲が(全周に亘って)蛍光体層36に囲まれたうえで、さらに隣接する発光素子20同士の間にも蛍光体層36が設けられている。そのため、各接合面34A1の周囲(各発光素子20の周囲)からも励起光が発光される。
したがって、本実施形態によれば、比較形態に比べて、グレアを小さくすることができる。
特に、本効果は、蛍光体層36が絶縁層32の全面に亘って設けられている場合、具体的には、絶縁層32の表面31における蛍光体層36が配置されている領域が表面13の80%以上の領域のような場合に有効である。
また、本実施形態の蛍光体層36は、図1Cに示されるように、隣接する発光素子20に対応する対向面36Aを有する。そのため、本実施形態は、例えば、蛍光体層36上に発光素子20が配置されている場合(図示省略)に比べて、グレアを低減することができる。
<Second effect>
In the case of the comparative form, as shown in FIG. 5, spots are generated in the light L irradiated to the outside due to the arrangement interval of each light emitting element 20. Here, it is said that the larger the spot of light L, the larger the glare.
On the other hand, in the case of the present embodiment, as shown in FIG. 2B, each bonding surface 34A1 is surrounded by the phosphor layer 36 (over the entire circumference), and the light emitting element 20 is further adjacent to the bonding element 20. A phosphor layer 36 is also provided between the two. Therefore, the excitation light is also emitted from the periphery of each joint surface 34A1 (periphery of each light emitting element 20).
Therefore, according to the present embodiment, the glare can be reduced as compared with the comparative embodiment.
In particular, in this effect, when the phosphor layer 36 is provided over the entire surface of the insulating layer 32, specifically, the region of the surface 31 of the insulating layer 32 where the fluorescent layer 36 is arranged is the surface 13. It is effective in the case of 80% or more of the area.
Further, as shown in FIG. 1C, the phosphor layer 36 of the present embodiment has a facing surface 36A corresponding to the adjacent light emitting element 20. Therefore, in this embodiment, glare can be reduced as compared with the case where the light emitting element 20 is arranged on the phosphor layer 36 (not shown), for example.

<第3の効果>
また、本実施形態の場合、例えば、蛍光体層36に含まれる蛍光体をEuを含有するCASN蛍光体とし、蛍光体層36をCu製の配線部分34B上に設けている。そのため、例えば、各発光素子20が白色系の光Lを出射した場合に、例えば、蛍光体層36に含まれるCASN蛍光体からの励起光は、下層電極を構成しているCuによる反射により発光効率が向上している(本実施形態の構成では、Cuの光反射効果がある)。そして、本実施形態では、当該効果により、白色系の光Lをより暖かい色系の光L(相関色温度が低温側にシフトした色)に調整することができる。この場合、発光素子20の白色系光に暖色系光を加味することができ、特殊演色係数R9値を上げることができる。本効果は、YAG系白色光(黄色蛍光体)を用いた擬似白色に特に有効となる。
<Third effect>
Further, in the case of the present embodiment, for example, the phosphor contained in the phosphor layer 36 is a CASN phosphor containing Eu, and the phosphor layer 36 is provided on the wiring portion 34B made of Cu. Therefore, for example, when each light emitting element 20 emits white light L, for example, the excitation light from the CASN phosphor contained in the phosphor layer 36 emits light due to reflection by Cu constituting the lower layer electrode. The efficiency is improved (in the configuration of this embodiment, there is a light reflection effect of Cu). Then, in the present embodiment, the white light L can be adjusted to a warmer color light L (a color in which the correlated color temperature is shifted to the lower temperature side) by the effect. In this case, warm color light can be added to the white light of the light emitting element 20, and the special color rendering coefficient R9 value can be increased. This effect is particularly effective for pseudo-white using YAG-based white light (yellow phosphor).

<第4の効果>
また、本実施形態の第3工程(図3C参照)では、一例として、蛍光体層36の1/3の厚みの蛍光体パターン361、362、363を3回積層させて蛍光体層36を配置する。
したがって、本実施形態によれば、多層構造の蛍光体層36を備える蛍光体基板30を製造することができる。また、別の見方をすると、本実施形態によれば、第3工程での蛍光体パターン361等の積層回数を調整することで、蛍光体層36の膜厚を調整することができる。
<Fourth effect>
Further, in the third step of the present embodiment (see FIG. 3C), as an example, the fluorescent material patterns 361, 362, and 363 having a thickness of 1/3 of the fluorescent material layer 36 are laminated three times to arrange the fluorescent material layer 36. do.
Therefore, according to the present embodiment, the phosphor substrate 30 provided with the phosphor layer 36 having a multilayer structure can be manufactured. From another point of view, according to the present embodiment, the film thickness of the fluorescent material layer 36 can be adjusted by adjusting the number of times the fluorescent material pattern 361 and the like are laminated in the third step.

<第5の効果>
また、本実施形態の発光基板10の製造方法では、第4工程(蛍光体層配置工程)は、第3工程(はんだ配置工程)の後に行われる(図3C〜図3E参照)。ここで、はんだSPの配置のタイミングは、例えば、第4工程の後の第5工程時(複数の発光素子20を搭載する工程時)も考えられる。
しかしながら、本実施形態のように、第4工程が第3工程の後に行われるため、はんだSPを印刷により簡単に配置することができる。また、回路パターン層34の表面に形成された各溝34Eは、はんだSPのはんだ流れ止めとして機能する点で有効である。
<Fifth effect>
Further, in the method for manufacturing the light emitting substrate 10 of the present embodiment, the fourth step (fluorescent layer placement step) is performed after the third step (solder placement step) (see FIGS. 3C to 3E). Here, the timing of arranging the solder SP may be, for example, at the time of the fifth step after the fourth step (at the time of the step of mounting the plurality of light emitting elements 20).
However, since the fourth step is performed after the third step as in the present embodiment, the solder SP can be easily arranged by printing. Further, each groove 34E formed on the surface of the circuit pattern layer 34 is effective in that it functions as a solder flow stop for the solder SP.

以上が、本実施形態の効果についての説明である。 The above is the description of the effect of this embodiment.

以上のとおり、本発明について前述の実施形態を例として説明したが、本発明は前述の実施形態に限定されるものではない。本発明の技術的範囲には、例えば、下記のような形態(変形例)も含まれる。 As described above, the present invention has been described by way of the above-described embodiment as an example, but the present invention is not limited to the above-mentioned embodiment. The technical scope of the present invention also includes, for example, the following forms (modifications).

例えば、本実施形態の第4工程(図3D参照)の説明では、蛍光体層36は、例えば、転写により、蛍光体層36の1/3の厚みの蛍光体パターン361、362、363を3回積層させて蛍光体層36を形成するとして説明した。しかしながら、蛍光体層36は、本実施形態と異なる方法により形成されてもよい。
例えば、図6Aに示される変形例(第1変形例)のように、第4工程において、ディスペンサーDP(吐出部の一例)を絶縁層32に相対的に移動させながら、蛍光体層36の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、ディスペンサーDPに蛍光体を含む液体LQを吐出させて、蛍光体層36を形成するようにしてもよい。
また、例えば、図6Bに示される変形例(第2変形例)のように、第4工程において、液滴吐出ヘッドIJH(吐出部の一例)を絶縁層32に相対的に移動させながら、蛍光体層36の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、液滴吐出ヘッドIJHに蛍光体を含む液滴DLを吐出させて、蛍光体層36を形成するようにしてもよい。
また、第1変形例及び第2変形例とは異なり、第4工程において、蛍光体層36の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、1/nの厚みの蛍光体パターンをn回印刷することにより、蛍光体層36を形成するようにしてもよい。この変形例の場合の印刷方法としては、例えばスクリーン印刷による方法がある。ただし、上記蛍光体パターンをn回印刷することにより蛍光体層36を形成することができれば、具体的な印刷方法はスクリーン印刷による方法でなくてもよい。
For example, in the description of the fourth step (see FIG. 3D) of the present embodiment, the fluorescent layer 36 has 3 fluorescent patterns 361, 362, and 363 having a thickness of 1/3 of the fluorescent layer 36, for example, by transfer. It has been described that the phosphor layer 36 is formed by laminating the phosphor layer 36 times. However, the fluorescent layer 36 may be formed by a method different from that of the present embodiment.
For example, as in the modified example (first modified example) shown in FIG. 6A, in the fourth step, the dispenser DP (an example of the ejection portion) is relatively moved to the insulating layer 32 while moving the dispenser DP (an example of the ejection portion) to the insulating layer 32. The liquid LQ containing the phosphor may be discharged to the dispenser DP to form the phosphor layer 36 so that the phosphor patterns having a thickness of / n (n ≧ 2) are laminated n times.
Further, for example, as in the modification shown in FIG. 6B (second modification), in the fourth step, the droplet ejection head IJH (an example of the ejection portion) is relatively moved to the insulating layer 32 while fluorescing. The droplet DL containing the phosphor is ejected to the droplet ejection head IJH to form the phosphor layer 36 so that the phosphor patterns having a thickness of 1 / n (n ≧ 2) of the body layer 36 are laminated n times. You may try to do it.
Further, unlike the first modification and the second modification, in the fourth step, the phosphor pattern having a thickness of 1 / n (n ≧ 2) of the phosphor layer 36 is laminated n times so as to be 1 / n. The fluorescent material layer 36 may be formed by printing the fluorescent material pattern having the same thickness n times. As a printing method in the case of this modification, for example, there is a method by screen printing. However, if the fluorescent material layer 36 can be formed by printing the fluorescent material pattern n times, the specific printing method does not have to be a screen printing method.

また、本実施形態の発光基板10の製造方法では、第4工程(蛍光体層配置工程)の後に第5工程(発光素子20の接合工程)を行うとして説明した。しかしながら、図6Bに示される第2変形例のように蛍光体層配置工程を液滴吐出ヘッドIJHを用いて行う場合、図6Cに示される変形例(第3変形例)の場合のように、第5工程の後に、第4工程を行ってもよい。このように、第4工程を第5工程の前後のいずれのタイミングでも行える点で、第2変形例は有効である。また、この点は第1変形例の場合にもいえる。
なお、図6Aの第1変形例のディスペンサーDP又は図6Bの第2変形例の液滴吐出ヘッドIJHを用いて第3工程を場合、例えば、部分的に蛍光体層36の膜厚を調整できる点で有効といえる。
Further, in the method for manufacturing the light emitting substrate 10 of the present embodiment, it has been described that the fifth step (bonding step of the light emitting element 20) is performed after the fourth step (fluorescent layer arrangement step). However, when the phosphor layer arrangement step is performed using the droplet ejection head IJH as in the second modification shown in FIG. 6B, as in the case of the modification (third modification) shown in FIG. 6C. After the fifth step, the fourth step may be performed. As described above, the second modification is effective in that the fourth step can be performed at any timing before and after the fifth step. This point can also be said for the first modification.
In the case of the third step using the dispenser DP of the first modification of FIG. 6A or the droplet ejection head IJH of the second modification of FIG. 6B, for example, the film thickness of the phosphor layer 36 can be partially adjusted. It can be said that it is effective in terms of points.

また、本実施形態の説明では、発光素子20の一例をCSPであるとした。しかしながら、発光素子20の一例はCSP以外でもよい。例えば、単にフリップチップを搭載したものでもよい。また、COBデバイスの基板自身に応用することもできる。 Further, in the description of this embodiment, an example of the light emitting element 20 is assumed to be a CSP. However, an example of the light emitting element 20 may be other than the CSP. For example, it may simply be equipped with a flip chip. It can also be applied to the substrate itself of a COB device.

また、本実施形態の説明では、蛍光体基板30には複数の発光素子20が搭載され、発光基板10は複数の発光素子20を備えているとした。しかしながら、前述の第1及び第4の効果の説明のメカニズムを考慮すると、発光素子20が1つであっても第1の効果を奏することは明らかである。したがって、蛍光体基板30に搭載される発光素子20の数は少なくとも1つ以上であればよい。また、発光基板10に搭載されている発光素子20は少なくとも1つ以上であればよい。これに伴い、接合面34A1及び非接合面34B1も少なくとも1つ以上であればよい。 Further, in the description of the present embodiment, it is assumed that the phosphor substrate 30 is equipped with a plurality of light emitting elements 20 and the light emitting substrate 10 is provided with a plurality of light emitting elements 20. However, considering the mechanism for explaining the first and fourth effects described above, it is clear that even one light emitting element 20 exerts the first effect. Therefore, the number of light emitting elements 20 mounted on the phosphor substrate 30 may be at least one. Further, the number of light emitting elements 20 mounted on the light emitting substrate 10 may be at least one or more. Along with this, at least one joint surface 34A1 and one non-joint surface 34B1 may be used.

また、本実施形態の説明では、蛍光体基板30の裏面33に裏面パターン層38が備えられているとした(図1B参照)。しかしながら、前述の第1及び第4の効果の説明のメカニズムを考慮すると、蛍光体基板30の裏面33に裏面パターン層38が備えられていなくても第1の効果を奏することは明らかである。したがって、裏面33に裏面パターン層38がない点のみ本実施形態の蛍光体基板30及び発光基板10と異なる形態であっても、当該形態は本発明の技術的範囲に属するといえる。 Further, in the description of the present embodiment, it is assumed that the back surface pattern layer 38 is provided on the back surface 33 of the phosphor substrate 30 (see FIG. 1B). However, considering the mechanism for explaining the first and fourth effects described above, it is clear that the first effect is exhibited even if the back surface 33 of the phosphor substrate 30 is not provided with the back surface pattern layer 38. Therefore, even if the form is different from the phosphor substrate 30 and the light emitting substrate 10 of the present embodiment only in that the back surface 33 does not have the back surface pattern layer 38, it can be said that the embodiment belongs to the technical scope of the present invention.

また、本実施形態の説明では、蛍光体基板30には複数の発光素子20が搭載されているとした。しかしながら、前述の第4の効果の説明のメカニズムを考慮すると、電子部品の一例は、発光素子20でなくてもよい。 Further, in the description of the present embodiment, it is assumed that a plurality of light emitting elements 20 are mounted on the phosphor substrate 30. However, considering the mechanism for explaining the fourth effect described above, the example of the electronic component does not have to be the light emitting device 20.

また、本実施形態の説明では、回路基板の一例である蛍光体基板30は、蛍光体層36を備えているとした。しかしながら、前述の第4の効果の説明のメカニズムを考慮すると、電子部品の一例が発光素子20でない場合、回路基板に蛍光体層36を備えていなくてもよい。 Further, in the description of the present embodiment, it is assumed that the phosphor substrate 30, which is an example of the circuit board, includes the phosphor layer 36. However, considering the mechanism for explaining the fourth effect described above, when the example of the electronic component is not the light emitting element 20, the circuit board may not have the phosphor layer 36.

また、本実施形態の説明では、蛍光体層36は、絶縁層32及び回路パターン層34の表面31における、複数の電極対34A以外の部分に配置されているとした(図2B参照)。しかしながら、前述の第1及び第4の効果の説明のメカニズムを考慮すると、蛍光体基板30の表面31における複数の電極対34A以外の部分の全域に亘って配置されていなくても第1及び第4の効果を奏することは明らかである。したがって、本実施形態の場合と異なる表面31の範囲に蛍光体層36が配置されている点のみ本実施形態の蛍光体基板30及び発光基板10と異なる形態であっても、当該形態は本発明の技術的範囲に属するといえる。
なお、本実施形態の場合、隣接する発光素子20同士の間に蛍光体層36が設けられている(図2B)。また、蛍光体層36のバインダーは、例えばソルダーレジストに含まれるバインダーと同等の絶縁性を有する。すなわち、本実施形態の場合、蛍光体層36がソルダーレジストの機能を果たす。
Further, in the description of the present embodiment, it is assumed that the phosphor layer 36 is arranged on the surface 31 of the insulating layer 32 and the circuit pattern layer 34 other than the plurality of electrode pairs 34A (see FIG. 2B). However, considering the mechanism for explaining the first and fourth effects described above, the first and first are not arranged over the entire area other than the plurality of electrode pairs 34A on the surface 31 of the phosphor substrate 30. It is clear that the effect of 4 is achieved. Therefore, even if the form is different from the phosphor substrate 30 and the light emitting substrate 10 of the present embodiment only in that the phosphor layer 36 is arranged in the range of the surface 31 different from that of the present embodiment, the present invention is the present invention. It can be said that it belongs to the technical scope of.
In the case of this embodiment, the phosphor layer 36 is provided between the adjacent light emitting elements 20 (FIG. 2B). Further, the binder of the phosphor layer 36 has an insulating property equivalent to that of the binder contained in, for example, a solder resist. That is, in the case of the present embodiment, the phosphor layer 36 functions as a solder resist.

また、本実施形態の説明では、蛍光体基板30及び発光基板10を製造するに当たり、利昌工業株式会社製のCS−3305AをマザーボードMBとして用いると説明した。しかしながら、これは一例であり、異なるマザーボードMBを用いてもよい。 Further, in the description of the present embodiment, it has been described that CS-3305A manufactured by Toshimasa Kogyo Co., Ltd. is used as the motherboard MB in manufacturing the phosphor substrate 30 and the light emitting substrate 10. However, this is just an example, and different motherboard MBs may be used.

なお、本実施形態の発光基板10(その変形例も含む)は、他の構成要素と組み合せて、照明装置に応用することができる。この場合における他の構成要素は、発光基板10の発光素子20を発光させるための電力を供給する電源等である。 The light emitting substrate 10 of the present embodiment (including a modification thereof) can be applied to a lighting device in combination with other components. Another component in this case is a power source or the like that supplies electric power for causing the light emitting element 20 of the light emitting substrate 10 to emit light.

この出願は、2019年2月21日に出願された日本出願特願2019−029205号を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority on the basis of Japanese Application Japanese Patent Application No. 2019-029205 filed on February 21, 2019 and incorporates all of its disclosures herein.

10 発光基板(実装基板の一例)
20 発光素子
30 蛍光体基板(回路基板の一例)
31 表面(一面の一例)
32 絶縁層(絶縁基板の一例)
33 裏面
34 回路パターン層
34A 電極対
34A1 接合面
34B 配線部分
34B1 非接合面
34E 溝
36 蛍光体層
36E 対向面
38 裏面パターン層
DP ディスペンサー(吐出部の一例)
IJH 液滴吐出ヘッド(吐出部の一例)
L 光
MB マザーボード
SP はんだボール、はんだ
10 Light emitting board (example of mounting board)
20 Light emitting element 30 Fluorescent board (example of circuit board)
31 Surface (an example of one surface)
32 Insulation layer (example of insulation substrate)
33 Back side 34 Circuit pattern layer 34A Electrode pair 34A1 Bonding surface 34B Wiring part 34B1 Non-joining surface 34E Groove 36 Fluorescent layer 36E Facing surface 38 Back side pattern layer DP dispenser (example of ejection part)
IJH Droplet Discharge Head (Example of Discharge Unit)
L Hikari MB Motherboard SP Solder Ball, Solder

Claims (20)

一面に少なくとも1つの発光素子が搭載される蛍光体基板であって、
絶縁基板と、
前記絶縁基板の一面に配置され、前記絶縁基板の厚み方向外側に向く平面を有し、前記平面の一部を前記少なくとも1つの電子部品と接合する少なくとも1つの接合面として接合される回路パターン層と、
少なくとも前記平面における前記少なくとも1つの接合面以外の部分とされる少なくとも1つの非接合面に配置され、前記少なくとも1つの発光素子の発光を励起光としたときの発光ピーク波長が可視光領域にある蛍光体を含む蛍光体層と、
を備え、
前記蛍光体層は、積層構造とされている、
蛍光体基板。
A phosphor substrate on which at least one light emitting element is mounted on one surface.
Insulated board and
A circuit pattern layer arranged on one surface of the insulating substrate, having a plane facing outward in the thickness direction of the insulating substrate, and being joined as at least one joining surface for joining a part of the plane to the at least one electronic component. When,
The emission peak wavelength is located in the visible light region when it is arranged on at least one non-junction surface which is a portion other than the at least one junction surface in the plane and the emission of the at least one light emitting element is used as excitation light. A phosphor layer containing a phosphor and
Equipped with
The phosphor layer has a laminated structure.
Fluorescent substrate.
前記少なくとも1つの発光素子は、複数の発光素子とされ、
前記少なくとも1つの接合面は、複数の接合面とされ、
前記少なくとも1つの非接合面は、複数の非接合面とされ、
前記複数の発光素子は、前記絶縁基板の一面に並べられ、それぞれ、前記複数の接合面に接合されて搭載される、
請求項1に記載の蛍光体基板。
The at least one light emitting element is a plurality of light emitting elements.
The at least one joint surface is a plurality of joint surfaces.
The at least one non-bonded surface is a plurality of non-bonded surfaces.
The plurality of light emitting elements are arranged on one surface of the insulating substrate, and each of the plurality of light emitting elements is bonded and mounted on the plurality of bonding surfaces.
The fluorescent material substrate according to claim 1.
前記回路パターン層には、前記少なくとも1つの接合面と前記平面における前記少なくとも1つの接合面以外の部分とされる少なくとも1つの非接合面とを隔てる少なくとも1つの溝が形成されている、
請求項1に記載の蛍光体基板。
The circuit pattern layer is formed with at least one groove separating the at least one junction surface and at least one non-junction surface which is a portion other than the at least one junction surface in the plane.
The fluorescent material substrate according to claim 1.
前記少なくとも1つの発光素子は、複数の発光素子とされ、
前記少なくとも1つの接合面は、複数の接合面とされ、
前記少なくとも1つの非接合面は、複数の非接合面とされ、
前記少なくとも1つの溝は、複数の溝とされ、
前記複数の発光素子は、前記絶縁基板の一面に並べられ、それぞれ、前記複数の接合面に接合されて搭載される、
請求項3に記載の蛍光体基板。
The at least one light emitting element is a plurality of light emitting elements.
The at least one joint surface is a plurality of joint surfaces.
The at least one non-bonded surface is a plurality of non-bonded surfaces.
The at least one groove is a plurality of grooves.
The plurality of light emitting elements are arranged on one surface of the insulating substrate, and each of the plurality of light emitting elements is bonded and mounted on the plurality of bonding surfaces.
The fluorescent material substrate according to claim 3.
請求項1〜4のいずれか1項に記載の蛍光体基板と、
前記少なくとも1つの接合面に接合されている少なくとも1つの発光素子と、
を備える発光基板。
The fluorescent substrate according to any one of claims 1 to 4,
With at least one light emitting element bonded to the at least one bonding surface,
A light emitting board.
前記蛍光体層における前記厚み方向外側に向く面の前記厚み方向の位置は、前記少なくとも1つの発光素子における前記厚み方向外側に向く面の位置よりも前記厚み方向内側に位置している、
請求項5に記載の発光基板。
The position of the surface of the phosphor layer facing outward in the thickness direction in the thickness direction is located inside the thickness direction of the position of the surface of the at least one light emitting element facing outward in the thickness direction.
The light emitting substrate according to claim 5.
前記蛍光体層における前記厚み方向外側に向く面の前記厚み方向の位置は、前記少なくとも1つの発光素子の厚み方向の中央の位置又は当該位置よりも前記厚み方向内側に位置している、
請求項5に記載の発光基板。
The position of the surface of the phosphor layer facing outward in the thickness direction in the thickness direction is located at the center of the at least one light emitting element in the thickness direction or inside the position in the thickness direction.
The light emitting substrate according to claim 5.
請求項5〜7のいずれか1項に記載の発光基板と、
前記発光素子を発光させるための電力を供給する電源と、
を備える照明装置。
The light emitting substrate according to any one of claims 5 to 7.
A power source that supplies electric power for causing the light emitting element to emit light,
Lighting device equipped with.
絶縁基板、回路パターン層、及び、少なくとも1つの発光素子の発光を励起光としたときの発光ピーク波長が可視光領域にある蛍光体を含む蛍光体層を備える蛍光体基板の製造方法であって、
前記絶縁基板の一面に、配線パターン層を形成するパターン層形成工程と、
前記配線パターン層の一部に前記蛍光体層を形成する蛍光体層形成工程と、
を含み、
前記蛍光体層形成工程では、前記蛍光体層の厚みよりも薄い蛍光体パターンを積層させて、前記蛍光体層を形成する、
蛍光体基板の製造方法。
A method for manufacturing a phosphor substrate including an insulating substrate, a circuit pattern layer, and a phosphor layer containing a phosphor whose emission peak wavelength is in the visible light region when the emission of at least one light emitting element is used as excitation light. ,
A pattern layer forming step of forming a wiring pattern layer on one surface of the insulating substrate,
A fluorescent material layer forming step of forming the fluorescent material layer on a part of the wiring pattern layer,
Including
In the phosphor layer forming step, a fluorescent material pattern thinner than the thickness of the fluorescent material layer is laminated to form the fluorescent material layer.
A method for manufacturing a fluorescent substrate.
前記蛍光体層形成工程では、転写により、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンをn回積層させて前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。
In the fluorescent layer forming step, the fluorescent layer having a thickness of 1 / n (n ≧ 2) of the fluorescent layer is laminated n times to form the fluorescent layer by transfer.
The method for manufacturing a fluorescent substrate according to claim 9.
前記蛍光体層形成工程では、液体を吐出する吐出部を前記絶縁基板に相対的に移動させながら、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、前記吐出部に前記蛍光体を含む液体を吐出させて、前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。
In the phosphor layer forming step, the phosphor patterns having a thickness of 1 / n (n ≧ 2) of the phosphor layer are laminated n times while the ejection portion for discharging the liquid is relatively moved to the insulating substrate. As described above, the liquid containing the fluorescent substance is discharged to the discharging portion to form the fluorescent substance layer.
The method for manufacturing a fluorescent substrate according to claim 9.
前記蛍光体層形成工程では、液滴を吐出する吐出部を前記絶縁基板に相対的に移動させながら、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンがn回積層するように、前記吐出部に前記蛍光体を含む液体を液滴として吐出させて、前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。
In the phosphor layer forming step, the phosphor pattern having a thickness of 1 / n (n ≧ 2) of the phosphor layer is laminated n times while the ejection portion for ejecting droplets is relatively moved to the insulating substrate. As described above, the liquid containing the fluorescent substance is discharged as droplets to the discharging portion to form the fluorescent substance layer.
The method for manufacturing a fluorescent substrate according to claim 9.
前記蛍光体層形成工程では、印刷により、前記蛍光体層の1/n(n≧2)の厚みの蛍光体パターンをn回積層させて前記蛍光体層を形成する、
請求項9に記載の蛍光体基板の製造方法。
In the phosphor layer forming step, the phosphor layer having a thickness of 1 / n (n ≧ 2) of the phosphor layer is laminated n times to form the phosphor layer by printing.
The method for manufacturing a fluorescent substrate according to claim 9.
前記印刷は、スクリーン印刷とされる、
請求項13に記載の蛍光体基板の製造方法。
The printing is referred to as screen printing.
The method for manufacturing a fluorescent substrate according to claim 13.
前記蛍光体層形成工程では、前記蛍光体層の厚みよりも薄い蛍光体パターンを積層させて、前記蛍光体層の厚みの半分以下の厚みの前記蛍光体層を形成する、
請求項9〜14のいずれか1項に記載の蛍光体基板の製造方法。
In the phosphor layer forming step, fluorescent patterns thinner than the thickness of the phosphor layer are laminated to form the phosphor layer having a thickness of half or less of the thickness of the phosphor layer.
The method for manufacturing a fluorescent substrate according to any one of claims 9 to 14.
前記パターン層形成工程の後、かつ、前記蛍光体層形成工程の前に行われる工程であって、前記回路パターン層における前記絶縁基板の厚み方向外側に向く平面に少なくとも1つの溝を形成する溝形成工程と、
前記蛍光体層形成工程の前に行われる工程であって、前記平面における前記少なくとも1つの溝を挟んで一方の部分に少なくとも一つの発光素子を接合させるためのはんだを配置するはんだ配置工程と
を含む請求項9〜15のいずれか1項に記載の蛍光体基板の製造方法。
A groove formed in a plane facing outward in the thickness direction of the insulating substrate in the circuit pattern layer, which is a step performed after the pattern layer forming step and before the phosphor layer forming step. The formation process and
A step performed before the phosphor layer forming step, which is a solder arranging step of arranging solder for joining at least one light emitting element to one portion of the at least one groove on the plane. The method for manufacturing a phosphor substrate according to any one of claims 9 to 15, which comprises.
請求項9〜16のいずれか1項に記載の蛍光体基板の製造方法と、
前記回路パターン層の一部に前記少なくとも1つの発光素子を接合する接合工程と、
を含む発光基板の製造方法。
The method for manufacturing a fluorescent substrate according to any one of claims 9 to 16.
A joining step of joining the at least one light emitting element to a part of the circuit pattern layer,
A method for manufacturing a light emitting substrate including.
請求項16に記載の蛍光体基板の製造方法と、
前記回路パターン層の一部であって、前記平面における前記少なくとも1つの溝を挟んで他方の部分に前記少なくとも1つの発光素子を接合する接合工程と、
を含む発光基板の製造方法。
The method for manufacturing a fluorescent substrate according to claim 16.
A joining step of joining the at least one light emitting element to a part of the circuit pattern layer, sandwiching the at least one groove in the plane, and joining the at least one light emitting element to the other portion.
A method for manufacturing a light emitting substrate including.
前記接合工程は、前記蛍光体層形成工程の後に行われる、
請求項17又は18に記載の発光基板の製造方法。
The joining step is performed after the phosphor layer forming step.
The method for manufacturing a light emitting substrate according to claim 17 or 18.
前記接合工程では、前記はんだにフラックスを塗布してから前記はんだを溶融させて前記他方の部分に前記少なくとも1つの発光素子を接合させる、
請求項18又は19に記載の発光基板の製造方法。
In the joining step, flux is applied to the solder and then the solder is melted to join the at least one light emitting element to the other portion.
The method for manufacturing a light emitting substrate according to claim 18 or 19.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006259546A (en) * 2005-03-18 2006-09-28 Kyocera Corp Liquid crystal display device
US20170084799A1 (en) * 2014-06-02 2017-03-23 3M Innovative Properties Company Led with remote phosphor and shell reflector
WO2017077739A1 (en) * 2015-11-04 2017-05-11 シャープ株式会社 Luminescent material, light-emitting device, illuminator, and process for producing luminescent material

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254775A (en) * 1994-03-16 1995-10-03 Sankyo Seiki Mfg Co Ltd Circuit board
ATE537564T1 (en) * 2004-10-13 2011-12-15 Panasonic Corp LUMINESCENT LIGHT SOURCE, METHOD FOR PRODUCING SAME AND LIGHT EMITTING DEVICE
KR100600411B1 (en) * 2005-08-26 2006-07-19 엘지전자 주식회사 Light emitting device package and method for fabricating the same
JP5089212B2 (en) * 2007-03-23 2012-12-05 シャープ株式会社 LIGHT EMITTING DEVICE, LED LAMP USING THE SAME, AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE
JP5989268B2 (en) * 2015-02-18 2016-09-07 日東電工株式会社 Phosphor ceramics, sealed optical semiconductor element, circuit board, optical semiconductor device, and light emitting device
CN106163113A (en) 2015-03-23 2016-11-23 李玉俊 LED installs lamp bead circuit board light-reflection layer processing technology
CN106856220B (en) * 2015-12-08 2020-03-06 上海芯元基半导体科技有限公司 Flip LED device packaged in wafer level, and segmentation unit and manufacturing method thereof
CN108072999A (en) * 2016-11-15 2018-05-25 迎辉科技股份有限公司 Quantum structure light emitting module
TW201901989A (en) * 2017-05-25 2019-01-01 凃中勇 Light-emitting diode package component and method of fabricating the same, and multiple color temperature illumination device with LED package component including a wavelength conversion layer and a flip-chip LED die that has a light-emitting body and two electrode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006259546A (en) * 2005-03-18 2006-09-28 Kyocera Corp Liquid crystal display device
US20170084799A1 (en) * 2014-06-02 2017-03-23 3M Innovative Properties Company Led with remote phosphor and shell reflector
WO2017077739A1 (en) * 2015-11-04 2017-05-11 シャープ株式会社 Luminescent material, light-emitting device, illuminator, and process for producing luminescent material

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