JPWO2020160477A5

JPWO2020160477A5 -

Info

Publication number: JPWO2020160477A5
Application number: JP2021544930A
Authority: JP
Publication date: 2022-12-28

Claims

A test device,
one or more printed circuit boards (PCBs);
at least one interface coupled to the one or more PCBs;
a controller coupled to the at least one interface;
The controller establishes a single-lane or multi-lane high-speed input/output (I/O) link for a device under test (DUT), and the test equipment , a test apparatus configured to evaluate electrical margins of said single-lane or multi-lane high-speed I/O link.

The at least one interface is connected to at least one test fixture for evaluating electrical margins of a DUT's single-lane or multi-lane high-speed I/O link in one or both of the Tx and Rx directions. 2. The testing device of claim 1, comprising at least one lane configured to:

The at least one lane has a plurality of lanes, and the controller supports a plurality of different protocols and the roles of different devices for testing a plurality of different devices with the test apparatus, each operating according to a different protocol. and the test apparatus of claim 2, configured to provide options to configure multiple lanes for multiple different protocols.

3. The plurality of lanes are connected to at least one test fixture and configured to evaluate electrical margins of one or more multi-lane high speed I/O links in motherboards and add-in cards. 3 test equipment.

2. The test apparatus of claim 1, wherein said single-lane or multi-lane high-speed I/O link of said DUT is a fully operational, normally available link with no special test modes.

The one or more PCBs include an add-in card PCB, the DUT is a motherboard, the add-in cards are plugged into connectors on the motherboard, and the single-lane or multi-lane high-speed I/O 2. The test apparatus of claim 1, configured to implement a physical layer and a link logical layer of each lane of an O-link.

The controller is configured to evaluate electrical margins of the single-lane or multi-lane high-speed I/O link by being configured to introduce an adjustable stress to at least a margin test transmitter. 2. The test apparatus of claim 1, wherein said adjustable stress includes one or more of eye width opening reduction and eye height opening reduction.

The single-lane or multi-lane high-speed I by the controller being configured to introduce a reduction in eye width opening by introducing jitter , noise or differential noise into at least the margin test transmitter. /O link electrical margin, wherein said jitter , noise or differential noise introduction is applied simultaneously to all lanes of said single lane or multi-lane high speed I/O link. 8. The test apparatus according to claim 7 , wherein it is possible to select independently applied to each lane of the single-lane or multi-lane high-speed I/O link.

A method for testing electrical margins of a device under test (DUT), comprising:
establishing a multi-lane high speed I/O link for the DUT by a tester;
A process of evaluating electrical margins in one or both of the transmit (Tx) and receive (Rx) directions for each high speed input/output (I/O) lane of the multi-lane high speed I/O link by the test equipment. A method of providing and .

The process of evaluating the electrical margin includes the process of introducing an adjustable stress to a margin test transmitter of the multi-lane high-speed I/O link, the adjustable stress including the single-lane Or eye narrowing jitter introduction applied simultaneously to all lanes of a multi-lane high speed I/O link or applied independently to each lane of the above single-lane or multi-lane high speed I/O link 10. The method of claim 9 , wherein there are other ways or ways to reduce the eye height.

The process of evaluating the electrical margin is
The test equipment causes, for each DUT of a plurality of devices under test (DUTs), in one or both of the Tx and receive Rx directions, for each high speed I/O lane of the multi-lane high speed I/O link of the DUT, a process of evaluating width margin timing;
detecting eye width margin timing measurements for each DUT among the plurality of DUTs that are consistently below a predetermined threshold for the same lane across the plurality of DUTs based on the evaluating operation;
10. The method of claim 9 , comprising identifying potential DUT design problems based on detecting eye width and eye height margin measurements for each DUT in the plurality of DUTs.

The process of evaluating the electrical margin is
For each DUT in the plurality of DUTs, the eye width margin or eye width margin or eye width margin for each high speed I/O lane of the DUT's multi-lane high speed I/O link in one or both of the Tx and Rx directions is determined by the test equipment. a process of evaluating a height margin;
Detect eye width margin timing measurements for several of the DUTs that are consistently below predetermined thresholds for different lanes across the DUTs, respectively, based on the evaluating process. processing;
based on detecting eye width margin timing measurements of the some DUTs among the plurality of DUTs below the predetermined threshold for different lanes across the several DUTs, respectively; 10. The method of claim 9 , comprising: identifying potential assembly or design problems.

A computer program which , when executed , causes at least one processor to:
Establishing a multi-lane high-speed input/output (I/O) link for a device under test (DUT) and electrically powering said multi-lane high-speed I/O link in one or both of the transmit (Tx) and receive (Rx) directions. providing user-selectable options to a tester configured to evaluate electrical margins, including customization of the electrical margin evaluation of the multi-lane high-speed I/O link;
receiving instructions to select one or more of the user-selectable options for the test device;
A process for causing the test equipment to initiate an operation of evaluating the electrical margin of the multi-lane high speed I/O link based on indications of selection of one or more of the user-selectable options for the test equipment. A computer program that causes and .

The above user-selectable options are
selectable options for selecting and using one or more different high speed I/O protocols to perform margin testing based on the multi-lane high speed I/O link of the DUT;
selectable options for testing multiple ports of the DUT simultaneously using promiscuous protocols;
a selectable option for outputting, for the multi-lane high-speed I/O link, a per-execution margin variation through any number of executions of margin testing of the test equipment;
To implement a fixed Tx equalization (EQ) on the DUT to test how much of the margin variation is due to variations in the Tx equalization (EQ) training. selectable options for and
Optional for testing the effect of receiver equalization on margins of the multi-lane high-speed I/O link of the DUT using a tuned continuous-time linear equalizer (CTLE) at the receiver of the tester. options and
a selectable option for using a decision feedback equalizer (DFE) in the receiver of the tester to test the effect of the receiver equalization process on the margin of the multi-lane high speed I/O link of the DUT;
a selectable option for calculating an expected margin for the test fixture based on target channels;
a selectable option for automatically generating debug information when low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I/O link;
Selectable for switching the test equipment to use a variable inter-symbol interference (ISI) signal source to find out how much ISI causes lane impairments of the multi-lane high speed I/O link. options and
a selectable option for the tester to test each lane individually to determine the amount of margin loss due to crosstalk of the multi-lane high speed I/O link of the DUT;
with the DFE turned off at the receiver of the tester to evaluate the margin with and without the DFE and the amount of non-linear discontinuities in each channel associated with the multi-lane high speed I/O link; available options and
flagging a lower than expected margin even if the lower than expected margin is consistent across all lanes of the multi-lane high speed I/O link of one of the DUTs. a selectable option for characterization data of the test apparatus that enables
a selectable option for selecting among a plurality of speeds of the multi-lane high speed I/O link for which the electrical margin evaluation is performed;
the test equipment uses protocol-specific knowledge to infer when an error has occurred at the receiver of the DUT based on oppositely traveling traffic of the multi-lane high speed I/O link; a selectable option for enabling the tester to perform margin testing on the production line without software on the DUT;
a selectable option for automatically capturing time domain reflection measurements (TDR) of low margin channels detected as a result of the electrical margin evaluation of the multi-lane high speed I/O link;
for performing an automatic connection to an oscilloscope and automatically capturing a digitized waveform when low margin is detected as a result of the electrical margin evaluation of the multi-lane high speed I/O link; available options and
selectable options for setting one or more user selectable options on the DUT by configuring silicon of the DUT to implement the one or more user selectable options 14. The computer program of claim 13, comprising one or more.

The computer program , when executed, causes the at least one processor to cause the test apparatus to:
selecting one or more different high speed I/O protocols and using them to perform margin testing based on the multi-lane high speed I/O link of the DUT;
a process of testing multiple ports of the DUT simultaneously using promiscuous protocols;
a process of outputting margin fluctuations for each execution process while the margin test of the test equipment is executed an arbitrary number of times for the multi-lane high-speed I/O link;
implementing Tx fixed equalization (EQ) on the DUT to test how much the margin varies due to Tx equalization (EQ) training;
testing the effect of receiver equalization on margins of the multi-lane high-speed I/O link of the DUT using a tuned continuous-time linear equalizer (CTLE) at the receiver of the tester;
using a decision feedback equalizer (DFE) in the receiver of the test equipment to test the effect of receiver equalization on the margin of the multi-lane high speed I/O link of the DUT;
calculating an expected margin for the test equipment based on the target channel;
automatically generating debug information when low margin is detected as a result of evaluating the multi-lane high speed I/O link electrical margin;
switching to using a variable inter-symbol interference (ISI) source to find out how much inter-symbol interference (ISI) would cause a lane failure of the multi-lane high speed I/O link;
testing each lane individually to determine the amount of margin loss due to crosstalk of the multi-lane high speed I/O link of the DUT;
turning off the DFE in the receiver of the tester to evaluate the margin with and without the DFE and the amount of non-linear discontinuities for each channel associated with the multi-lane high speed I/O link;
A reference receiver and a typical channel are used to show expected margins, which are consistent with lower than expected margins across all lanes of the multi-lane high speed I/O link of the DUT and of the DUTs. the process of flagging margins lower than expected, even when
a process of selecting among a plurality of speeds of the multi-lane high speed I/O link and performing an electrical margin evaluation thereon;
Using protocol-specific knowledge, the test equipment infers when an error has occurred at the DUT's receiver based on traffic traveling in the opposite direction on the multi-lane high-speed I/O link; enabling the test equipment to perform margin testing on a production line without the above software;
automatically capturing time domain reflectometry (TDR) values of detected low margin channels as a result of evaluating the electrical margin of the multi-lane high speed I/O link;
performing an automatic connection to an oscilloscope to automatically capture a digitized waveform when low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I/O link;
setting one or more user-selectable options for the DUT by providing a software plug-in to configure the silicon of the DUT, and implementing the one or more user-selectable options. 14. The computer program of claim 13 which causes the

a motherboard;
at least one slot coupled to the motherboard for margin testing at least one add-in card;
The motherboard, after inserting the add-in card into the at least one slot, sets the electrical margins of the multi-lane fast input/output (I/O) link of the add-in card to transmit (Tx) and receive (Rx ) margin tester configured to evaluate in one or both directions.

the motherboard introduces controlled noise or jitter into at least the margin test transmitter;
To evaluate the electrical margin of the multi-lane high speed I/O link by being configured to change the expected eye margin at the motherboard receiver to specific targets for timing or voltage margins. 17. The margin tester of claim 16 , configured.

The multi-lane high speed, wherein the motherboard is configured to have the margin test receiver measure eye margins by moving independent error detectors and comparing for discrepancies using a data sampler. 17. The margin tester of claim 16 , configured to evaluate the electrical margin of an I/O link.

17. The margin tester of claim 16 , wherein the motherboard is configured to provide various margin test modes to enable characterization of problems with the add-in card based on margin test measurements.

The multi-lane high speed I/O link, wherein the motherboard is configured to introduce at least eye width and eye height opening reduction by introducing differential noise into the margin test transmitter. and the differential noise introduction is applied simultaneously to all lanes of the multi-lane high-speed I/O link, or the multi-lane high-speed I/O 17. The margin tester of claim 16 , wherein the margin tester is independently applied or selectable for each lane of the link.

The motherboard is configured to evaluate the electrical margins of the multi-lane high speed I/O link by being configured to introduce jitter into a margin test transmitter, the jitter introduction 17. The margin of claim 16 is selectable to be applied simultaneously to all lanes of the multi-lane high speed I/O link or to be applied independently to each lane of the multi-lane high speed I/O link. Testa.

The motherboard is configured to at least modulate the electrical length of the signal path to achieve jitter characteristics relative to an assumed ideal constant timing reference, thereby introducing jitter into the margin test transmitter. 22. The margin tester of claim 21, configured to install.

a process of calibrating the margin tester and allowing the user to receive a set of expected margins for a set of reference channels;
Without a special test mode, using the DUT's fully operational normally available link, the device under test (DUT) can be electrically and providing a calibrated margin tester configured to measure the margin of the eye and capture the full effects of loading and crosstalk.

4. The claim further comprising providing individually calibrated models for said margin tester to enable calculation of expected margins for one or more of personalized system channels, receiver models and transmitter models. 2 3 ways.

Further comprising a process of providing a software plug-in model in the form of a configuration software application for the margin tester, allowing the silicon vendor to perform margin testing with the margin tester under various conditions of the silicon of said DUT. 24. The method of claim 23, facilitating providing a software plug-in and DUT silicon parameters that enable configuration to perform.

A feature in the form of DUT silicon that allows the margin tester to indicate, using a vendor-defined message or another protocol mechanism, that the margin test is about to be performed by the margin tester. 24. The method of claim 23, further comprising processing to provide , enabling the silicon of the DUT to disable logic that reduces link width or link speed due to errors during margin testing.

further comprising providing a software application of the margin tester to test the channel component under test using the margin tester on both sides of the channel component under test in a test configuration; 24. The method of claim 23, which is tester-enableable.

a process of providing said margin tester hardware to a company that manufactures printed circuit boards (PCBs);
24. The method of claim 23, further comprising: providing data relating to the use of the margin tester to a silicon company that provides silicon used in manufacturing the PCB.

A computer program which , when executed , causes at least one processor to:
a process of receiving configuration settings for a device under test (DUT);
and setting up a DUT for margin testing by a margin tester under various conditions of the DUT 's silicon.

The computer program , when executed, causes the at least one processor to cause the margin tester to:
a software plug-in that enables configuration to perform the margin testing by the margin tester under various conditions of the silicon of the DUT and a process that accepts DUT silicon parameters. 29. The computer program of claim 29.