JPWO2020152523A1 - - Google Patents

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Publication number
JPWO2020152523A1
JPWO2020152523A1 JP2020567658A JP2020567658A JPWO2020152523A1 JP WO2020152523 A1 JPWO2020152523 A1 JP WO2020152523A1 JP 2020567658 A JP2020567658 A JP 2020567658A JP 2020567658 A JP2020567658 A JP 2020567658A JP WO2020152523 A1 JPWO2020152523 A1 JP WO2020152523A1
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2020567658A
Other languages
Japanese (ja)
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JPWO2020152523A5 (ja
JP7525405B2 (ja
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Publication of JPWO2020152523A1 publication Critical patent/JPWO2020152523A1/ja
Publication of JPWO2020152523A5 publication Critical patent/JPWO2020152523A5/ja
Application granted granted Critical
Publication of JP7525405B2 publication Critical patent/JP7525405B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2020567658A 2019-01-25 2019-11-20 半導体装置 Active JP7525405B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2019011605 2019-01-25
JP2019011605 2019-01-25
JP2019013347 2019-01-29
JP2019013347 2019-01-29
PCT/IB2019/059962 WO2020152523A1 (ja) 2019-01-25 2019-11-20 半導体装置、半導体装置の作製方法、及び半導体装置の動作方法

Publications (3)

Publication Number Publication Date
JPWO2020152523A1 true JPWO2020152523A1 (https=) 2020-07-30
JPWO2020152523A5 JPWO2020152523A5 (ja) 2022-11-30
JP7525405B2 JP7525405B2 (ja) 2024-07-30

Family

ID=71736850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020567658A Active JP7525405B2 (ja) 2019-01-25 2019-11-20 半導体装置

Country Status (3)

Country Link
US (1) US11849584B2 (https=)
JP (1) JP7525405B2 (https=)
WO (1) WO2020152523A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12250819B2 (en) 2019-07-05 2025-03-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US12156410B2 (en) 2019-08-09 2024-11-26 Semiconductor Energy Laboratory Co., Ltd. Memory device
KR102633039B1 (ko) * 2019-08-26 2024-02-05 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 제조 방법
WO2021144648A1 (ja) 2020-01-16 2021-07-22 株式会社半導体エネルギー研究所 記憶装置およびその作製方法
KR20230074757A (ko) 2020-10-02 2023-05-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR102889679B1 (ko) 2020-10-26 2025-11-24 삼성전자주식회사 반도체 메모리 장치
JP2023180895A (ja) * 2022-06-10 2023-12-21 キオクシア株式会社 半導体装置及び半導体記憶装置
CN119300490B (zh) * 2024-12-06 2025-03-21 电子科技大学 一种感存算一体的双面栅晶体管单管及其使用方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012069932A (ja) * 2010-08-27 2012-04-05 Semiconductor Energy Lab Co Ltd 記憶装置、半導体装置
JP2014017477A (ja) * 2012-06-15 2014-01-30 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016225614A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
JP2019012822A (ja) * 2017-06-16 2019-01-24 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7075829B2 (en) * 2001-08-30 2006-07-11 Micron Technology, Inc. Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
KR101698193B1 (ko) 2009-09-15 2017-01-19 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
US9177872B2 (en) 2011-09-16 2015-11-03 Micron Technology, Inc. Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
US9634097B2 (en) 2014-11-25 2017-04-25 Sandisk Technologies Llc 3D NAND with oxide semiconductor channel
US9887010B2 (en) 2016-01-21 2018-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, memory device, and driving method thereof
US10665604B2 (en) 2017-07-21 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor wafer, memory device, and electronic device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012069932A (ja) * 2010-08-27 2012-04-05 Semiconductor Energy Lab Co Ltd 記憶装置、半導体装置
JP2014017477A (ja) * 2012-06-15 2014-01-30 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016225614A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
JP2019012822A (ja) * 2017-06-16 2019-01-24 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Also Published As

Publication number Publication date
US20220068967A1 (en) 2022-03-03
WO2020152523A1 (ja) 2020-07-30
JP7525405B2 (ja) 2024-07-30
US11849584B2 (en) 2023-12-19

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