JPWO2020036819A5 - - Google Patents

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JPWO2020036819A5
JPWO2020036819A5 JP2021506675A JP2021506675A JPWO2020036819A5 JP WO2020036819 A5 JPWO2020036819 A5 JP WO2020036819A5 JP 2021506675 A JP2021506675 A JP 2021506675A JP 2021506675 A JP2021506675 A JP 2021506675A JP WO2020036819 A5 JPWO2020036819 A5 JP WO2020036819A5
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layer
barrier layer
graphene barrier
tungsten
forming
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JP2021506675A
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JP2021534572A (en
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Priority claimed from PCT/US2019/045872 external-priority patent/WO2020036819A1/en
Publication of JP2021534572A publication Critical patent/JP2021534572A/en
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Claims (20)

電子デバイスを形成する方法であって、前記方法が、
基板表面上にグラフェンバリア層を形成することと、
前記グラフェンバリア層の上に充填層を堆積させることと
を含み、
前記グラフェンバリア層が、前記充填層と前記基板表面との間の少なくとも１つの元素の拡散を防止する、方法。 A method of forming an electronic device, the method comprising:
forming a graphene barrier layer on the substrate surface;
depositing a fill layer over the graphene barrier layer;
The method, wherein the graphene barrier layer prevents diffusion of at least one element between the fill layer and the substrate surface. 前記基板表面が、誘電体材料を含む、請求項１に記載の方法。 2. The method of claim 1, wherein the substrate surface comprises a dielectric material. 前記誘電体材料が、金属酸化物を含む、請求項２に記載の方法。 3. The method of claim 2, wherein said dielectric material comprises a metal oxide. 前記誘電体材料が、本質的にＡｌ２０３からなる、請求項２に記載の方法。 3. The method of claim 2 , wherein the dielectric material consists essentially of Al2O3 . 前記グラフェンバリア層が、プラズマ強化原子層堆積を含む方法によって形成される、請求項１に記載の方法。 2. The method of claim 1, wherein the graphene barrier layer is formed by a method comprising plasma enhanced atomic layer deposition. 前記グラフェンバリア層が、約１５Åから約１００Åの範囲の厚さを有する、請求項１に記載の方法。 2. The method of claim 1, wherein the graphene barrier layer has a thickness ranging from about 15 Å to about 100 Å. 前記充填層が、タングステン、ルテニウム、銅、又はコバルトのうちの１つ又は複数を含む、請求項１に記載の方法。 2. The method of claim 1, wherein the fill layer comprises one or more of tungsten, ruthenium, copper, or cobalt. 前記少なくとも１つの元素が、ハロゲン、酸素又はホウ素のうちの１つ又は複数を含む、請求項１に記載の方法。 2. The method of claim 1, wherein the at least one element comprises one or more of halogen, oxygen or boron. 前記少なくとも１つの元素が、本質的にフッ素からなる、請求項８に記載の方法。 9. The method of claim 8 , wherein said at least one element consists essentially of fluorine. 前記充填層が、タングステンを含み、前記充填層が、 The fill layer comprises tungsten, and the fill layer comprises
前記グラフェンバリア層上にアモルファスシリコン層を形成することと、 forming an amorphous silicon layer on the graphene barrier layer;
前記アモルファスシリコン層を、タングステン前駆体に曝露し、原子置換によってタングステン層を形成することと exposing the amorphous silicon layer to a tungsten precursor to form a tungsten layer by atomic substitution;
を含む方法によって堆積される、請求項１に記載の方法。2. The method of claim 1, deposited by a method comprising: 前記タングステン前駆体がＷＦ The tungsten precursor is WF ６6 を含み、前記少なくとも１つの元素がフッ素を含む、請求項１０に記載の方法。and wherein said at least one element comprises fluorine. 前記充填層が、タングステンを含み、前記充填層が、前記グラフェンバリア層を、ＷＦ ６ を含むタングステン前駆体及び反応物に順次曝露することを含む方法によって堆積される、請求項１に記載の方法。 3. The method of claim 1, wherein the fill layer comprises tungsten, and wherein the fill layer is deposited by a method comprising sequentially exposing the graphene barrier layer to a tungsten precursor comprising WF6 and a reactant. . 電子デバイスを形成する方法であって、前記方法が、
Ａｌ２０３を含む基板表面上に、約１５Åから約１００Åの範囲の厚さを有するグラフェンバリア層を形成することと、
前記グラフェンバリア層上にアモルファスシリコン層を形成することと、
前記アモルファスシリコン層を、ＷＦ６を含むタングステン前駆体に曝露し、原子置換によってタングステン層を形成することと
を含み、前記グラフェンバリア層が、前記基板表面へのフッ素の拡散を防止する、方法。 A method of forming an electronic device, the method comprising:
forming a graphene barrier layer having a thickness ranging from about 15 Å to about 100 Å on a substrate surface comprising Al 2 O 3 ;
forming an amorphous silicon layer on the graphene barrier layer;
exposing the amorphous silicon layer to a tungsten precursor comprising WF6 to form a tungsten layer by atomic substitution, wherein the graphene barrier layer prevents diffusion of fluorine to the substrate surface. 第１の材料と第２の材料との間にグラフェンバリア層を含み、前記グラフェンバリア層が、前記第１の材料と前記第２の材料との間の少なくとも１つの元素の拡散を防止する、電子デバイス。 comprising a graphene barrier layer between the first material and the second material, the graphene barrier layer preventing diffusion of at least one element between the first material and the second material; electronic device. 前記グラフェンバリア層は、約１５Åから約１００Åの範囲の厚さを有する、請求項１４に記載のデバイス。 15. The device of Claim 14 , wherein the graphene barrier layer has a thickness ranging from about 15A to about 100A. 前記少なくとも１つの元素が、ハロゲン、酸素又はホウ素のうちの１つ又は複数を含む、請求項１４に記載のデバイス。 15. The device of claim 14 , wherein said at least one element comprises one or more of halogen, oxygen or boron. 前記少なくとも１つの元素が、本質的にフッ素からなる、請求項１６に記載のデバイス。 17. The device of claim 16 , wherein said at least one element consists essentially of fluorine. 前記第１の材料がタングステンを含み、前記第２の材料がＡｌ the first material comprises tungsten and the second material comprises Al ２2 ０0 ３3 を含む、請求項１４に記載のデバイス。15. The device of claim 14, comprising: 前記少なくとも１つの元素が、フッ素を含む、請求項１８に記載のデバイス。 19. The device of Claim 18, wherein said at least one element comprises fluorine. 前記デバイスが、前記第１の材料及び前記第２の材料の複数の交互層を含む３ＤのＮＡＮＤデバイスである、請求項１４に記載のデバイス。 15. The device of claim 14 , wherein said device is a 3D NAND device comprising multiple alternating layers of said first material and said second material.
JP2021506675A 2018-08-11 2019-08-09 Graphene diffusion barrier Pending JP2021534572A (en)

Applications Claiming Priority (3)

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US201862717824P 2018-08-11 2018-08-11
US62/717,824 2018-08-11
PCT/US2019/045872 WO2020036819A1 (en) 2018-08-11 2019-08-09 Graphene diffusion barrier

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JP2021534572A JP2021534572A (en) 2021-12-09
JPWO2020036819A5 true JPWO2020036819A5 (en) 2022-08-19

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JP (1) JP2021534572A (en)
KR (2) KR102554839B1 (en)
CN (1) CN112514031A (en)
SG (1) SG11202100359SA (en)
TW (2) TWI807639B (en)
WO (1) WO2020036819A1 (en)

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