KR19990029260A - Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using same - Google Patents
Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using same Download PDFInfo
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- KR19990029260A KR19990029260A KR1019980029531A KR19980029531A KR19990029260A KR 19990029260 A KR19990029260 A KR 19990029260A KR 1019980029531 A KR1019980029531 A KR 1019980029531A KR 19980029531 A KR19980029531 A KR 19980029531A KR 19990029260 A KR19990029260 A KR 19990029260A
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- metal
- deposition chamber
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- nitride film
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 219
- 239000002184 metal Substances 0.000 title claims abstract description 219
- 238000000034 method Methods 0.000 title claims abstract description 95
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 82
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000005229 chemical vapour deposition Methods 0.000 title claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 168
- 230000008021 deposition Effects 0.000 claims abstract description 160
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 103
- 239000007789 gas Substances 0.000 claims abstract description 85
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 63
- 238000010926 purge Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000002243 precursor Substances 0.000 claims abstract description 13
- 230000000903 blocking effect Effects 0.000 claims abstract 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 65
- 239000010410 layer Substances 0.000 claims description 47
- 230000004888 barrier function Effects 0.000 claims description 26
- 239000010936 titanium Substances 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 11
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910004529 TaF 5 Inorganic materials 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 239000012159 carrier gas Substances 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 4
- 241000209094 Oryza Species 0.000 claims 2
- 235000007164 Oryza sativa Nutrition 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- 235000009566 rice Nutrition 0.000 claims 2
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 description 122
- 239000000460 chlorine Substances 0.000 description 11
- 238000007796 conventional method Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000000376 reactant Substances 0.000 description 4
- 238000005001 rutherford backscattering spectroscopy Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- QCEOZLISXJGWSW-UHFFFAOYSA-K 1,2,3,4,5-pentamethylcyclopentane;trichlorotitanium Chemical compound [Cl-].[Cl-].[Cl-].CC1=C(C)C(C)([Ti+3])C(C)=C1C QCEOZLISXJGWSW-UHFFFAOYSA-K 0.000 description 1
- ZBFBXTFQCKIUHU-UHFFFAOYSA-L 1,2,3,5,5-pentamethylcyclopenta-1,3-diene;titanium(4+);dichloride Chemical compound [Cl-].[Cl-].[Ti+4].CC1=[C-]C(C)(C)C(C)=C1C.CC1=[C-]C(C)(C)C(C)=C1C ZBFBXTFQCKIUHU-UHFFFAOYSA-L 0.000 description 1
- MDTDQDVMQBTXST-UHFFFAOYSA-K 2h-inden-2-ide;titanium(4+);trichloride Chemical compound Cl[Ti+](Cl)Cl.C1=CC=C2[CH-]C=CC2=C1 MDTDQDVMQBTXST-UHFFFAOYSA-K 0.000 description 1
- MHDUGMOWFSOPJS-UHFFFAOYSA-N 4-(piperazin-4-ium-1-carbonyl)benzoate Chemical compound C1=CC(C(=O)[O-])=CC=C1C(=O)N1CC[NH2+]CC1 MHDUGMOWFSOPJS-UHFFFAOYSA-N 0.000 description 1
- KBXCFLXEWFCLED-UHFFFAOYSA-N CC1=C(C(=C(C1(C)[Ti](C)(C)C)C)C)C Chemical compound CC1=C(C(=C(C1(C)[Ti](C)(C)C)C)C)C KBXCFLXEWFCLED-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- NCSYGTWPOQMGOZ-UHFFFAOYSA-J N[Ti](N)(Cl)(Cl)(Cl)Cl Chemical compound N[Ti](N)(Cl)(Cl)(Cl)Cl NCSYGTWPOQMGOZ-UHFFFAOYSA-J 0.000 description 1
- -1 TiN Chemical class 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- JAGHDVYKBYUAFD-UHFFFAOYSA-L cyclopenta-1,3-diene;titanium(4+);dichloride Chemical compound [Cl-].[Cl-].[Ti+4].C1C=CC=[C-]1.C1C=CC=[C-]1 JAGHDVYKBYUAFD-UHFFFAOYSA-L 0.000 description 1
- QOXHZZQZTIGPEV-UHFFFAOYSA-K cyclopenta-1,3-diene;titanium(4+);trichloride Chemical compound Cl[Ti+](Cl)Cl.C=1C=C[CH-]C=1 QOXHZZQZTIGPEV-UHFFFAOYSA-K 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- ZNRKKSGNBIJSRT-UHFFFAOYSA-L dibromotantalum Chemical compound Br[Ta]Br ZNRKKSGNBIJSRT-UHFFFAOYSA-L 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- HDZGCSFEDULWCS-UHFFFAOYSA-N monomethylhydrazine Chemical compound CNN HDZGCSFEDULWCS-UHFFFAOYSA-N 0.000 description 1
- YRGLXIVYESZPLQ-UHFFFAOYSA-I tantalum pentafluoride Chemical compound F[Ta](F)(F)(F)F YRGLXIVYESZPLQ-UHFFFAOYSA-I 0.000 description 1
- MISXNQITXACHNJ-UHFFFAOYSA-I tantalum(5+);pentaiodide Chemical compound [I-].[I-].[I-].[I-].[I-].[Ta+5] MISXNQITXACHNJ-UHFFFAOYSA-I 0.000 description 1
- OEIMLTQPLAGXMX-UHFFFAOYSA-I tantalum(v) chloride Chemical compound Cl[Ta](Cl)(Cl)(Cl)Cl OEIMLTQPLAGXMX-UHFFFAOYSA-I 0.000 description 1
- 239000013076 target substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- UBZYKBZMAMTNKW-UHFFFAOYSA-J titanium tetrabromide Chemical compound Br[Ti](Br)(Br)Br UBZYKBZMAMTNKW-UHFFFAOYSA-J 0.000 description 1
- XROWMBWRMNHXMF-UHFFFAOYSA-J titanium tetrafluoride Chemical compound [F-].[F-].[F-].[F-].[Ti+4] XROWMBWRMNHXMF-UHFFFAOYSA-J 0.000 description 1
- NLLZTRMHNHVXJJ-UHFFFAOYSA-J titanium tetraiodide Chemical compound I[Ti](I)(I)I NLLZTRMHNHVXJJ-UHFFFAOYSA-J 0.000 description 1
- YONPGGFAJWQGJC-UHFFFAOYSA-K titanium(iii) chloride Chemical compound Cl[Ti](Cl)Cl YONPGGFAJWQGJC-UHFFFAOYSA-K 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Chemical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
화학기상증착법에 의한 금속질화막 형성방법 및 이를 이용한 반도체 장치의 금속컨택 형성방법을 개시한다. 본 발명의 금속질화막 형성방법은, 금속소스와 질소소스를 전구체로 사용하는 화학기상증착법에 의한 금속질화막 형성방법으로서, 반도체 기판을 증착실 내로 인입하는 단계와, 금속소스를 증착실 내로 유입하는 단계와, 금속소스의 유입을 차단하고 퍼지가스를 증착실 내로 유입하여 증착실 내에 잔류하는 금속소스를 제거하는 단계와, 퍼지가스의 유입을 차단하고 질소소스를 증착실 내로 유입하여 반도체 기판상에 흡착된 금속소스와 반응시키는 단계와, 질소소스의 유입을 차단하고 퍼지가스를 증착실내로 유입하여 증착실내에 잔류하는 질소소스를 제거하는 단계를 구비하여 반도체 기판상에 금속질화막을 형성하는 것을 특징으로 한다.A method of forming a metal nitride film by chemical vapor deposition and a method of forming a metal contact in a semiconductor device using the same are disclosed. The metal nitride film forming method of the present invention is a method of forming a metal nitride film by a chemical vapor deposition method using a metal source and a nitrogen source as precursors, including introducing a semiconductor substrate into a deposition chamber, and introducing a metal source into the deposition chamber. And blocking the inflow of the metal source and introducing the purge gas into the deposition chamber to remove the metal source remaining in the deposition chamber, and blocking the introduction of the purge gas and introducing the nitrogen source into the deposition chamber and adsorbing on the semiconductor substrate. Forming a metal nitride film on the semiconductor substrate by reacting with the prepared metal source and blocking the inflow of the nitrogen source and introducing the purge gas into the deposition chamber to remove the nitrogen source remaining in the deposition chamber. do.
본 발명에 따르면, 500℃ 이하의 저온에서 단차도포성이 우수하면서도 낮은 비저항과 낮은 Cl 함량을 갖는 금속질화막을 얻을 수 있고, 증착속도가 대략 20Å/cycle로서 대량생산에도 적합하다.According to the present invention, it is possible to obtain a metal nitride film having excellent step coverage at a low temperature of 500 ° C. or less and having a low specific resistance and a low Cl content.
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로서, 상세하게는 금속소스와 질소소스를 전구체(precursor)로 사용하는 화학기상증착법(Chemical Vapor Deposion, 이하 CVD라 함)에 의한 금속질화막 형성방법 및 이를 이용한 반도체 장치의 금속컨택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method of forming a metal nitride film using a chemical vapor deposition method (hereinafter referred to as CVD) using a metal source and a nitrogen source as a precursor, and using the same. A metal contact forming method of a semiconductor device.
반도체 소자의 컨택 계면의 안정화를 위해서는 다른 물질간의 상호확산이나 화학반응을 억제하는 역할을 하는 장벽금속(barrier metal)층이 필수적이다. 이러한 반도체 소자의 장벽금속층으로는 일반적으로 TiN, TaN, WN과 같은 금속질화물이 널리 이용되는데, 이 중에서도 TiN이 대표적인 물질이다.In order to stabilize the contact interface of a semiconductor device, a barrier metal layer, which serves to suppress interdiffusion or chemical reaction between different materials, is essential. In general, metal nitrides such as TiN, TaN, and WN are widely used as the barrier metal layer of the semiconductor device. Among them, TiN is a representative material.
그러나 TiN과 같은 금속질화막을 스퍼터링 방법으로 제조할 경우 단차도포성(step coverage)이 낮아 점차 고집적화하는 반도체 소자에 적용하기에는 문제가 있다. 일예로, 금속배선간의 연결을 위한 비아컨택(via contact)을 형성한 경우의 단면을 도 9a 및 도 9b에 도시하였다. 도 9a 및 도 9b는 각각 단순한 비아컨택 및 앵커(anchor) 비아컨택을 도시한 것으로 그 형성과정은 다음과 같다. 반도체 기판(20) 상에 알루미늄(Al)으로 이루어진 제1금속층(30)을 형성하고, 그 위에 캡핑막으로서 TiN막(40)을 스퍼터링 방법으로 형성한 후, 층간절연막(50,51)을 적층한다. 이어서 제1금속층(30) 위의 층간절연막을 식각하여 컨택홀을 형성하고(도9b의 경우는 습식식각으로 앵커(A)를 형성하는 과정이 추가된다), 접착층인 Ti 및 장벽금속층인 TiN막(60,61)을 증착한 다음, CVD법으로 컨택홀을 채우는 텅스텐(W) 플러그(70,71)를 형성한다. 이후에, 화학기계적 연마(Chemical Mechanical Polishing)나 에치백으로 윗 부분의 텅스텐을 제거하고 그 위에 제2금속층을 적층함으로써 금속배선간 연결이 완성되는데, 이 과정은 도시를 생략하였다.However, when a metal nitride film such as TiN is manufactured by a sputtering method, there is a problem in that it is applied to a semiconductor device which gradually increases due to low step coverage. For example, cross-sections in the case of forming via contacts for connection between metal wires are illustrated in FIGS. 9A and 9B. 9A and 9B illustrate a simple via contact and an anchor via contact, respectively. The formation process is as follows. After forming the first metal layer 30 made of aluminum (Al) on the semiconductor substrate 20 and forming the TiN film 40 as a capping film thereon by a sputtering method, the interlayer insulating films 50 and 51 are laminated. do. Subsequently, the interlayer insulating film on the first metal layer 30 is etched to form a contact hole (in the case of FIG. 9B, a process of forming the anchor A by wet etching is added), and the TiN film, which is an adhesive layer and a barrier metal layer After depositing (60,61), tungsten (W) plugs 70,71 are formed to fill the contact holes by CVD. Subsequently, the connection between the metal wirings is completed by removing the upper tungsten with chemical mechanical polishing or etch back and laminating a second metal layer thereon, and the process is omitted.
여기서, 종래의 방법은 장벽금속층인 TiN막(60,61)을 단차도포성이 좋지 않은 스퍼터링 방법으로 증착하는데, 비아의 종횡비(aspect ratio)가 커짐에 따라 컨택홀의 저면이나 구석, 앵커를 형성하는 부위(A)에서는 그 두께가 적어진다. 따라서, 그 두께가 적은 부위는 후속공정인 텅스텐 증착시 텅스텐 소스가스인 WF6에서 잔류한 불소와 결합하여 절연막인 TiFx또는 AlFx(X)를 형성하여 컨택불량을 초래한다.Here, in the conventional method, the TiN films 60 and 61, which are barrier metal layers, are deposited by a sputtering method having a poor level coating property. As the aspect ratio of the via increases, the bottom surface, corners, and anchors of the contact holes are formed. In the part A, the thickness becomes small. Therefore, the portion having a small thickness is combined with fluorine remaining in the tungsten source gas WF 6 during the subsequent tungsten deposition to form an insulating film TiF x or AlF x (X), resulting in contact failure.
이러한 컨택불량을 제거하는 방법으로 증착시간을 늘려 TiN막(60,61)의 두께를 증가시키는 것을 채택하는 경우에는 컨택홀 윗쪽만 TiN막의 두께가 증가하여 컨택홀 윗쪽이 좁아지거나 막혀서 이후 텅스텐 증착시 보이드(void)가 발생할 소지가 많다. 따라서, TiN을 종횡비가 큰 컨택에 적용하기 위해서는 단차도포 특성이 개선된 공정을 필요로 한다. 이에 따라 CVD법에 의한 금속질화막(이하 CVD-금속질화막이라 함)의 제조공정이 차세대 공정으로 연구되어 왔다.In the case of adopting the method of removing the contact defect by increasing the deposition time to increase the thickness of the TiN film (60, 61), the thickness of the TiN film is increased only on the upper contact hole, so that the upper contact hole becomes narrow or clogged. Voids are likely to occur. Therefore, in order to apply TiN to a contact having a high aspect ratio, a process having improved step application characteristics is required. Accordingly, the manufacturing process of the metal nitride film (hereinafter referred to as CVD-metal nitride film) by the CVD method has been studied as the next generation process.
일반적으로 CVD-금속질화막 공정에서는 염소(Cl)를 함유한 금속소스, 예를 들면 TiCl4(titanium chloride)와 같은전구체를 사용한다. TiCl4를 전구체로 이용하는 CVD-금속질화막은 95% 이상의 높은 단차도포성을 갖고 증착속도가 빠르다는 장점이 있지만, Cl이 금속질화막 내에서 미처 빠져나가지 못하고 불순물로 남게된다는 문제가 있다. 이와 같이 금속질화막에 불순물로 남게되는 Cl은 Al과 같은 금속배선의 부식문제를 야기하며 비저항을 높게 한다. 따라서, 금속질화막내에 남게되는 Cl함량을 줄이고 비저항을 낮추는 것이 요구되는데, 이를 위해서는 높은 온도에서 증착이 행해져야 한다. 즉, TiCl4와 같은 금속소스를 이용한 CVD-금속질화막 공정에서 200μΩ-㎝이하의 비저항을 얻기 위해서는 최소한 675℃의 증착온도를 요구한다. 그러나 600℃ 이상의 높은 증착온도는 하지막(underlayer)이 감당할 수 있는 열적 부담(thermal budget) 한계와 열응력 한계를 넘는다는 문제가 있고, 특히 Si 컨택이나 Al이 하지막으로 있는 비아컨택에 금속질화막을 증착할 때는 480℃ 이하의 증착온도가 요구되기 때문에 고온의 CVD-금속질화막 공정을 사용할 수가 없다.In general, a CVD-metal nitride film process uses a metal source containing chlorine (Cl), for example a precursor such as TiCl 4 (titanium chloride). The CVD-metal nitride film using TiCl 4 as a precursor has an advantage of having a high step coverage of more than 95% and a high deposition rate, but has a problem that Cl does not escape in the metal nitride film and remains as an impurity. As such, Cl, which remains as an impurity in the metal nitride film, causes corrosion problems of metal wires such as Al and increases specific resistance. Therefore, it is required to reduce the Cl content remaining in the metal nitride film and to lower the specific resistance, for which the deposition should be performed at a high temperature. That is, in order to obtain a resistivity of 200 µΩ-cm or less in a CVD-metal nitride film process using a metal source such as TiCl 4 , a deposition temperature of at least 675 ° C. is required. However, the high deposition temperature of more than 600 ℃ has a problem of exceeding the thermal budget limit and the thermal stress limit that the underlayer can afford, especially the metal nitride film in the via contact with Si contact or Al as the underlying film. The high temperature CVD-metal nitride film process cannot be used because the deposition temperature of 480 ° C. or less is required for the deposition.
저온증착 CVD-금속질화막 공정으로서 TiCl4와 같은 금속소스에 MH(methylhydrazine, (CH3)HNNH2)를 첨가하는 방법이 있으나, 이 경우 단차도포 특성이 70% 이하로 떨어진다는 단점이 있다.As a low-temperature deposition CVD-metal nitride film process, there is a method of adding MH (methylhydrazine, (CH 3 ) HNNH 2 ) to a metal source such as TiCl 4 , but in this case, there is a disadvantage in that the step coating property drops to 70% or less.
저온증착이 가능한 다른 방법으로는, TDEAT(tetrakis diethylamino Ti, Ti(N(CH2CH3)2)4), TDMAT(tetrakis dimethylamino Ti, Ti(N(CH3)2)4) 등의 유기금속 전구체(metalorganic precursor)를 사용하는 MOCVD-금속질화막 형성방법이 있다. MOCVD-금속질화막은 Cl로 인한 문제점이 발생하지 않고 저온증착이 가능하다는 장점이 있다. 그러나 MOCVD-금속질화막은 그 막내에 불순물로 탄소(C)가 다량으로 존재하여 높은 비저항을 보이며 단차도포성이 70% 정도로 좋지 않다는 단점이 있다.Other methods capable of low temperature deposition include organic metals such as tetrakis diethylamino Ti, Ti (N (CH 2 CH 3 ) 2 ) 4 ), TDMAT (tetrakis dimethylamino Ti, Ti (N (CH 3 ) 2 ) 4 ) There is a method of forming a MOCVD-metal nitride film using a metalorganic precursor. The MOCVD-metal nitride film has an advantage that low temperature deposition is possible without a problem caused by Cl. However, the MOCVD-metal nitride film has a disadvantage in that a large amount of carbon (C) is present as an impurity in the film, and thus shows a high specific resistance, and the step coverage is not as good as 70%.
한편, Cl로 인한 문제점을 극복하기 위해 증착이 아닌 다른 방법으로는 원자층 성장법(atomic layer epitaxy, 이하 ALE라 함)에 의한 금속질화막의 형성방법이 시도되고 있다. 그러나 ALE는 화학적 흡착만을 이용하여 원자층 단위로 성장시키기 때문에 대량생산이 요구되는 반도체소자의 제조공정에 적용하기에는 증착속도(0.25Å/cycle 이하)가 너무 느리다는 단점이 있다.On the other hand, in order to overcome the problems caused by Cl, as a method other than deposition, a method of forming a metal nitride film by atomic layer growth method (hereinafter referred to as ALE) has been attempted. However, since ALE grows by atomic adsorption using only chemical adsorption, the deposition rate (0.25 Pa / cycle or less) is too slow to be applied to the manufacturing process of semiconductor devices requiring mass production.
본 발명은 상기와 같은 단점을 감안하여 안출된 것으로서, 저온에서 증착속도가 빠르면서도 우수한 단차도포 특성과 낮은 불순물 농도 및 낮은 비저항 값을 만족하는 금속질화막을 형성하는 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above disadvantages, and an object thereof is to provide a method of forming a metal nitride film which satisfies a high deposition rate and low impurity concentration and low resistivity at low temperature. .
본 발명의 다른 목적은 상기의 금속질화막 형성방법을 반도체 장치의 금속컨택에 적용하여 저온에서 증착속도가 빠르면서도 우수한 단차도포 특성과 낮은 불순물 농도 및 낮은 비저항 값을 만족하는 장벽금속층을 갖는 금속컨택 형성방법을 제공하는 데 있다.Another object of the present invention is to apply the method of forming the metal nitride film to the metal contact of the semiconductor device to form a metal contact having a barrier metal layer that satisfies a high deposition rate, low impurity concentration and low resistivity value at a low deposition rate at low temperatures To provide a way.
도 1은 본 발명에 따라 반도체 기판상에 금속질화막을 증착하기 위한 화학기상증착 장치의 증착실을 나타내는 개략도이다.1 is a schematic view showing a deposition chamber of a chemical vapor deposition apparatus for depositing a metal nitride film on a semiconductor substrate according to the present invention.
도 2는 본 발명에 따라 반도체 기판상에 금속질화막을 증착하기 위한 가스유입 타이밍을 나타내는 타이밍도이다.2 is a timing diagram showing a gas inflow timing for depositing a metal nitride film on a semiconductor substrate according to the present invention.
도 3은 본 발명에 따라 증착된 금속질화막의 RBS(Rutherford Back Scattering) 결과를 나타내는 그래프이다.3 is a graph showing the RBS (Rutherford Back Scattering) results of the metal nitride film deposited according to the present invention.
도 4는 본 발명에 따라 금속질화막을 증착할 때 NH3의 유량에 대한 금속질화막의 비저항 및 증착속도의 관계를 나타내는 그래프이다.4 is a graph showing the relationship between the specific resistance of the metal nitride film and the deposition rate with respect to the flow rate of NH 3 when the metal nitride film is deposited according to the present invention.
도 5는 본 발명에 따라 금속질화막을 증착할 때 증착실 압력에 대한 금속질화막의 비저항 및 증착속도의 관계를 나타내는 그래프이다.5 is a graph showing the relationship between the specific resistance of the metal nitride film and the deposition rate to the deposition chamber pressure when the metal nitride film is deposited according to the present invention.
도 6은 본 발명에 따라 금속질화막을 증착할 때 반복하는 사이클 수에 대한 금속질화막의 증착두께의 관계를 나타내는 그래프이다.6 is a graph showing the relationship between the deposition thickness of a metal nitride film and the number of cycles repeated when the metal nitride film is deposited according to the present invention.
도 7은 본 발명에 따라 금속질화막을 증착할 때 반복하는 사이클 수에 대한 금속질화막의 증착속도의 관계를 나타내는 그래프이다.7 is a graph showing the relationship between the deposition rate of the metal nitride film and the number of cycles to be repeated when the metal nitride film is deposited according to the present invention.
도 8은 본 발명에 따라 금속질화막을 증착할 때 증착온도에 대한 금속질화막의 비저항의 관계를 나타내는 그래프이다.8 is a graph showing the relationship between the specific resistance of the metal nitride film and the deposition temperature when the metal nitride film is deposited according to the present invention.
도 9a 및 도 9b는 종래의 방법에 의하여 형성된 비아컨택을 도시한 단면도이다.9A and 9B are cross-sectional views illustrating via contacts formed by a conventional method.
도 10a 내지 도 10f는 본 발명의 금속질화막 형성방법을 이용한 비아컨택 형성과정의 일예를 도시한 단면도이다.10A to 10F are cross-sectional views illustrating an example of a via contact forming process using the metal nitride film forming method of the present invention.
도 11a 내지 도 11f는 본 발명의 금속질화막 형성방법을 이용한 비아컨택 형성과정의 다른 예를 도시한 단면도이다.11A to 11F are cross-sectional views illustrating another example of a via contact forming process using the metal nitride film forming method of the present invention.
도 12는 본 발명 및 종래의 방법에 따라 장벽금속층을 형성한 경우의 비아폭에 대한 비아 저항의 관계를 도시한 그래프이다.FIG. 12 is a graph showing the relationship of the via resistance to the via width when the barrier metal layer is formed according to the present invention and the conventional method.
도 13은 본 발명 및 종래의 방법에 따라 장벽금속층을 형성한 경우의 비아 저항의 분포를 도시한 그래프이다.FIG. 13 is a graph showing the distribution of via resistance when a barrier metal layer is formed according to the present invention and the conventional method.
상기의 목적을 달성하기 위한 본 발명의 금속질화막 형성방법은, 금속소스와 질소소스를 전구체로 사용하는 화학기상증착법에 의한 금속질화막 형성방법으로서 다음과 같이 이루어지는 것을 특징으로 한다. 먼저, 반도체 기판을 증착실 내로 인입하고, 금속소스를 증착실 내로 유입한다. 소정시간후 금속소스의 유입을 차단하고 퍼지가스를 증착실 내로 유입하여 증착실 내에 잔류하는 금속소스를 제거한다. 소정시간후 퍼지가스의 유입을 차단하고 질소소스를 증착실 내로 유입하여 반도체 기판상에 흡착된 금속소스와 반응시킨다. 다시 소정시간후 질소가스의 유입을 차단하고 퍼지가스를 증착실내로 유입하여 증착실내에 잔류하는 질소소스를 제거하여 반도체 기판상에 금속질화막을 형성한다.The metal nitride film forming method of the present invention for achieving the above object is a metal nitride film forming method by a chemical vapor deposition method using a metal source and a nitrogen source as a precursor, characterized in that made as follows. First, a semiconductor substrate is introduced into a deposition chamber, and a metal source is introduced into the deposition chamber. After a predetermined time, the inflow of the metal source is blocked and the purge gas is introduced into the deposition chamber to remove the metal source remaining in the deposition chamber. After a predetermined time, the inflow of the purge gas is blocked and a nitrogen source is introduced into the deposition chamber to react with the metal source adsorbed on the semiconductor substrate. After a predetermined time, the inflow of nitrogen gas is blocked and the purge gas is introduced into the deposition chamber to remove the nitrogen source remaining in the deposition chamber to form a metal nitride film on the semiconductor substrate.
본 발명의 금속질화막 형성방법은 원하는 두께의 금속질화막을 얻을 때까지 상기의 금속소스→퍼지가스→질소소스→퍼지가스의 순으로 유입하는 가스유입 사이클을 반복할 수 있다.In the metal nitride film forming method of the present invention, the gas inlet cycle which flows in the order of the metal source → purge gas → nitrogen source → purge gas can be repeated until a metal nitride film having a desired thickness is obtained.
여기서, 금속소스는 TiCl4(titanium chloride), TiCl3(titanium chloride), TiI4(titanium iodide), TiBr2(titanium bromide), TiF4(titanium fluoride), (C5H5)2TiCl2(bis(cyclopentadienyl)titanium dichloride), ((CH3)5C5)2TiCl2(bis(pentamethylcyclopentadienyl)titanium dichloride), C5H5TiCl3(cyclopentadienyltitanium trichloride), C9H10BCl3N6Ti(hydrotris (1-pyrazolylborato)trichloro titanium), C9H7TiCl3(indenyltitanium trichloride), (C5(CH3)5)TiCl3(pentamethylcyclopentadienyltitanium trichloride), TiCl4(NH3)2(tetrachlorodiaminotitanium), (CH3)5C5Ti(CH3)3(trimethylpentamethylcyclopenta dienyltitanium), TDEAT 또는 TDMAT이고, 질소소스는 NH3로 하여 금속질화막으로서 TiN막을 형성하도록 할 수 있고, 금속소스를 TaBr5(tantalum bromide), TaCl5(tantalum chloride), TaF5(tantalum fluoride), TaI5(tantalum iodide) 또는 (C5(CH3)5)TaCl4(pentamethylcyclopentadienyltantalum tetrachloride)로 하고, 질소소스를 NH3로 하여 TaN막을 형성하도록 할 수도 있다.Here, the metal source is TiCl 4 (titanium chloride), TiCl 3 (titanium chloride), TiI 4 (titanium iodide), TiBr 2 (titanium bromide), TiF 4 (titanium fluoride), (C 5 H 5 ) 2 TiCl 2 ( bis (cyclopentadienyl) titanium dichloride), ((CH 3 ) 5 C 5 ) 2 TiCl 2 (bis (pentamethylcyclopentadienyl) titanium dichloride), C 5 H 5 TiCl 3 (cyclopentadienyltitanium trichloride), C 9 H 10 BCl 3 N 6 Ti ( hydrotris (1-pyrazolylborato) trichloro titanium), C 9 H 7 TiCl 3 (indenyltitanium trichloride), (C 5 (CH 3 ) 5 ) TiCl 3 (pentamethylcyclopentadienyltitanium trichloride), TiCl 4 (NH 3 ) 2 (tetrachlorodiaminotitanium), (CH 3 ) 5 C 5 Ti (CH 3 ) 3 (trimethylpentamethylcyclopenta dienyltitanium), TDEAT or TDMAT, the nitrogen source is NH 3 to form a TiN film as a metal nitride film, the metal source is TaBr 5 (tantalum bromide), TaCl 5 (tantalum chloride), TaF 5 (tantalum fluoride), TaI 5 (tantalum iodide) or (C 5 (CH 3 ) 5 ) TaCl 4 (pentamethylcyclopentadienyltantalum tetrachlor ide), and a nitrogen source is NH 3 to form a TaN film.
또한, 퍼지가스는 Ar이나 N2등의 불활성 기체를 사용하는 것이 바람직하다.Further, the purge gas is preferably an inert gas such as Ar or N 2.
증착실 내로 유입하는 금속소스, 질소소스, 퍼지가스의 유량은 각각 1∼5sccm, 5∼200sccm, 10∼200sccm 정도로 하는 것이 바람직하고, 각 가스의 유입시간은 1∼10초 정도로 하는 것이 바람직하다.The flow rates of the metal source, the nitrogen source, and the purge gas flowing into the deposition chamber are preferably about 1 to 5 sccm, 5 to 200 sccm, and 10 to 200 sccm, respectively, and the introduction time of each gas is preferably about 1 to 10 seconds.
또한, 증착실 내의 압력을 일정하게 유지하기 위하여 Ar, He 또는 N2등의 분위기 가스를 증착실내로 계속하여 유입할 수도 있다.In addition, in order to maintain a constant pressure in the deposition chamber, an atmosphere gas such as Ar, He, or N 2 may be continuously introduced into the deposition chamber.
한편, 금속소스로서 TDEAT나 TDMAT를 사용하여 TiN막을 형성하는 경우에는 증착실 압력을 0.1∼10torr, 증착온도를 250∼400℃로 하는 것이 바람직하다. 그밖의 금속소스를 사용하는 경우에는 증착실 압력을 1∼20torr, 증착온도를 400∼500℃로 한다.On the other hand, when a TiN film is formed using TDEAT or TDMAT as the metal source, it is preferable to set the deposition chamber pressure to 0.1 to 10 torr and the deposition temperature to 250 to 400 ° C. In the case of using other metal sources, the deposition chamber pressure is 1-20 torr and the deposition temperature is 400-500 占 폚.
상기의 다른 목적을 달성하기 위한 본 발명의 금속컨택 형성방법은, 반도체 기판 상에 제1금속층, 층간절연막, 컨택홀, 장벽금속층, 금속 플러그, 제2금속층을 차례로 형성하는 금속컨택 형성방법으로서, 특히 장벽금속층을 형성하는 과정이 다음과 같은 것을 특징으로 한다. 즉, 층간절연막에 제1금속층을 노출하는 컨택홀이 형성된 반도체 기판에 대하여, 금속소스를 유입하여 금속소스를 흡착시킨다. 소정시간후 금속소스의 유입을 차단하고 퍼지가스를 유입하여 증착실 내에 잔류하는 금속소스를 제거한다. 소정시간후 퍼지가스의 유입을 차단하고 질소소스를 증착실 내로 유입하여 반도체 기판 상에 흡착된 금속소스와 반응시켜, 노출된 제1금속층 및 컨택홀 상에 장벽금속층인 금속질화막을 형성한다. 다시 소정시간후 질소소스의 유입을 차단하고 퍼지가스를 증착실내로 유입하여 증착실 내에 잔류하는 질소소스를 제거한다.The metal contact forming method of the present invention for achieving the above another object is a metal contact forming method of sequentially forming a first metal layer, an interlayer insulating film, a contact hole, a barrier metal layer, a metal plug, a second metal layer on a semiconductor substrate, In particular, the process of forming the barrier metal layer is characterized as follows. That is, the metal source is introduced into the semiconductor substrate having the contact hole exposing the first metal layer in the interlayer insulating film to adsorb the metal source. After a predetermined time, the inflow of the metal source is blocked and the purge gas is introduced to remove the metal source remaining in the deposition chamber. After a predetermined time, the inflow of the purge gas is blocked and the nitrogen source is introduced into the deposition chamber to react with the metal source adsorbed on the semiconductor substrate, thereby forming a metal nitride film as a barrier metal layer on the exposed first metal layer and the contact hole. After a predetermined time, the inflow of the nitrogen source is blocked and the purge gas is introduced into the deposition chamber to remove the nitrogen source remaining in the deposition chamber.
이상과 같은 장벽금속층 형성과정을 원하는 두께의 장벽금속층을 얻을 때까지 반복하여 수행할 수 있다.The barrier metal layer formation process as described above may be repeatedly performed until a barrier metal layer having a desired thickness is obtained.
여기서, 금속소스는 TiCl4, TiCl3, TiI4, TiB2, TiF4, (C5H5)2TiCl2, ((CH3)5C5)2TiCl2, C5H5TiCl3, C9H10BCl3N6Ti, C9H7TiCl3, (C5(CH3)5)TiCl3, TiCl4(NH3)2, (CH3)5C5Ti(CH3)3, TDEAT 또는 TDMAT이고, 질소소스는 NH3로 하여 장벽금속층으로서 TiN막을 형성하도록 하거나, 금속소스는 TaBr5, TaCl5, TaF5, TaI5또는 (C5(CH3)5)TaCl4이고, 질소소스는 NH3로 하여 장벽금속층으로서 TaN막을 형성하도록 한다.Here, the metal source is TiCl 4 , TiCl 3 , TiI 4 , TiB 2 , TiF 4 , (C 5 H 5 ) 2 TiCl 2 , ((CH 3 ) 5 C 5 ) 2 TiCl 2 , C 5 H 5 TiCl 3 , C 9 H 10 BCl 3 N 6 Ti, C 9 H 7 TiCl 3 , (C 5 (CH 3 ) 5 ) TiCl 3 , TiCl 4 (NH 3 ) 2 , (CH 3 ) 5 C 5 Ti (CH 3 ) 3 , the TDEAT or TDMAT, nitrogen source, or to form a TiN film as a barrier metal layer to NH 3, the metal source is a TaBr 5, TaCl 5, TaF 5 , TaI 5 , or (C 5 (CH 3) 5 ) TaCl 4, The nitrogen source is NH 3 to form a TaN film as a barrier metal layer.
또한, 퍼지가스는 Ar 또는 N2등의 불활성 기체를 사용하는 것이 바람직하다.Further, the purge gas is preferably an inert gas such as Ar or N 2.
증착실 내로 유입하는 금속소스, 질소소스 및 퍼지가스의 유량 및 유입시간은 전술한 본 발명의 금속질화막 형성방법에서와 동일한 범위로 한다.The flow rate and the inflow time of the metal source, the nitrogen source and the purge gas flowing into the deposition chamber are in the same range as in the method of forming the metal nitride film of the present invention described above.
또한, 장벽금속층 형성시 증착실 내의 압력을 일정하게 유지하기 위하여, Ar, He 또는 N2등의 분위기 가스를 사용하여 증착실 내의 압력을, 금속소스로서 TDEAT나 TDMAT를 사용하는 경우는 0.1∼10torr, 그밖의 금속소스를 사용하는 경우는 1-20torr 정도로 유지한다.In addition, in order to maintain a constant pressure in the deposition chamber when forming the barrier metal layer, the pressure in the deposition chamber using an atmosphere gas such as Ar, He, or N 2 is used, and when the TDEAT or TDMAT is used as the metal source, 0.1 to 10 torr In case of using other metal source, keep it at 1-20torr.
장벽금속층 형성시 증착온도는, 금속소스로서 TDEAT나 TDMAT를 사용하는 경우는 250∼400℃, 그밖의 금속소스를 사용하는 경우는 400∼480℃ 정도로 하는 것이 바람직하다.When forming the barrier metal layer, the deposition temperature is preferably about 250 to 400 ° C. when TDEAT or TDMAT is used as the metal source, and about 400 to 480 ° C. when other metal sources are used.
이와 같이 구성된 본 발명에 따르면, 단차도포 특성이 우수하면서도 200μΩ-㎝이하의 낮은 비저항과 낮은 Cl 함량을 갖는 금속질화막을 얻을 수 있다. 그리고 500℃ 이하의 저온에서 CVD-금속질화막을 형성하는 것이 가능하면서도 증착속도가 대략 20Å/cycle로서 성장속도가 0.25Å/cycle인 ALE에 의한 금속질화막 형성방법에 비하여 증착속도가 빠르다.According to the present invention configured as described above, it is possible to obtain a metal nitride film having excellent step-coating characteristics and low resistivity and low Cl content of less than 200 mu Ω-cm. It is possible to form the CVD-metal nitride film at a low temperature of 500 ° C. or lower, but the deposition rate is about 20 μs / cycle, and the deposition rate is faster than the method of forming the metal nitride film by ALE having a growth rate of 0.25 μs / cycle.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 형성방법에 따라 금속질화막을 증착하기 위한 CVD 장치의 증착실을 나타내는 개략도이다.1 is a schematic view showing a deposition chamber of a CVD apparatus for depositing a metal nitride film according to the forming method of the present invention.
도시된 바와 같이, 증착실(100)에는 반응기체들을 증착실(100) 내로 유입시키기 위한 복수의 가스관(114a, 114b)이 설치되는데, 가스관들의 수는 증착실(100) 내로 유입되는 금속소스와 질소소스의 수, 즉 반응기체들의 수에 의존하며, 본 발명의 실시예에서는 2개의 가스관들(114a, 114b)이 설치된다.As shown, the deposition chamber 100 is provided with a plurality of gas pipes (114a, 114b) for introducing the reactants into the deposition chamber 100, the number of gas pipes and the metal source introduced into the deposition chamber 100 and Depending on the number of nitrogen sources, ie the number of reactors, in the embodiment of the invention two gas lines 114a, 114b are installed.
이 2개의 가스관들(114a, 114b)은 그 한쪽 끝이 각각 금속소스의 공급원(미도시)과 질소소스의 공급원(미도시)에 연결되는데, 반도체 기판(104)상에 TiN막을 증착하는 경우에는 금속소스로는 TiCl4를 사용하고 질소소스로는 NH3를 사용한다. 한편, 가스관들(114a, 114b)의 다른쪽 끝은 증착실(100) 내에 안착된 반도체 기판(104)과 소정의 거리(도1의 D)만큼 떨어져 있는 샤워헤드(110)에 연결된다. 따라서, 가스 공급원(미도시)으로부터 공급되는 반응기체들은 가스관들(114a, 114b)과 가스관들(114a, 114b)의 끝에 연결된 샤워헤드(110)를 통하여 증착실(100)로 유입되어 서로 반응을 일으킴으로써 반도체 기판(104)상에 막을 형성한다.The two gas pipes 114a and 114b have their ends connected to a source of metal source (not shown) and a source of nitrogen source (not shown), respectively. In the case of depositing a TiN film on the semiconductor substrate 104, TiCl 4 is used as the metal source and NH 3 is used as the nitrogen source. Meanwhile, the other ends of the gas pipes 114a and 114b are connected to the showerhead 110 spaced apart from the semiconductor substrate 104 seated in the deposition chamber 100 by a predetermined distance (D in FIG. 1). Therefore, the reactants supplied from the gas source (not shown) flow into the deposition chamber 100 through the shower head 110 connected to the gas pipes 114a and 114b and the ends of the gas pipes 114a and 114b to react with each other. Thereby forming a film on the semiconductor substrate 104.
샤워헤드(110)는 반응기체들이 혼합되지 않은 상태로 증착실(100) 내에 유입되도록 하는 다단 샤워헤드가 바람직하며, 본 실시예에서는 2단 샤워헤드를 사용한다. 또한, 반응후의 잔류가스를 배기시키기 위한 퍼지가스를 증착실(100) 내로 공급하기 위하여 가스관들(114a, 114b)은 다기관(manifold)인 것이 바람직하다.Shower head 110 is preferably a multi-stage shower head to be introduced into the deposition chamber 100 in a state that the reactants are not mixed, in this embodiment uses a two-stage shower head. In addition, the gas pipes 114a and 114b are preferably manifolds to supply the purge gas for evacuating the residual gas after the reaction into the deposition chamber 100.
다기관의 각 가스 공급라인에는 밸브들(112)이 설치되어 밸브(112)들의 온/오프에 따라 증착실(100)내로 퍼지가스나 반응가스들을 유입하거나 또는 차단할 수 있다. 밸브들(112)은, 예를 들면 뉴매틱 밸브(pneumatic valve)와 같이, 미리 일정한 주기로 밸브의 온/오프를 제어할 수 있도록 프로그램된 제어부에 의해 조정되는 것이 바람직하다. 참조부호 102는 반도체 기판(104)을 가열하기 위한 히터이다.Valves 112 may be installed in each gas supply line of the manifold so that purge gas or reactant gases may be introduced into or blocked from the deposition chamber 100 according to on / off of the valves 112. The valves 112 are preferably adjusted by a controller that is programmed to control the on / off of the valve in advance at regular intervals, such as, for example, a pneumatic valve. Reference numeral 102 denotes a heater for heating the semiconductor substrate 104.
이하에서 도 1과 도 2를 참조하여, 상기와 같이 구성된 CVD장치의 증착실내에 안착된 반도체 기판에 본 발명에 따라 TiN과 같은 금속 질화물을 증착하는 방법을 상세히 설명한다.Hereinafter, a method of depositing a metal nitride such as TiN according to the present invention on a semiconductor substrate seated in a deposition chamber of a CVD apparatus configured as described above will be described in detail with reference to FIGS. 1 and 2.
먼저, 증착실(100)내로 반도체 기판(104)을 인입한다. 이 반도체 기판(104)은 금속배선 공정전의 장벽금속층을 형성하기 위하여 트랜지스터와 같은 개별소자가 그 표면에 이미 형성된 것일 수도 있다.(도 1 참조)First, the semiconductor substrate 104 is introduced into the deposition chamber 100. The semiconductor substrate 104 may be formed with an individual element such as a transistor already formed on its surface in order to form a barrier metal layer before the metallization process (see FIG. 1).
그리고, 다기관(114a)의 금속소스 공급라인을 통하여 TiCl4와 같은 금속소스를 증착실(100) 내로 ts시간 동안 유입한다. 한편, 원활한 가스의 흐름을 위하여 Ar이나 N2와 같은 운반가스를 금속소스와 함께 혼합하여 증착실(100) 내로 유입할 수 있다. 이 때, 금속소스를 유입시키기 위한 가스 공급라인(114a)의 밸브외의 다른 밸브들은 오프 상태에 있다. 따라서, 증착실(100) 내로는 TiCl4와 같은 금속소스만 유입된다. 이 때, 유입된 금속소스의 일부분은 기판(104) 표면에 화학적 및 물리적으로 흡착되고 나머지는 증착실(100) 내에 잔존한다. 이와 같이 반응가스들을 동시에 증착실(100) 내로 유입시키지 않고 한 종류의 가스만을 일정시간 동안 증착실(100)내로 유입시키는 방법을 이하에서 가스 펄싱이라 한다(도2의 타이밍도 참조).Then, a metal source such as TiCl 4 is introduced into the deposition chamber 100 through the metal source supply line of the manifold 114a for t s time. Meanwhile, a carrier gas such as Ar or N 2 may be mixed with a metal source to flow into the deposition chamber 100 for smooth gas flow. At this time, valves other than the valve of the gas supply line 114a for introducing the metal source are in an off state. Therefore, only a metal source such as TiCl 4 flows into the deposition chamber 100. At this time, a part of the introduced metal source is chemically and physically adsorbed to the surface of the substrate 104 and the remainder remains in the deposition chamber 100. As such, a method of introducing only one kind of gas into the deposition chamber 100 for a predetermined time without simultaneously introducing the reaction gases into the deposition chamber 100 is referred to as gas pulsing (see also timing in FIG. 2).
증착실(100) 내로 금속소스의 유입이 완료되면, 금속소스를 유입시키기 위한 가스 공급라인(114a)의 밸브를 닫은 후, 다기관(도1의 114a)의 퍼지가스 공급라인의 밸브를 열고 Ar이나 N2와 같은 퍼지가스를 tp시간 동안 증착실(100) 내로 유입시켜 샤워헤드(110) 및 증착실(100)내에 잔류하는 가스, 예컨대 TiCl4를 배기시킨다 (도2의 퍼지가스 펄싱 단계). 이때, 퍼지가스의 유량 및 증착실의 압력은 반도체 기판에 화학적 물리적으로 흡착된 금속소스가 분리되어 배기되지 않도록 적절히 조절하여, 증착실 내에 잔류한 소스가스만을 배기시키도록 한다.When the introduction of the metal source into the deposition chamber 100 is completed, close the valve of the gas supply line 114a for introducing the metal source, and then open the valve of the purge gas supply line of the manifold (114a of FIG. A purge gas such as N 2 is introduced into the deposition chamber 100 for t p time to exhaust the gas remaining in the showerhead 110 and the deposition chamber 100, for example, TiCl 4 (purge gas pulsing step of FIG. 2). . At this time, the flow rate of the purge gas and the pressure of the deposition chamber are appropriately adjusted so that the metal source that is chemically and physically adsorbed to the semiconductor substrate is not separated and exhausted so that only the source gas remaining in the deposition chamber is exhausted.
그리고, 다기관(114a)의 퍼지가스 공급라인의 밸브를 닫은 후, 다기관(114b)의 질소소스 공급라인의 밸브를 열고 NH3와 같은 질소소스를 tr시간 동안 증착실(100) 내로 유입시켜 기판(104)상에 화학적 물리적으로 흡착되어 있는 TiCl4와 같은 금속소스와 반응시키므로써 반도체 기판(104)상에 TiN과 같은 금속질화물을 형성시킨다. 즉, NH3와 같은 질소소스가 증착실(100) 내로 유입되기 전에 퍼지가스 펄싱 단계를 거치면서 증착실(100) 내에 잔존하는 TiCl4와 같은 금속소스는 펌프(도1 참조)에 의해 이미 배기된다. 따라서, NH3와 같은 질소소스는 반도체 기판(104)을 제외한 증착실(100)내에서는 TiCl4와 같은 금속소스와 반응하지 않는다. 따라서, TiCl4와 NH3가 흡착되어 있는 반도체 기판(104)에서만 TiN과 같은 금속질화물이 형성된다(도2의 NH3펄싱 단계).Then, after closing the valve of the purge gas supply line of the manifold 114a, the valve of the nitrogen source supply line of the manifold 114b is opened, and a nitrogen source such as NH 3 is introduced into the deposition chamber 100 for t r time, The metal nitride, such as TiN, is formed on the semiconductor substrate 104 by reacting with a metal source such as TiCl 4 which is chemically and physically adsorbed on the 104. That is, a metal source such as TiCl 4 remaining in the deposition chamber 100 is exhausted by a pump (see FIG. 1) while the nitrogen source, such as NH 3 , passes through the purge gas pulsing step before entering the deposition chamber 100. do. Therefore, the nitrogen source such as NH 3 does not react with the metal source such as TiCl 4 in the deposition chamber 100 except for the semiconductor substrate 104. Therefore, metal nitrides such as TiN are formed only in the semiconductor substrate 104 on which TiCl 4 and NH 3 are adsorbed (NH 3 pulsing step of FIG. 2).
이 때, 원활한 가스의 흐름을 위하여 Ar이나 N2와 같은 운반가스를 NH3와 같은 질소소스와 함께 혼합하여 증착실(100) 내로 유입할 수 있다.In this case, a carrier gas such as Ar or N 2 may be mixed with a nitrogen source such as NH 3 to flow into the deposition chamber 100 for smooth gas flow.
한편, 종래의 ALE에 의한 금속질화막 형성방법은 기판상에 물리적으로 흡착된 소스를 퍼지시켜 화학적으로 흡착된 소스만을 남기는 반면, 본 발명의 금속질화막 형성방법은 기판상에 화학적으로 흡착된 소스뿐만 아니라 물리적으로 흡착된 소스까지 남겨 반응시키는 점에서 근본적으로 다르다.On the other hand, the conventional method of forming the metal nitride film by ALE purges the source that is physically adsorbed on the substrate to leave only the chemically adsorbed source, whereas the method of forming the metal nitride film of the present invention is not only a chemically adsorbed source on the substrate It is fundamentally different in that it reacts by leaving a physically adsorbed source.
다음, 이미 설명한 퍼지가스 펄싱단계와 동일한 두 번째 퍼지가스 펄싱 단계를 거치면서, TiCl4와 반응이 완료되어 증착실(100) 내에 잔류하는 잉여분의 NH3를 배기한다(도2의 퍼지가스 펄싱 단계).Next, while passing through a second purge gas pulsing step identical to the purge gas pulsing step described above, the reaction with TiCl 4 is completed and the excess NH 3 remaining in the deposition chamber 100 is exhausted (the purge gas pulsing step of FIG. 2). ).
한편, 증착실(100) 내의 압력을 조절하기 위하여 상기 각 단계를 진행하는 동안, Ar이나 N2와 같은 분위기 가스를 증착실(100) 내로 계속 공급하는 것이 바람직하다.On the other hand, during the above steps to adjust the pressure in the deposition chamber 100, it is preferable to continue to supply the atmosphere gas, such as Ar or N 2 into the deposition chamber 100.
이와 같이 본 발명에 따른 가스펄싱을 이용한 금속질화막 형성방법은, TiCl4펄싱 단계→퍼지가스 펄싱 단계→NH3펄싱 단계→퍼지가스 펄싱 단계로 이루어진 하나의 사이클을 거치면서 일정한 두께의 TiN과 같은 금속질화막이 증착된다. 증착속도는 대략 20Å/cycle로서, 이 사이클을 반복하면 박막의 두께가 비례적으로 증가하기 때문에 사이클의 반복을 통하여 원하는 두께의 박막을 반도체 기판(100)에 증착할 수 있다. 이 때, 하나의 사이클당 증착되는 금속질화막의 두께는 증착실(100) 내로 유입되는 금속소스의 유량과 질소소스의 유량 및 가스 펄싱 시간, 퍼지 가스의 유량 및 퍼지 시간에 따라 결정된다.As described above, the method of forming a metal nitride film using gas pulsing according to the present invention includes a metal such as TiN having a constant thickness while passing through one cycle consisting of a TiCl 4 pulsing step → purge gas pulsing step → NH 3 pulsing step → purge gas pulsing step. A nitride film is deposited. The deposition rate is approximately 20 mW / cycle, and since the thickness of the thin film is proportionally increased when the cycle is repeated, a thin film having a desired thickness may be deposited on the semiconductor substrate 100 through repeated cycles. At this time, the thickness of the metal nitride film deposited per cycle is determined according to the flow rate of the metal source flowing into the deposition chamber 100, the flow rate of the nitrogen source and gas pulsing time, the flow rate of the purge gas and the purge time.
이하에서는 본 발명에 따라 TiN막을 형성하는 실험예들을 기술한다.Hereinafter, experimental examples of forming a TiN film according to the present invention will be described.
실험예1Experimental Example 1
히터(도1의 102)를 작동시켜 반도체 기판(104)의 온도를 500℃ 이하의 낮은 온도로 유지하면서 반도체 기판(104)상에 다음과 같은 반응조건 하에서 상기의 가스 펄싱단계들로 구성된 사이클에 따라 TiN막을 증착한다.In the cycle consisting of the above gas pulsing steps on the semiconductor substrate 104 under the following reaction conditions while maintaining the temperature of the semiconductor substrate 104 at a temperature lower than 500 ° C by operating the heater 102 (Fig. 1). Accordingly a TiN film is deposited.
증착조건Deposition Conditions
목표물질 : TiNTarget substance: TiN
분위기 가스 : ArAtmosphere Gas: Ar
증착실 내의 압력 : 1-20TorrPressure in Deposition Chamber: 1-20Torr
금속소스, 질소소스 : TiCl4,NH3 Metal source, nitrogen source: TiCl 4 , NH 3
TiCl4유량, TiCl4펄싱 시간(ts) : 1-5sccm, 5secTiCl 4 flow rate, TiCl 4 pulsing time (t s ): 1-5sccm, 5sec
NH3유량, NH3펄싱 시간(tr): 5-30sccm, 5secNH 3 flow rate, NH 3 pulsing time (t r ): 5-30 sccm, 5sec
퍼지가스, 퍼지가스 유량, 퍼지 시간(tp) : Ar, 10-100sccm, 10secPurge gas, purge gas flow rate, purge time (t p ): Ar, 10-100sccm, 10sec
운반가스, 운반가스 유량 : Ar, 10-100sccmCarrier Gas, Carrier Gas Flow Rate: Ar, 10-100sccm
1 사이클당 시간(tt) : 30secTime per Cycle (t t ): 30sec
이러한 조건에서 반도체 기판(104)에 증착된 TiN박막의 상태를 RBS법으로 확인한 결과를 도3에 도시하였다. 도3에서 횡축의 채널은 MCA(Mutilple Channel Analyzer)의 각각의 채널을 나타내는 것으로서, 에너지 단위인 eV와는 eV=4.05×채널+59.4의 관계에 있다. 또한 도3의 종축은 MCA에 의해 검출된 원소들의 규격화된 수율을 나타낸다.The results of confirming the state of the TiN thin film deposited on the semiconductor substrate 104 under such conditions by the RBS method are shown in FIG. In FIG. 3, the horizontal channel represents each channel of the MCA (Mutilple Channel Analyzer), and has eV = 4.05 × channel + 59.4 with eV, which is an energy unit. In addition, the vertical axis of FIG. 3 represents the normalized yield of elements detected by MCA.
위와 같은 조건으로 반도체 기판(104)에 증착되어 형성된 TiN막은 TiN 특유의 금색빛을 띠고 있으며, 도 3에 도시된 바와 같이 Ti:N=1:1의 완벽한 조성을 갖는다. TiN박막 내에 함유되어 있는 Cl은 도 3에 도시된 바와 같이 RBS법에 의한 검출한계(detection limit)인 TiN박막 내에 함유되어 있는 전체 원소 대비 0.3% 이하이다. 또한, 위와 같은 조건으로 반도체 기판(104)에 증착되어 형성된 TiN막의 비저항은 그 측정값이 130μΩ-cm 정도의 낮은 값을 갖고 있었다. 한편, 수회의 실험에 따르면, 이와 같은 우수한 박막 특성을 갖기 위해서는 1 사이클당 증착되는 TiN박막의 두께가 20Å이하가 되어야 함을 확인하였다.The TiN film deposited on the semiconductor substrate 104 under the same conditions as described above has a gold color characteristic of TiN, and has a perfect composition of Ti: N = 1: 1 as shown in FIG. 3. Cl contained in the TiN thin film is 0.3% or less than the total elements contained in the TiN thin film, which is a detection limit by the RBS method, as shown in FIG. 3. In addition, the specific resistance of the TiN film deposited and formed on the semiconductor substrate 104 under the above conditions had a low value of about 130 Ω-cm. On the other hand, according to several experiments, it was confirmed that in order to have such excellent thin film characteristics, the thickness of the TiN thin film deposited per cycle should be 20 mW or less.
한편, 도 4 및 도 5는 각각 질소소스(NH3)의 유량과 증착실 압력을 변화시켜 가면서 본 발명의 방법에 따라 증착되는 TiN막의 비저항 및 증착속도를 측정한 결과를 도시한 것이다. 도 4 및 도 5에 도시된 바와 같이, 증착속도는 NH3의 유량 및 증착실 압력의 증가에 따라 증가하지만, 그에 따라 비저항도 증가한다. 따라서, 금속질화막의 응용처에 따라 요구되는 두께, 증착속도 및 비저항을 모두 고려하여 증착조건을 설정한다.4 and 5 show the results of measuring the specific resistance and the deposition rate of the TiN film deposited according to the method of the present invention while varying the flow rate and the deposition chamber pressure of the nitrogen source (NH 3 ), respectively. As shown in Figs. 4 and 5, the deposition rate increases with increasing flow rate of NH 3 and deposition chamber pressure, but the resistivity also increases accordingly. Therefore, the deposition conditions are set in consideration of all the required thickness, deposition rate, and specific resistance according to the application of the metal nitride film.
실험예2Experimental Example 2
다음 표 1과 같은 네 가지의 증착조건하에서 사이클당 증착속도, 사이클 수의 증가에 따른 증착되는 TiN막의 두께와 증착속도, 증착온도의 변화에 따른 비저항을 측정하였다. 여기서 금속소스는 TiCl4이고, 질소소스는 NH3, 퍼지가스는 Ar을 사용하였다.In the four deposition conditions shown in Table 1 below, the deposition rate per cycle, the thickness of the TiN film deposited as the number of cycles increased, the deposition rate, and the specific resistance according to the change in the deposition temperature were measured. The metal source is TiCl 4 , the nitrogen source is NH 3 , the purge gas is Ar.
위의 각 증착조건별로 사이클당 증착속도는 대략 다음과 같았다.The deposition rate per cycle for each of the above deposition conditions was approximately as follows.
TiN 00 : 20Å/cycle(한 사이클이 20초이므로 60Å/min)TiN 00: 20ms / cycle (60ms / min since one cycle is 20 seconds)
TiN 01 : 2Å/cycle(한 사이클이 12초이므로 10Å/min)TiN 01: 2ms / cycle (10ms / min since one cycle is 12 seconds)
TiN 02 : 3.5Å/cycle(한 사이클이 8초이므로 26.3Å/min)TiN 02: 3.5mW / cycle (26.3mW / min because one cycle is 8 seconds)
TiN 03 : 6Å/cycle(한 사이클이 8초이므로 45Å/min)TiN 03: 6Å / cycle (45Å / min because one cycle is 8 seconds)
또한, 도 6 및 도 7은 각각 사이클 수의 증가에 따른 증착되는 두께 및 증착속도를 도시한 것이다. 단, 여기서 증착온도는 500℃로 하였다. 도면에서 알 수 있듯이, 사이클 수를 증가할수록 증착속도는 완만하게 증가하고(도 7), 증착되는 두께는 그에 비례하여 증가한다. 따라서, 일정한 증착조건에서 사이클 수를 조절함에 따라 증착되는 TiN막의 두께를 조절할 수 있다.6 and 7 show the deposition thickness and deposition rate as the number of cycles increases, respectively. However, the deposition temperature here was 500 ° C. As can be seen from the figure, as the number of cycles is increased, the deposition rate slowly increases (Fig. 7), and the deposited thickness increases in proportion. Therefore, the thickness of the deposited TiN film can be adjusted by controlling the number of cycles under constant deposition conditions.
그리고, 도 8은 위의 네 가지 증착조건별로 증착온도에 따른 TiN막의 비저항을 측정한 결과를 도시한 그래프이다. 이를 보면, 증착온도가 증가함에 따라 비저항은 감소하고, 특히 증착속도가 높은 증착조건(TiN 00)에서 비저항이 급격히 감소함을 알 수 있다. 또한 대략 500℃에서 네 가지 모든 증착조건에서 200μΩ-cm 이하의 비저항이 얻어짐을 알 수 있다.8 is a graph showing the results of measuring the specific resistance of the TiN film according to the deposition temperature for each of the above four deposition conditions. As a result, it can be seen that as the deposition temperature increases, the resistivity decreases, and in particular, the resistivity decreases rapidly in the deposition condition (TiN 00) where the deposition rate is high. In addition, it can be seen that the specific resistance of 200 μ 200-cm or less is obtained in all four deposition conditions at approximately 500 ° C.
다음으로, 본 발명의 금속질화막 형성방법을 비아컨택에 적용한 예를, 첨부한 도 10a 내지 도 11f를 참조하여, 상세히 설명한다.Next, an example in which the metal nitride film forming method of the present invention is applied to a via contact will be described in detail with reference to FIGS. 10A to 11F.
먼저, 도 10a와 같이 반도체 기판(200) 위에 Al 등으로 이루어진 제1금속층(210)을 형성하고 그 위에 캡핑막으로서 TiN막(220)을 증착한다. 이 TiN막(220)은 스퍼터링 방법으로 증착할 수 있다. 이어서, 층간절연막(230)을 적층하고 비아를 형성할 부위를 식각하면 도 10b와 같이 된다. 여기에 장벽금속층인 TiN막을 증착하기 전에 TiN막의 접착특성을 좋게 하기 위해 Ti막을 얇게 형성한다. 이 Ti막도 스퍼터링 방법으로 형성할 수 있다.First, as shown in FIG. 10A, a first metal layer 210 made of Al or the like is formed on a semiconductor substrate 200, and a TiN film 220 is deposited as a capping film thereon. The TiN film 220 can be deposited by a sputtering method. Subsequently, when the interlayer insulating layer 230 is stacked and a portion where the via is to be formed is etched, as shown in FIG. 10B. Before the TiN film, which is a barrier metal layer, is deposited, a thin Ti film is formed to improve the adhesion characteristics of the TiN film. This Ti film can also be formed by a sputtering method.
이어서, 상술한 본 발명의 금속질화막 형성방법에 따라 장벽금속층인 TiN막을 증착하면 도 10c와 같이 된다. 즉, 금속소스로는 TiCl4를 사용하고 질소소스는 NH3를 사용하여 상술한 바와 같이, 도1과 같은 증착장치 내에서 금속소스→퍼지가스→질소소스→퍼지가스의 순으로 유입하여 원하는 두께를 얻을 때까지 반복한다. 금속소스, 질소소스 및 퍼지가스의 유량은 각각 1∼5sccm, 5∼200sccm 및 10∼200sccm으로 하고 각각의 유입시간은 1∼10초 정도로 한다. 증착온도는 480℃ 이하로 하고, 증착실 압력은 1∼20torr로 하며, 필요하면 Ar, He 또는 N2등의 분위기 가스, Ar, N2등의 운반가스를 사용할 수 있다. 이러한 증착조건들은 증착장치, 증착속도, 증착되는 TiN막의 두께 및 비저항을 고려하여 적절히 조절한다.Subsequently, when the TiN film, which is a barrier metal layer, is deposited according to the metal nitride film forming method of the present invention described above, as shown in FIG. 10C. That is, TiCl 4 is used as the metal source, and NH 3 is used as the nitrogen source. As described above, in the deposition apparatus as shown in FIG. 1, the metal source → purge gas → nitrogen source → purge gas is introduced into the desired thickness. Repeat until you get it. The flow rates of the metal source, the nitrogen source and the purge gas are 1 to 5 sccm, 5 to 200 sccm and 10 to 200 sccm, respectively, and the inflow time is about 1 to 10 seconds. The deposition temperature is 480 ° C. or lower, the deposition chamber pressure is 1-20 torr, and if necessary, an atmosphere gas such as Ar, He or N 2 , and a carrier gas such as Ar, N 2 can be used. These deposition conditions are appropriately adjusted in consideration of the deposition apparatus, deposition rate, thickness and specific resistance of the deposited TiN film.
이어서, 통상의 방법으로 W 등으로 이루어진 금속플러그(250)를 형성하고(도10d), 화학기계적 연마나 에치백으로 층간절연막(235) 윗면에 증착된 금속을 제거한(도10e) 후, 그 위에 제2금속층(260)을 형성하면(도10f) 금속층간 연결이 이루어진다.Subsequently, a metal plug 250 made of W or the like is formed by a conventional method (FIG. 10D), and the metal deposited on the upper surface of the interlayer insulating film 235 is removed by chemical mechanical polishing or etch back (FIG. 10E), and thereon. When the second metal layer 260 is formed (FIG. 10F), the metal layers are connected.
한편, 도 11a 내지 도 11f는 앵커비아컨택을 형성하는 과정을 도시한 단면도들로서, 상기한 도 10a 내지 도 10f의 과정과 기본적으로 동일한 과정을 거치나, 도 11b에서 보듯이, 접촉면적을 넓혀 저항을 낮추기 위해 컨택홀의 하부에 앵커(A)를 형성한 점이 다르다. 앵커(A)는 도 11a와 같이 컨택홀을 형성한 후에 층간절연막(335)을 습식식각함으로써 형성된다. 그밖의 과정은 상기한 도 10a 내지 도 10f의 과정과 동일하므로 상세한 설명은 생략한다.11A to 11F are cross-sectional views illustrating a process of forming an anchor via contact, and are basically the same as those of FIGS. 10A to 10F. However, as shown in FIG. 11B, the contact area is increased by resistance. Anchor (A) is formed at the bottom of the contact hole to lower the difference. The anchor A is formed by wet etching the interlayer insulating film 335 after forming the contact hole as shown in FIG. 11A. Since other processes are the same as those of FIGS. 10A to 10F, detailed descriptions thereof will be omitted.
이와 같이 본 발명에 의한 금속질화막 형성방법을 비아컨택에 적용하면 저온에서 단차도포성이 좋은 장벽금속층을 얻을 수 있어, 도 9a 및 도 9b에 도시된 TiFx나 AlFx와 같은 컨택불량(X)을 방지할 수 있다.As described above, when the method of forming the metal nitride film according to the present invention is applied to a via contact, a barrier metal layer having good step coverage at low temperatures can be obtained, and contact defects (X) such as TiF x or AlF x shown in FIGS. 9A and 9B are obtained. Can be prevented.
실험예3Experimental Example 3
다음과 같이 폭이 다른 컨택홀에 스퍼터링에 의한 Ti막을 100Å 두께로 증착한 후, 본 발명의 방법에 의한 장벽금속층으로서 TiN막 및 종래의 방법인 스퍼터링에 의한 콜리메이션(collimation)된 TiN막을 서로 다른 두께로 증착하고, CVD-W으로 플러그를 형성한 경우에 비아저항을 측정하였다. 단, 본 발명에 의한 TiN막의 증착조건은 450℃의 증착온도와 그밖에 전술한 실험예2의 TiN 00의 증착조건으로 하였다.After depositing a Ti film by sputtering to a thickness of 100 에 in a contact hole having a different width as follows, the TiN film as a barrier metal layer according to the method of the present invention and a collimated TiN film by sputtering as a conventional method are different from each other. Via resistance was measured when deposited to a thickness and a plug was formed by CVD-W. However, the deposition conditions of the TiN film according to the present invention were the deposition temperature of 450 ° C. and the TiN 00 deposition conditions of Experimental Example 2 described above.
비아폭 : 0.24, 0.32, 0.39μm(층간절연막의 단차 : 0.9μm)Via width: 0.24, 0.32, 0.39 μm (step difference of interlayer insulating film: 0.9 μm)
TiN막의 두께 : 100, 200, 400, 600Å(이상 본 발명의 방법에 의해 증착),Thickness of the TiN film: 100, 200, 400, 600 kPa (deposited by the method of the present invention),
700Å(콜리메이션 TiN)700Å (Collision TiN)
측정결과, 도 12에 도시된 바와 같이 전체적으로 비아폭이 증가할수록 저항이 감소하고, 본 발명에 의한 TiN막(PCVD-TiN)의 두께가 작을수록 저항이 작은 것으로 나타났다. 비교대상인 콜리메이션 TiN막과 비교하면, 100Å 두께의 본 발명에 의한 TiN막의 저항이 비슷하게 나타났다. 특히, 비아폭이 0.39μm일 때는 위의 다섯 가지 TiN막의 비아저항이 모두 비슷하게 나타났다. 한편 PCVD-TiN막은 실험예2의 결과와 도 8에서 보듯이 사이클당 증착속도가 빠르고(20Å/cycle) 비저항이 큰(450℃에서 300μΩ-cm) 증착조건으로 형성하였음을 고려할 때, 이보다 증착속도가 좀더 느리고 비저항이 작은 조건으로 형성한다면 비아저항은 크게 개선될 수 있음을 알 수 있다.As a result, as shown in FIG. 12, the resistance decreases as the via width increases, and the smaller the thickness of the TiN film (PCVD-TiN) according to the present invention, the smaller the resistance. Compared with the collimated TiN film to be compared, the resistance of the TiN film according to the present invention having a thickness of 100 Å was similar. In particular, when the via width was 0.39 μm, the via resistances of the above five TiN films were similar. On the other hand, considering that the PCVD-TiN film was formed under a deposition condition having a high deposition rate per cycle (20 μs / cycle) and a high resistivity (300 μΩ-cm at 450 ° C.) as shown in the results of Experimental Example 2 and FIG. 8, the deposition rate was higher than this. It can be seen that the via resistance can be greatly improved if is formed at a slower and smaller resistivity condition.
또한, 도 13은 비아폭이 0.39μm일 때 각 TiN막의 비아저항의 분포를 나타낸 그래프로서, 콜리메이션 TiN막과 본 발명에 의한 PCVD-TiN막 모두가 1.0Ω을 전후하여 큰 차이없이 고르게 분포함을 알 수 있다.FIG. 13 is a graph showing the distribution of the via resistance of each TiN film when the via width is 0.39 μm, in which both the collimation TiN film and the PCVD-TiN film according to the present invention are evenly distributed around 1.0 Ω without significant difference. It can be seen.
이상 TiCl4및 NH3를 전구체로 사용하여 금속질화막으로서 TiN막을 형성하는 것에 대해 설명하였으나, 본 발명은 상기한 TiCl4뿐만 아니라 TiCl3, TiI4, TiBr2, TiF4, (C5H5)2TiCl2, ((CH3)5C5)2TiCl2, C5H5TiCl3, C9H10BCl3N6Ti, C9H7TiCl3, (C5(CH3)5)TiCl3, TiCl4(NH3)2, (CH3)5C5Ti(CH3)3, TDEAT 또는 TDMAT를 전구체로 사용한 TiN막뿐만 아니라, TaBr5, TaCl5, TaF5, TaI5및 (C5(CH3)5)TaCl4를 전구체로 사용한 TaN막 등의 금속질화막 및 나아가서 CVD 방법을 사용하여 증착되는 대부분의 물질층에 적용할 수 있다.As described above, the formation of the TiN film as the metal nitride film using TiCl 4 and NH 3 as precursors, but the present invention is not only TiCl 4 but also TiCl 3 , TiI 4 , TiBr 2 , TiF 4 , (C 5 H 5 ) 2 TiCl 2 , ((CH 3 ) 5 C 5 ) 2 TiCl 2 , C 5 H 5 TiCl 3 , C 9 H 10 BCl 3 N 6 Ti, C 9 H 7 TiCl 3 , (C 5 (CH 3 ) 5 ) TiCl 3, TiCl 4 (NH 3 ) 2, (CH 3) 5 C 5 Ti (CH 3) 3, as well as a TiN film with TDEAT or TDMAT as a precursor, TaBr 5, TaCl 5, TaF 5, TaI 5 , and ( It can be applied to metal nitride films such as TaN films using C 5 (CH 3 ) 5 ) TaCl 4 as precursors, and most of the material layers deposited using the CVD method.
다만, TDEAT나 TDMAT를 전구체로 사용하여 TiN막을 형성할 때는 다른 전구체를 사용한 경우와는 달리 증착온도와 압력을 250∼400℃, 0.1∼10torr 정도로 하는 것이 바람직하고, 위에 열거한 TaN막을 형성하기 위한 전구체들은 모두 고체이므로 소스가스를 형성할 때, 고체용 버블러(bubble)를 사용해야 한다는 점이 다르다.However, when forming a TiN film using TDEAT or TDMAT as a precursor, it is preferable to set the deposition temperature and pressure to about 250 to 400 ° C. and about 0.1 to 10 torr, unlike other precursors, and to form the TaN films listed above. Since the precursors are all solids, the difference is that a bubbler for solids must be used to form the source gas.
이상에서 살펴본 바와 같이 본 발명에 따른 금속질화막 형성방법에 따르면, 단차도포성이 우수하면서도 200μΩ-㎝이하의 낮은 비저항과 낮은 Cl 함량을 갖는 금속질화막을 얻을 수 있다. 그리고 500℃ 이하의 저온에서 금속질화막을 형성하는 것이 가능하면서도 증착속도가 대략 20Å/cycle로서 성장속도가 0.25Å/cycle인 ALE에 의한 금속질화막 형성방법에 비하여 증착속도가 훨씬 빠르다.As described above, according to the method of forming the metal nitride film according to the present invention, it is possible to obtain a metal nitride film having excellent step coverage and low resistivity and low Cl content of 200 μm-cm or less. In addition, it is possible to form the metal nitride film at a low temperature of 500 ° C. or lower, but the deposition rate is about 20 μs / cycle, and the deposition rate is much faster than the method of forming the metal nitride film by ALE having a growth rate of 0.25 μs / cycle.
따라서 650℃ 이상의 고온에서 증착된 금속질화막의 문제점인 금속질화막에 불순물로 남아있는 Cl로 인한 금속배선의 부식문제와 높은 비저항의 문제를 해결할 수 있으므로 종횡비가 크고 저온이 요구되는 비아컨택에 적용할 수 있고, ALE에 의한 금속질화막 형성방법에 비하여 증착속도가 빠르기 때문에 대량생산이 요구되는 반도체소자의 제조공정에 적합하다.Therefore, it is possible to solve the problem of corrosion of metal wiring due to Cl remaining as an impurity in the metal nitride film and the problem of high resistivity, which is a problem of the metal nitride film deposited at a high temperature of 650 ° C. or higher, and thus it can be applied to a via contact requiring a high aspect ratio and low temperature. In addition, since the deposition rate is faster than that of the metal nitride film forming method by ALE, it is suitable for the manufacturing process of semiconductor devices requiring mass production.
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| JP27566498A JP3998830B2 (en) | 1997-09-29 | 1998-09-29 | Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using the same |
| US09/765,531 US6348376B2 (en) | 1997-09-29 | 2001-01-19 | Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact and capacitor of semiconductor device using the same |
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| KR20030044140A (en) * | 2001-11-28 | 2003-06-09 | 주식회사 하이닉스반도체 | Method of forming a tantalum nitride layer and semiconductor device utilizing thereof |
| KR100480914B1 (en) * | 2002-08-05 | 2005-04-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100671612B1 (en) * | 2000-06-30 | 2007-01-18 | 주식회사 하이닉스반도체 | Apparatus for depositing metal and a method for forming a metal layer using the same |
| KR100668738B1 (en) * | 2004-12-30 | 2007-01-26 | 주식회사 하이닉스반도체 | Forming method of titanium nitride layer and deposition apparatus of titanium nitride layer |
| KR20180120097A (en) * | 2017-04-26 | 2018-11-05 | 도쿄엘렉트론가부시키가이샤 | Method of forming tungsten film |
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| KR20160071026A (en) | 2014-12-11 | 2016-06-21 | 주식회사 유진테크 머티리얼즈 | Organo group 14 metalloid azide precursors and method for dipositing thin film using thereof |
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| KR100671612B1 (en) * | 2000-06-30 | 2007-01-18 | 주식회사 하이닉스반도체 | Apparatus for depositing metal and a method for forming a metal layer using the same |
| KR20030044140A (en) * | 2001-11-28 | 2003-06-09 | 주식회사 하이닉스반도체 | Method of forming a tantalum nitride layer and semiconductor device utilizing thereof |
| KR100480914B1 (en) * | 2002-08-05 | 2005-04-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100668738B1 (en) * | 2004-12-30 | 2007-01-26 | 주식회사 하이닉스반도체 | Forming method of titanium nitride layer and deposition apparatus of titanium nitride layer |
| KR20180120097A (en) * | 2017-04-26 | 2018-11-05 | 도쿄엘렉트론가부시키가이샤 | Method of forming tungsten film |
| US10886170B2 (en) | 2017-04-26 | 2021-01-05 | Tokyo Electron Limited | Method of forming tungsten film |
| KR20200024851A (en) * | 2017-06-29 | 2020-03-09 | 가부시키가이샤 아데카 | Raw material for thin film formation, method for manufacturing thin film and new compound |
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